1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Copyright (C) 2003-2006, Advanced Micro Devices, Inc.
8 /* driver logic flags */
10 #define AES_MODE_CBC 1
12 #define AES_DIR_DECRYPT 0
13 #define AES_DIR_ENCRYPT 1
15 #define AES_FLAGS_HIDDENKEY (1 << 0)
17 /* Register definitions */
19 #define AES_CTRLA_REG 0x0000
21 #define AES_CTRL_START 0x01
22 #define AES_CTRL_DECRYPT 0x00
23 #define AES_CTRL_ENCRYPT 0x02
24 #define AES_CTRL_WRKEY 0x04
25 #define AES_CTRL_DCA 0x08
26 #define AES_CTRL_SCA 0x10
27 #define AES_CTRL_CBC 0x20
29 #define AES_INTR_REG 0x0008
31 #define AES_INTRA_PENDING (1 << 16)
32 #define AES_INTRB_PENDING (1 << 17)
34 #define AES_INTR_PENDING (AES_INTRA_PENDING | AES_INTRB_PENDING)
35 #define AES_INTR_MASK 0x07
37 #define AES_SOURCEA_REG 0x0010
38 #define AES_DSTA_REG 0x0014
39 #define AES_LENA_REG 0x0018
40 #define AES_WRITEKEY0_REG 0x0030
41 #define AES_WRITEIV0_REG 0x0040
43 /* A very large counter that is used to gracefully bail out of an
44 * operation in case of trouble
47 #define AES_OP_TIMEOUT 0x50000
49 struct geode_aes_tfm_ctx
{
50 u8 key
[AES_KEYSIZE_128
];
52 struct crypto_skcipher
*skcipher
;
53 struct crypto_cipher
*cip
;