drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #define nv40_instmem(p) container_of((p), struct nv40_instmem, base)
  25 #include "priv.h"
  26
  27 #include <core/ramht.h>
  28 #include <engine/gr/nv40.h>
  29
  30 struct nv40_instmem {
  31         struct nvkm_instmem base;
  32         struct nvkm_mm heap;
  33         void __iomem *iomem;
  34 };
  35
  36 /******************************************************************************
  37  * instmem object implementation
  38  *****************************************************************************/
  39 #define nv40_instobj(p) container_of((p), struct nv40_instobj, base.memory)
  40
  41 struct nv40_instobj {
  42         struct nvkm_instobj base;
  43         struct nv40_instmem *imem;
  44         struct nvkm_mm_node *node;
  45 };
  46
  47 static void
  48 nv40_instobj_wr32(struct nvkm_memory *memory, u64 offset, u32 data)
  49 {
  50         struct nv40_instobj *iobj = nv40_instobj(memory);
  51         iowrite32_native(data, iobj->imem->iomem + iobj->node->offset + offset);
  52 }
  53
  54 static u32
  55 nv40_instobj_rd32(struct nvkm_memory *memory, u64 offset)
  56 {
  57         struct nv40_instobj *iobj = nv40_instobj(memory);
  58         return ioread32_native(iobj->imem->iomem + iobj->node->offset + offset);
  59 }
  60
  61 static const struct nvkm_memory_ptrs
  62 nv40_instobj_ptrs = {
  63         .rd32 = nv40_instobj_rd32,
  64         .wr32 = nv40_instobj_wr32,
  65 };
  66
  67 static void
  68 nv40_instobj_release(struct nvkm_memory *memory)
  69 {
  70         wmb();
  71 }
  72
  73 static void __iomem *
  74 nv40_instobj_acquire(struct nvkm_memory *memory)
  75 {
  76         struct nv40_instobj *iobj = nv40_instobj(memory);
  77         return iobj->imem->iomem + iobj->node->offset;
  78 }
  79
  80 static u64
  81 nv40_instobj_size(struct nvkm_memory *memory)
  82 {
  83         return nv40_instobj(memory)->node->length;
  84 }
  85
  86 static u64
  87 nv40_instobj_addr(struct nvkm_memory *memory)
  88 {
  89         return nv40_instobj(memory)->node->offset;
  90 }
  91
  92 static enum nvkm_memory_target
  93 nv40_instobj_target(struct nvkm_memory *memory)
  94 {
  95         return NVKM_MEM_TARGET_INST;
  96 }
  97
  98 static void *
  99 nv40_instobj_dtor(struct nvkm_memory *memory)
 100 {
 101         struct nv40_instobj *iobj = nv40_instobj(memory);
 102         mutex_lock(&iobj->imem->base.subdev.mutex);
 103         nvkm_mm_free(&iobj->imem->heap, &iobj->node);
 104         mutex_unlock(&iobj->imem->base.subdev.mutex);
 105         nvkm_instobj_dtor(&iobj->imem->base, &iobj->base);
 106         return iobj;
 107 }
 108
 109 static const struct nvkm_memory_func
 110 nv40_instobj_func = {
 111         .dtor = nv40_instobj_dtor,
 112         .target = nv40_instobj_target,
 113         .size = nv40_instobj_size,
 114         .addr = nv40_instobj_addr,
 115         .acquire = nv40_instobj_acquire,
 116         .release = nv40_instobj_release,
 117 };
 118
 119 static int
 120 nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
 121                  struct nvkm_memory **pmemory)
 122 {
 123         struct nv40_instmem *imem = nv40_instmem(base);
 124         struct nv40_instobj *iobj;
 125         int ret;
 126
 127         if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL)))
 128                 return -ENOMEM;
 129         *pmemory = &iobj->base.memory;
 130
 131         nvkm_instobj_ctor(&nv40_instobj_func, &imem->base, &iobj->base);
 132         iobj->base.memory.ptrs = &nv40_instobj_ptrs;
 133         iobj->imem = imem;
 134
 135         mutex_lock(&imem->base.subdev.mutex);
 136         ret = nvkm_mm_head(&imem->heap, 0, 1, size, size,
 137                            align ? align : 1, &iobj->node);
 138         mutex_unlock(&imem->base.subdev.mutex);
 139         return ret;
 140 }
 141
 142 /******************************************************************************
 143  * instmem subdev implementation
 144  *****************************************************************************/
 145
 146 static u32
 147 nv40_instmem_rd32(struct nvkm_instmem *base, u32 addr)
 148 {
 149         return ioread32_native(nv40_instmem(base)->iomem + addr);
 150 }
 151
 152 static void
 153 nv40_instmem_wr32(struct nvkm_instmem *base, u32 addr, u32 data)
 154 {
 155         iowrite32_native(data, nv40_instmem(base)->iomem + addr);
 156 }
 157
 158 static int
 159 nv40_instmem_oneinit(struct nvkm_instmem *base)
 160 {
 161         struct nv40_instmem *imem = nv40_instmem(base);
 162         struct nvkm_device *device = imem->base.subdev.device;
 163         int ret, vs;
 164
 165         /* PRAMIN aperture maps over the end of vram, reserve enough space
 166          * to fit graphics contexts for every channel, the magics come
 167          * from engine/gr/nv40.c
 168          */
 169         vs = hweight8((nvkm_rd32(device, 0x001540) & 0x0000ff00) >> 8);
 170         if      (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs;
 171         else if (device->chipset  < 0x43) imem->base.reserved = 0x4f00 * vs;
 172         else if (nv44_gr_class(device))   imem->base.reserved = 0x4980 * vs;
 173         else                              imem->base.reserved = 0x4a40 * vs;
 174         imem->base.reserved += 16 * 1024;
 175         imem->base.reserved *= 32;              /* per-channel */
 176         imem->base.reserved += 512 * 1024;      /* pci(e)gart table */
 177         imem->base.reserved += 512 * 1024;      /* object storage */
 178         imem->base.reserved = round_up(imem->base.reserved, 4096);
 179
 180         ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1);
 181         if (ret)
 182                 return ret;
 183
 184         /* 0x00000-0x10000: reserve for probable vbios image */
 185         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false,
 186                               &imem->base.vbios);
 187         if (ret)
 188                 return ret;
 189
 190         /* 0x10000-0x18000: reserve for RAMHT */
 191         ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht);
 192         if (ret)
 193                 return ret;
 194
 195         /* 0x18000-0x18200: reserve for RAMRO
 196          * 0x18200-0x20000: padding
 197          */
 198         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x08000, 0, false,
 199                               &imem->base.ramro);
 200         if (ret)
 201                 return ret;
 202
 203         /* 0x20000-0x21000: reserve for RAMFC
 204          * 0x21000-0x40000: padding and some unknown crap
 205          */
 206         ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x20000, 0, true,
 207                               &imem->base.ramfc);
 208         if (ret)
 209                 return ret;
 210
 211         return 0;
 212 }
 213
 214 static void *
 215 nv40_instmem_dtor(struct nvkm_instmem *base)
 216 {
 217         struct nv40_instmem *imem = nv40_instmem(base);
 218         nvkm_memory_unref(&imem->base.ramfc);
 219         nvkm_memory_unref(&imem->base.ramro);
 220         nvkm_ramht_del(&imem->base.ramht);
 221         nvkm_memory_unref(&imem->base.vbios);
 222         nvkm_mm_fini(&imem->heap);
 223         if (imem->iomem)
 224                 iounmap(imem->iomem);
 225         return imem;
 226 }
 227
 228 static const struct nvkm_instmem_func
 229 nv40_instmem = {
 230         .dtor = nv40_instmem_dtor,
 231         .oneinit = nv40_instmem_oneinit,
 232         .rd32 = nv40_instmem_rd32,
 233         .wr32 = nv40_instmem_wr32,
 234         .memory_new = nv40_instobj_new,
 235         .zero = false,
 236 };
 237
 238 int
 239 nv40_instmem_new(struct nvkm_device *device, int index,
 240                  struct nvkm_instmem **pimem)
 241 {
 242         struct nv40_instmem *imem;
 243         int bar;
 244
 245         if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
 246                 return -ENOMEM;
 247         nvkm_instmem_ctor(&nv40_instmem, device, index, &imem->base);
 248         *pimem = &imem->base;
 249
 250         /* map bar */
 251         if (device->func->resource_size(device, 2))
 252                 bar = 2;
 253         else
 254                 bar = 3;
 255
 256         imem->iomem = ioremap_wc(device->func->resource_addr(device, bar),
 257                                  device->func->resource_size(device, bar));
 258         if (!imem->iomem) {
 259                 nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n");
 260                 return -EFAULT;
 261         }
 262
 263         return 0;
 264 }