drivers/gpu/drm/radeon/radeon_ib.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  *          Christian König
  28  */
  29
  30 #include <drm/drm_debugfs.h>
  31 #include <drm/drm_file.h>
  32
  33 #include "radeon.h"
  34
  35 /*
  36  * IB
  37  * IBs (Indirect Buffers) and areas of GPU accessible memory where
  38  * commands are stored.  You can put a pointer to the IB in the
  39  * command ring and the hw will fetch the commands from the IB
  40  * and execute them.  Generally userspace acceleration drivers
  41  * produce command buffers which are send to the kernel and
  42  * put in IBs for execution by the requested ring.
  43  */
  44 static int radeon_debugfs_sa_init(struct radeon_device *rdev);
  45
  46 /**
  47  * radeon_ib_get - request an IB (Indirect Buffer)
  48  *
  49  * @rdev: radeon_device pointer
  50  * @ring: ring index the IB is associated with
  51  * @vm: requested vm
  52  * @ib: IB object returned
  53  * @size: requested IB size
  54  *
  55  * Request an IB (all asics).  IBs are allocated using the
  56  * suballocator.
  57  * Returns 0 on success, error on failure.
  58  */
  59 int radeon_ib_get(struct radeon_device *rdev, int ring,
  60                   struct radeon_ib *ib, struct radeon_vm *vm,
  61                   unsigned size)
  62 {
  63         int r;
  64
  65         r = radeon_sa_bo_new(rdev, &rdev->ring_tmp_bo, &ib->sa_bo, size, 256);
  66         if (r) {
  67                 dev_err(rdev->dev, "failed to get a new IB (%d)\n", r);
  68                 return r;
  69         }
  70
  71         radeon_sync_create(&ib->sync);
  72
  73         ib->ring = ring;
  74         ib->fence = NULL;
  75         ib->ptr = radeon_sa_bo_cpu_addr(ib->sa_bo);
  76         ib->vm = vm;
  77         if (vm) {
  78                 /* ib pool is bound at RADEON_VA_IB_OFFSET in virtual address
  79                  * space and soffset is the offset inside the pool bo
  80                  */
  81                 ib->gpu_addr = ib->sa_bo->soffset + RADEON_VA_IB_OFFSET;
  82         } else {
  83                 ib->gpu_addr = radeon_sa_bo_gpu_addr(ib->sa_bo);
  84         }
  85         ib->is_const_ib = false;
  86
  87         return 0;
  88 }
  89
  90 /**
  91  * radeon_ib_free - free an IB (Indirect Buffer)
  92  *
  93  * @rdev: radeon_device pointer
  94  * @ib: IB object to free
  95  *
  96  * Free an IB (all asics).
  97  */
  98 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib)
  99 {
 100         radeon_sync_free(rdev, &ib->sync, ib->fence);
 101         radeon_sa_bo_free(rdev, &ib->sa_bo, ib->fence);
 102         radeon_fence_unref(&ib->fence);
 103 }
 104
 105 /**
 106  * radeon_ib_schedule - schedule an IB (Indirect Buffer) on the ring
 107  *
 108  * @rdev: radeon_device pointer
 109  * @ib: IB object to schedule
 110  * @const_ib: Const IB to schedule (SI only)
 111  * @hdp_flush: Whether or not to perform an HDP cache flush
 112  *
 113  * Schedule an IB on the associated ring (all asics).
 114  * Returns 0 on success, error on failure.
 115  *
 116  * On SI, there are two parallel engines fed from the primary ring,
 117  * the CE (Constant Engine) and the DE (Drawing Engine).  Since
 118  * resource descriptors have moved to memory, the CE allows you to
 119  * prime the caches while the DE is updating register state so that
 120  * the resource descriptors will be already in cache when the draw is
 121  * processed.  To accomplish this, the userspace driver submits two
 122  * IBs, one for the CE and one for the DE.  If there is a CE IB (called
 123  * a CONST_IB), it will be put on the ring prior to the DE IB.  Prior
 124  * to SI there was just a DE IB.
 125  */
 126 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib,
 127                        struct radeon_ib *const_ib, bool hdp_flush)
 128 {
 129         struct radeon_ring *ring = &rdev->ring[ib->ring];
 130         int r = 0;
 131
 132         if (!ib->length_dw || !ring->ready) {
 133                 /* TODO: Nothings in the ib we should report. */
 134                 dev_err(rdev->dev, "couldn't schedule ib\n");
 135                 return -EINVAL;
 136         }
 137
 138         /* 64 dwords should be enough for fence too */
 139         r = radeon_ring_lock(rdev, ring, 64 + RADEON_NUM_SYNCS * 8);
 140         if (r) {
 141                 dev_err(rdev->dev, "scheduling IB failed (%d).\n", r);
 142                 return r;
 143         }
 144
 145         /* grab a vm id if necessary */
 146         if (ib->vm) {
 147                 struct radeon_fence *vm_id_fence;
 148                 vm_id_fence = radeon_vm_grab_id(rdev, ib->vm, ib->ring);
 149                 radeon_sync_fence(&ib->sync, vm_id_fence);
 150         }
 151
 152         /* sync with other rings */
 153         r = radeon_sync_rings(rdev, &ib->sync, ib->ring);
 154         if (r) {
 155                 dev_err(rdev->dev, "failed to sync rings (%d)\n", r);
 156                 radeon_ring_unlock_undo(rdev, ring);
 157                 return r;
 158         }
 159
 160         if (ib->vm)
 161                 radeon_vm_flush(rdev, ib->vm, ib->ring,
 162                                 ib->sync.last_vm_update);
 163
 164         if (const_ib) {
 165                 radeon_ring_ib_execute(rdev, const_ib->ring, const_ib);
 166                 radeon_sync_free(rdev, &const_ib->sync, NULL);
 167         }
 168         radeon_ring_ib_execute(rdev, ib->ring, ib);
 169         r = radeon_fence_emit(rdev, &ib->fence, ib->ring);
 170         if (r) {
 171                 dev_err(rdev->dev, "failed to emit fence for new IB (%d)\n", r);
 172                 radeon_ring_unlock_undo(rdev, ring);
 173                 return r;
 174         }
 175         if (const_ib) {
 176                 const_ib->fence = radeon_fence_ref(ib->fence);
 177         }
 178
 179         if (ib->vm)
 180                 radeon_vm_fence(rdev, ib->vm, ib->fence);
 181
 182         radeon_ring_unlock_commit(rdev, ring, hdp_flush);
 183         return 0;
 184 }
 185
 186 /**
 187  * radeon_ib_pool_init - Init the IB (Indirect Buffer) pool
 188  *
 189  * @rdev: radeon_device pointer
 190  *
 191  * Initialize the suballocator to manage a pool of memory
 192  * for use as IBs (all asics).
 193  * Returns 0 on success, error on failure.
 194  */
 195 int radeon_ib_pool_init(struct radeon_device *rdev)
 196 {
 197         int r;
 198
 199         if (rdev->ib_pool_ready) {
 200                 return 0;
 201         }
 202
 203         if (rdev->family >= CHIP_BONAIRE) {
 204                 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
 205                                               RADEON_IB_POOL_SIZE*64*1024,
 206                                               RADEON_GPU_PAGE_SIZE,
 207                                               RADEON_GEM_DOMAIN_GTT,
 208                                               RADEON_GEM_GTT_WC);
 209         } else {
 210                 /* Before CIK, it's better to stick to cacheable GTT due
 211                  * to the command stream checking
 212                  */
 213                 r = radeon_sa_bo_manager_init(rdev, &rdev->ring_tmp_bo,
 214                                               RADEON_IB_POOL_SIZE*64*1024,
 215                                               RADEON_GPU_PAGE_SIZE,
 216                                               RADEON_GEM_DOMAIN_GTT, 0);
 217         }
 218         if (r) {
 219                 return r;
 220         }
 221
 222         r = radeon_sa_bo_manager_start(rdev, &rdev->ring_tmp_bo);
 223         if (r) {
 224                 return r;
 225         }
 226
 227         rdev->ib_pool_ready = true;
 228         if (radeon_debugfs_sa_init(rdev)) {
 229                 dev_err(rdev->dev, "failed to register debugfs file for SA\n");
 230         }
 231         return 0;
 232 }
 233
 234 /**
 235  * radeon_ib_pool_fini - Free the IB (Indirect Buffer) pool
 236  *
 237  * @rdev: radeon_device pointer
 238  *
 239  * Tear down the suballocator managing the pool of memory
 240  * for use as IBs (all asics).
 241  */
 242 void radeon_ib_pool_fini(struct radeon_device *rdev)
 243 {
 244         if (rdev->ib_pool_ready) {
 245                 radeon_sa_bo_manager_suspend(rdev, &rdev->ring_tmp_bo);
 246                 radeon_sa_bo_manager_fini(rdev, &rdev->ring_tmp_bo);
 247                 rdev->ib_pool_ready = false;
 248         }
 249 }
 250
 251 /**
 252  * radeon_ib_ring_tests - test IBs on the rings
 253  *
 254  * @rdev: radeon_device pointer
 255  *
 256  * Test an IB (Indirect Buffer) on each ring.
 257  * If the test fails, disable the ring.
 258  * Returns 0 on success, error if the primary GFX ring
 259  * IB test fails.
 260  */
 261 int radeon_ib_ring_tests(struct radeon_device *rdev)
 262 {
 263         unsigned i;
 264         int r;
 265
 266         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 267                 struct radeon_ring *ring = &rdev->ring[i];
 268
 269                 if (!ring->ready)
 270                         continue;
 271
 272                 r = radeon_ib_test(rdev, i, ring);
 273                 if (r) {
 274                         radeon_fence_driver_force_completion(rdev, i);
 275                         ring->ready = false;
 276                         rdev->needs_reset = false;
 277
 278                         if (i == RADEON_RING_TYPE_GFX_INDEX) {
 279                                 /* oh, oh, that's really bad */
 280                                 DRM_ERROR("radeon: failed testing IB on GFX ring (%d).\n", r);
 281                                 rdev->accel_working = false;
 282                                 return r;
 283
 284                         } else {
 285                                 /* still not good, but we can live with it */
 286                                 DRM_ERROR("radeon: failed testing IB on ring %d (%d).\n", i, r);
 287                         }
 288                 }
 289         }
 290         return 0;
 291 }
 292
 293 /*
 294  * Debugfs info
 295  */
 296 #if defined(CONFIG_DEBUG_FS)
 297
 298 static int radeon_debugfs_sa_info(struct seq_file *m, void *data)
 299 {
 300         struct drm_info_node *node = (struct drm_info_node *) m->private;
 301         struct drm_device *dev = node->minor->dev;
 302         struct radeon_device *rdev = dev->dev_private;
 303
 304         radeon_sa_bo_dump_debug_info(&rdev->ring_tmp_bo, m);
 305
 306         return 0;
 307
 308 }
 309
 310 static struct drm_info_list radeon_debugfs_sa_list[] = {
 311         {"radeon_sa_info", &radeon_debugfs_sa_info, 0, NULL},
 312 };
 313
 314 #endif
 315
 316 static int radeon_debugfs_sa_init(struct radeon_device *rdev)
 317 {
 318 #if defined(CONFIG_DEBUG_FS)
 319         return radeon_debugfs_add_files(rdev, radeon_debugfs_sa_list, 1);
 320 #else
 321         return 0;
 322 #endif
 323 }