1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, NVIDIA Corporation.
6 #include <linux/platform_device.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/firmware.h>
9 #include <linux/pci_ids.h>
10 #include <linux/iopoll.h>
20 static void falcon_writel(struct falcon
*falcon
, u32 value
, u32 offset
)
22 writel(value
, falcon
->regs
+ offset
);
25 int falcon_wait_idle(struct falcon
*falcon
)
29 return readl_poll_timeout(falcon
->regs
+ FALCON_IDLESTATE
, value
,
30 (value
== 0), 10, 100000);
33 static int falcon_dma_wait_idle(struct falcon
*falcon
)
37 return readl_poll_timeout(falcon
->regs
+ FALCON_DMATRFCMD
, value
,
38 (value
& FALCON_DMATRFCMD_IDLE
), 10, 100000);
41 static int falcon_copy_chunk(struct falcon
*falcon
,
44 enum falcon_memory target
)
46 u32 cmd
= FALCON_DMATRFCMD_SIZE_256B
;
48 if (target
== FALCON_MEMORY_IMEM
)
49 cmd
|= FALCON_DMATRFCMD_IMEM
;
51 falcon_writel(falcon
, offset
, FALCON_DMATRFMOFFS
);
52 falcon_writel(falcon
, base
, FALCON_DMATRFFBOFFS
);
53 falcon_writel(falcon
, cmd
, FALCON_DMATRFCMD
);
55 return falcon_dma_wait_idle(falcon
);
58 static void falcon_copy_firmware_image(struct falcon
*falcon
,
59 const struct firmware
*firmware
)
61 u32
*virt
= falcon
->firmware
.virt
;
64 /* copy the whole thing taking into account endianness */
65 for (i
= 0; i
< firmware
->size
/ sizeof(u32
); i
++)
66 virt
[i
] = le32_to_cpu(((u32
*)firmware
->data
)[i
]);
69 static int falcon_parse_firmware_image(struct falcon
*falcon
)
71 struct falcon_fw_bin_header_v1
*bin
= (void *)falcon
->firmware
.virt
;
72 struct falcon_fw_os_header_v1
*os
;
74 /* endian problems would show up right here */
75 if (bin
->magic
!= PCI_VENDOR_ID_NVIDIA
) {
76 dev_err(falcon
->dev
, "incorrect firmware magic\n");
80 /* currently only version 1 is supported */
81 if (bin
->version
!= 1) {
82 dev_err(falcon
->dev
, "unsupported firmware version\n");
86 /* check that the firmware size is consistent */
87 if (bin
->size
> falcon
->firmware
.size
) {
88 dev_err(falcon
->dev
, "firmware image size inconsistency\n");
92 os
= falcon
->firmware
.virt
+ bin
->os_header_offset
;
94 falcon
->firmware
.bin_data
.size
= bin
->os_size
;
95 falcon
->firmware
.bin_data
.offset
= bin
->os_data_offset
;
96 falcon
->firmware
.code
.offset
= os
->code_offset
;
97 falcon
->firmware
.code
.size
= os
->code_size
;
98 falcon
->firmware
.data
.offset
= os
->data_offset
;
99 falcon
->firmware
.data
.size
= os
->data_size
;
104 int falcon_read_firmware(struct falcon
*falcon
, const char *name
)
108 /* request_firmware prints error if it fails */
109 err
= request_firmware(&falcon
->firmware
.firmware
, name
, falcon
->dev
);
113 falcon
->firmware
.size
= falcon
->firmware
.firmware
->size
;
118 int falcon_load_firmware(struct falcon
*falcon
)
120 const struct firmware
*firmware
= falcon
->firmware
.firmware
;
123 /* copy firmware image into local area. this also ensures endianness */
124 falcon_copy_firmware_image(falcon
, firmware
);
126 /* parse the image data */
127 err
= falcon_parse_firmware_image(falcon
);
129 dev_err(falcon
->dev
, "failed to parse firmware image\n");
133 release_firmware(firmware
);
134 falcon
->firmware
.firmware
= NULL
;
139 int falcon_init(struct falcon
*falcon
)
141 falcon
->firmware
.virt
= NULL
;
146 void falcon_exit(struct falcon
*falcon
)
148 if (falcon
->firmware
.firmware
)
149 release_firmware(falcon
->firmware
.firmware
);
152 int falcon_boot(struct falcon
*falcon
)
154 unsigned long offset
;
158 if (!falcon
->firmware
.virt
)
161 err
= readl_poll_timeout(falcon
->regs
+ FALCON_DMACTL
, value
,
162 (value
& (FALCON_DMACTL_IMEM_SCRUBBING
|
163 FALCON_DMACTL_DMEM_SCRUBBING
)) == 0,
168 falcon_writel(falcon
, 0, FALCON_DMACTL
);
170 /* setup the address of the binary data so Falcon can access it later */
171 falcon_writel(falcon
, (falcon
->firmware
.iova
+
172 falcon
->firmware
.bin_data
.offset
) >> 8,
175 /* copy the data segment into Falcon internal memory */
176 for (offset
= 0; offset
< falcon
->firmware
.data
.size
; offset
+= 256)
177 falcon_copy_chunk(falcon
,
178 falcon
->firmware
.data
.offset
+ offset
,
179 offset
, FALCON_MEMORY_DATA
);
181 /* copy the first code segment into Falcon internal memory */
182 falcon_copy_chunk(falcon
, falcon
->firmware
.code
.offset
,
183 0, FALCON_MEMORY_IMEM
);
185 /* setup falcon interrupts */
186 falcon_writel(falcon
, FALCON_IRQMSET_EXT(0xff) |
187 FALCON_IRQMSET_SWGEN1
|
188 FALCON_IRQMSET_SWGEN0
|
189 FALCON_IRQMSET_EXTERR
|
190 FALCON_IRQMSET_HALT
|
191 FALCON_IRQMSET_WDTMR
,
193 falcon_writel(falcon
, FALCON_IRQDEST_EXT(0xff) |
194 FALCON_IRQDEST_SWGEN1
|
195 FALCON_IRQDEST_SWGEN0
|
196 FALCON_IRQDEST_EXTERR
|
200 /* enable interface */
201 falcon_writel(falcon
, FALCON_ITFEN_MTHDEN
|
206 falcon_writel(falcon
, 0x00000000, FALCON_BOOTVEC
);
207 falcon_writel(falcon
, FALCON_CPUCTL_STARTCPU
, FALCON_CPUCTL
);
209 err
= falcon_wait_idle(falcon
);
211 dev_err(falcon
->dev
, "Falcon boot failed due to timeout\n");
218 void falcon_execute_method(struct falcon
*falcon
, u32 method
, u32 data
)
220 falcon_writel(falcon
, method
>> 2, FALCON_UCLASS_METHOD_OFFSET
);
221 falcon_writel(falcon
, data
, FALCON_UCLASS_METHOD_DATA
);