?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
WIP FPC-III support
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-pxa.c
bloba636ea0eb50af2c7234e508fd00c78723e764ffd
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * i2c_adap_pxa.c
4 *
5 * I2C adapter for the PXA I2C bus access.
6 *
7 * Copyright (C) 2002 Intrinsyc Software Inc.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 *
10 * History:
11 * Apr 2002: Initial version [CS]
12 * Jun 2002: Properly separated algo/adap [FB]
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
15 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
16 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
17 * Feb 2005: Rework slave mode handling [RMK]
18 */
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/errno.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/i2c.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/platform_device.h>
34 #include <linux/platform_data/i2c-pxa.h>
35 #include <linux/slab.h>
36
37 /* I2C register field definitions */
38 #define IBMR_SDAS (1 << 0)
39 #define IBMR_SCLS (1 << 1)
40
41 #define ICR_START (1 << 0) /* start bit */
42 #define ICR_STOP (1 << 1) /* stop bit */
43 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
44 #define ICR_TB (1 << 3) /* transfer byte bit */
45 #define ICR_MA (1 << 4) /* master abort */
46 #define ICR_SCLE (1 << 5) /* master clock enable */
47 #define ICR_IUE (1 << 6) /* unit enable */
48 #define ICR_GCD (1 << 7) /* general call disable */
49 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
50 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
51 #define ICR_BEIE (1 << 10) /* enable bus error ints */
52 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
53 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
54 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
55 #define ICR_UR (1 << 14) /* unit reset */
56 #define ICR_FM (1 << 15) /* fast mode */
57 #define ICR_HS (1 << 16) /* High Speed mode */
58 #define ICR_A3700_FM (1 << 16) /* fast mode for armada-3700 */
59 #define ICR_A3700_HS (1 << 17) /* high speed mode for armada-3700 */
60 #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
61
62 #define ISR_RWM (1 << 0) /* read/write mode */
63 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
64 #define ISR_UB (1 << 2) /* unit busy */
65 #define ISR_IBB (1 << 3) /* bus busy */
66 #define ISR_SSD (1 << 4) /* slave stop detected */
67 #define ISR_ALD (1 << 5) /* arbitration loss detected */
68 #define ISR_ITE (1 << 6) /* tx buffer empty */
69 #define ISR_IRF (1 << 7) /* rx buffer full */
70 #define ISR_GCAD (1 << 8) /* general call address detected */
71 #define ISR_SAD (1 << 9) /* slave address detected */
72 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
73
74 #define ILCR_SLV_SHIFT 0
75 #define ILCR_SLV_MASK (0x1FF << ILCR_SLV_SHIFT)
76 #define ILCR_FLV_SHIFT 9
77 #define ILCR_FLV_MASK (0x1FF << ILCR_FLV_SHIFT)
78 #define ILCR_HLVL_SHIFT 18
79 #define ILCR_HLVL_MASK (0x1FF << ILCR_HLVL_SHIFT)
80 #define ILCR_HLVH_SHIFT 27
81 #define ILCR_HLVH_MASK (0x1F << ILCR_HLVH_SHIFT)
82
83 #define IWCR_CNT_SHIFT 0
84 #define IWCR_CNT_MASK (0x1F << IWCR_CNT_SHIFT)
85 #define IWCR_HS_CNT1_SHIFT 5
86 #define IWCR_HS_CNT1_MASK (0x1F << IWCR_HS_CNT1_SHIFT)
87 #define IWCR_HS_CNT2_SHIFT 10
88 #define IWCR_HS_CNT2_MASK (0x1F << IWCR_HS_CNT2_SHIFT)
89
90 /* need a longer timeout if we're dealing with the fact we may well be
91 * looking at a multi-master environment
92 */
93 #define DEF_TIMEOUT 32
94
95 #define NO_SLAVE (-ENXIO)
96 #define BUS_ERROR (-EREMOTEIO)
97 #define XFER_NAKED (-ECONNREFUSED)
98 #define I2C_RETRY (-2000) /* an error has occurred retry transmit */
99
100 /* ICR initialize bit values
101 *
102 * 15 FM 0 (100 kHz operation)
103 * 14 UR 0 (No unit reset)
104 * 13 SADIE 0 (Disables the unit from interrupting on slave addresses
105 * matching its slave address)
106 * 12 ALDIE 0 (Disables the unit from interrupt when it loses arbitration
107 * in master mode)
108 * 11 SSDIE 0 (Disables interrupts from a slave stop detected, in slave mode)
109 * 10 BEIE 1 (Enable interrupts from detected bus errors, no ACK sent)
110 * 9 IRFIE 1 (Enable interrupts from full buffer received)
111 * 8 ITEIE 1 (Enables the I2C unit to interrupt when transmit buffer empty)
112 * 7 GCD 1 (Disables i2c unit response to general call messages as a slave)
113 * 6 IUE 0 (Disable unit until we change settings)
114 * 5 SCLE 1 (Enables the i2c clock output for master mode (drives SCL)
115 * 4 MA 0 (Only send stop with the ICR stop bit)
116 * 3 TB 0 (We are not transmitting a byte initially)
117 * 2 ACKNAK 0 (Send an ACK after the unit receives a byte)
118 * 1 STOP 0 (Do not send a STOP)
119 * 0 START 0 (Do not send a START)
120 */
121 #define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
122
123 /* I2C status register init values
124 *
125 * 10 BED 1 (Clear bus error detected)
126 * 9 SAD 1 (Clear slave address detected)
127 * 7 IRF 1 (Clear IDBR Receive Full)
128 * 6 ITE 1 (Clear IDBR Transmit Empty)
129 * 5 ALD 1 (Clear Arbitration Loss Detected)
130 * 4 SSD 1 (Clear Slave Stop Detected)
131 */
132 #define I2C_ISR_INIT 0x7FF /* status register init */
133
134 struct pxa_reg_layout {
135 u32 ibmr;
136 u32 idbr;
137 u32 icr;
138 u32 isr;
139 u32 isar;
140 u32 ilcr;
141 u32 iwcr;
142 u32 fm;
143 u32 hs;
144 };
145
146 enum pxa_i2c_types {
147 REGS_PXA2XX,
148 REGS_PXA3XX,
149 REGS_CE4100,
150 REGS_PXA910,
151 REGS_A3700,
152 };
153
154 /* I2C register layout definitions */
155 static struct pxa_reg_layout pxa_reg_layout[] = {
156 [REGS_PXA2XX] = {
157 .ibmr = 0x00,
158 .idbr = 0x08,
159 .icr = 0x10,
160 .isr = 0x18,
161 .isar = 0x20,
162 .fm = ICR_FM,
163 .hs = ICR_HS,
164 },
165 [REGS_PXA3XX] = {
166 .ibmr = 0x00,
167 .idbr = 0x04,
168 .icr = 0x08,
169 .isr = 0x0c,
170 .isar = 0x10,
171 .fm = ICR_FM,
172 .hs = ICR_HS,
173 },
174 [REGS_CE4100] = {
175 .ibmr = 0x14,
176 .idbr = 0x0c,
177 .icr = 0x00,
178 .isr = 0x04,
179 /* no isar register */
180 .fm = ICR_FM,
181 .hs = ICR_HS,
182 },
183 [REGS_PXA910] = {
184 .ibmr = 0x00,
185 .idbr = 0x08,
186 .icr = 0x10,
187 .isr = 0x18,
188 .isar = 0x20,
189 .ilcr = 0x28,
190 .iwcr = 0x30,
191 .fm = ICR_FM,
192 .hs = ICR_HS,
193 },
194 [REGS_A3700] = {
195 .ibmr = 0x00,
196 .idbr = 0x04,
197 .icr = 0x08,
198 .isr = 0x0c,
199 .isar = 0x10,
200 .fm = ICR_A3700_FM,
201 .hs = ICR_A3700_HS,
202 },
203 };
204
205 static const struct of_device_id i2c_pxa_dt_ids[] = {
206 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
207 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
208 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA910 },
209 { .compatible = "marvell,armada-3700-i2c", .data = (void *)REGS_A3700 },
210 {}
211 };
212 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
213
214 static const struct platform_device_id i2c_pxa_id_table[] = {
215 { "pxa2xx-i2c", REGS_PXA2XX },
216 { "pxa3xx-pwri2c", REGS_PXA3XX },
217 { "ce4100-i2c", REGS_CE4100 },
218 { "pxa910-i2c", REGS_PXA910 },
219 { "armada-3700-i2c", REGS_A3700 },
220 { },
221 };
222 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
223
224 struct pxa_i2c {
225 spinlock_t lock;
226 wait_queue_head_t wait;
227 struct i2c_msg *msg;
228 unsigned int msg_num;
229 unsigned int msg_idx;
230 unsigned int msg_ptr;
231 unsigned int slave_addr;
232 unsigned int req_slave_addr;
233
234 struct i2c_adapter adap;
235 struct clk *clk;
236 #ifdef CONFIG_I2C_PXA_SLAVE
237 struct i2c_client *slave;
238 #endif
239
240 unsigned int irqlogidx;
241 u32 isrlog[32];
242 u32 icrlog[32];
243
244 void __iomem *reg_base;
245 void __iomem *reg_ibmr;
246 void __iomem *reg_idbr;
247 void __iomem *reg_icr;
248 void __iomem *reg_isr;
249 void __iomem *reg_isar;
250 void __iomem *reg_ilcr;
251 void __iomem *reg_iwcr;
252
253 unsigned long iobase;
254 unsigned long iosize;
255
256 int irq;
257 unsigned int use_pio :1;
258 unsigned int fast_mode :1;
259 unsigned int high_mode:1;
260 unsigned char master_code;
261 unsigned long rate;
262 bool highmode_enter;
263 u32 fm_mask;
264 u32 hs_mask;
265
266 struct i2c_bus_recovery_info recovery;
267 };
268
269 #define _IBMR(i2c) ((i2c)->reg_ibmr)
270 #define _IDBR(i2c) ((i2c)->reg_idbr)
271 #define _ICR(i2c) ((i2c)->reg_icr)
272 #define _ISR(i2c) ((i2c)->reg_isr)
273 #define _ISAR(i2c) ((i2c)->reg_isar)
274 #define _ILCR(i2c) ((i2c)->reg_ilcr)
275 #define _IWCR(i2c) ((i2c)->reg_iwcr)
276
277 /*
278 * I2C Slave mode address
279 */
280 #define I2C_PXA_SLAVE_ADDR 0x1
281
282 #ifdef DEBUG
283
284 struct bits {
285 u32 mask;
286 const char *set;
287 const char *unset;
288 };
289 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
290
291 static inline void
292 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
293 {
294 printk("%s %08x:", prefix, val);
295 while (num--) {
296 const char *str = val & bits->mask ? bits->set : bits->unset;
297 if (str)
298 pr_cont(" %s", str);
299 bits++;
300 }
301 pr_cont("\n");
302 }
303
304 static const struct bits isr_bits[] = {
305 PXA_BIT(ISR_RWM, "RX", "TX"),
306 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
307 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
308 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
309 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
310 PXA_BIT(ISR_ALD, "ALD", NULL),
311 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
312 PXA_BIT(ISR_IRF, "RxFull", NULL),
313 PXA_BIT(ISR_GCAD, "GenCall", NULL),
314 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
315 PXA_BIT(ISR_BED, "BusErr", NULL),
316 };
317
318 static void decode_ISR(unsigned int val)
319 {
320 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
321 }
322
323 static const struct bits icr_bits[] = {
324 PXA_BIT(ICR_START, "START", NULL),
325 PXA_BIT(ICR_STOP, "STOP", NULL),
326 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
327 PXA_BIT(ICR_TB, "TB", NULL),
328 PXA_BIT(ICR_MA, "MA", NULL),
329 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
330 PXA_BIT(ICR_IUE, "IUE", "iue"),
331 PXA_BIT(ICR_GCD, "GCD", NULL),
332 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
333 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
334 PXA_BIT(ICR_BEIE, "BEIE", NULL),
335 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
336 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
337 PXA_BIT(ICR_SADIE, "SADIE", NULL),
338 PXA_BIT(ICR_UR, "UR", "ur"),
339 };
340
341 #ifdef CONFIG_I2C_PXA_SLAVE
342 static void decode_ICR(unsigned int val)
343 {
344 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
345 }
346 #endif
347
348 static unsigned int i2c_debug = DEBUG;
349
350 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
351 {
352 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
353 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
354 }
355
356 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
357
358 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
359 {
360 unsigned int i;
361 struct device *dev = &i2c->adap.dev;
362
363 dev_err(dev, "slave_0x%x error: %s\n",
364 i2c->req_slave_addr >> 1, why);
365 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
366 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
367 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
368 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
369 readl(_ISR(i2c)));
370 dev_err(dev, "log:");
371 for (i = 0; i < i2c->irqlogidx; i++)
372 pr_cont(" [%03x:%05x]", i2c->isrlog[i], i2c->icrlog[i]);
373 pr_cont("\n");
374 }
375
376 #else /* ifdef DEBUG */
377
378 #define i2c_debug 0
379
380 #define show_state(i2c) do { } while (0)
381 #define decode_ISR(val) do { } while (0)
382 #define decode_ICR(val) do { } while (0)
383 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
384
385 #endif /* ifdef DEBUG / else */
386
387 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
388
389 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
390 {
391 return !(readl(_ICR(i2c)) & ICR_SCLE);
392 }
393
394 static void i2c_pxa_abort(struct pxa_i2c *i2c)
395 {
396 int i = 250;
397
398 if (i2c_pxa_is_slavemode(i2c)) {
399 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
400 return;
401 }
402
403 while ((i > 0) && (readl(_IBMR(i2c)) & IBMR_SDAS) == 0) {
404 unsigned long icr = readl(_ICR(i2c));
405
406 icr &= ~ICR_START;
407 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
408
409 writel(icr, _ICR(i2c));
410
411 show_state(i2c);
412
413 mdelay(1);
414 i --;
415 }
416
417 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
418 _ICR(i2c));
419 }
420
421 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
422 {
423 int timeout = DEF_TIMEOUT;
424 u32 isr;
425
426 while (1) {
427 isr = readl(_ISR(i2c));
428 if (!(isr & (ISR_IBB | ISR_UB)))
429 return 0;
430
431 if (isr & ISR_SAD)
432 timeout += 4;
433
434 if (!timeout--)
435 break;
436
437 msleep(2);
438 show_state(i2c);
439 }
440
441 show_state(i2c);
442
443 return I2C_RETRY;
444 }
445
446 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
447 {
448 unsigned long timeout = jiffies + HZ*4;
449
450 while (time_before(jiffies, timeout)) {
451 if (i2c_debug > 1)
452 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
453 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
454
455 if (readl(_ISR(i2c)) & ISR_SAD) {
456 if (i2c_debug > 0)
457 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
458 goto out;
459 }
460
461 /* wait for unit and bus being not busy, and we also do a
462 * quick check of the i2c lines themselves to ensure they've
463 * gone high...
464 */
465 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 &&
466 readl(_IBMR(i2c)) == (IBMR_SCLS | IBMR_SDAS)) {
467 if (i2c_debug > 0)
468 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
469 return 1;
470 }
471
472 msleep(1);
473 }
474
475 if (i2c_debug > 0)
476 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
477 out:
478 return 0;
479 }
480
481 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
482 {
483 if (i2c_debug)
484 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
485
486 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
487 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
488 if (!i2c_pxa_wait_master(i2c)) {
489 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
490 return I2C_RETRY;
491 }
492 }
493
494 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
495 return 0;
496 }
497
498 #ifdef CONFIG_I2C_PXA_SLAVE
499 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
500 {
501 unsigned long timeout = jiffies + HZ*1;
502
503 /* wait for stop */
504
505 show_state(i2c);
506
507 while (time_before(jiffies, timeout)) {
508 if (i2c_debug > 1)
509 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
510 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
511
512 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
513 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
514 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
515 if (i2c_debug > 1)
516 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
517 return 1;
518 }
519
520 msleep(1);
521 }
522
523 if (i2c_debug > 0)
524 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
525 return 0;
526 }
527
528 /*
529 * clear the hold on the bus, and take of anything else
530 * that has been configured
531 */
532 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
533 {
534 show_state(i2c);
535
536 if (errcode < 0) {
537 udelay(100); /* simple delay */
538 } else {
539 /* we need to wait for the stop condition to end */
540
541 /* if we where in stop, then clear... */
542 if (readl(_ICR(i2c)) & ICR_STOP) {
543 udelay(100);
544 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
545 }
546
547 if (!i2c_pxa_wait_slave(i2c)) {
548 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
549 __func__);
550 return;
551 }
552 }
553
554 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
555 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
556
557 if (i2c_debug) {
558 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
559 decode_ICR(readl(_ICR(i2c)));
560 }
561 }
562 #else
563 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
564 #endif
565
566 static void i2c_pxa_do_reset(struct pxa_i2c *i2c)
567 {
568 /* reset according to 9.8 */
569 writel(ICR_UR, _ICR(i2c));
570 writel(I2C_ISR_INIT, _ISR(i2c));
571 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
572
573 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
574 writel(i2c->slave_addr, _ISAR(i2c));
575
576 /* set control register values */
577 writel(I2C_ICR_INIT | (i2c->fast_mode ? i2c->fm_mask : 0), _ICR(i2c));
578 writel(readl(_ICR(i2c)) | (i2c->high_mode ? i2c->hs_mask : 0), _ICR(i2c));
579
580 #ifdef CONFIG_I2C_PXA_SLAVE
581 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
582 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
583 #endif
584
585 i2c_pxa_set_slave(i2c, 0);
586 }
587
588 static void i2c_pxa_enable(struct pxa_i2c *i2c)
589 {
590 /* enable unit */
591 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
592 udelay(100);
593 }
594
595 static void i2c_pxa_reset(struct pxa_i2c *i2c)
596 {
597 pr_debug("Resetting I2C Controller Unit\n");
598
599 /* abort any transfer currently under way */
600 i2c_pxa_abort(i2c);
601 i2c_pxa_do_reset(i2c);
602 i2c_pxa_enable(i2c);
603 }
604
605
606 #ifdef CONFIG_I2C_PXA_SLAVE
607 /*
608 * PXA I2C Slave mode
609 */
610
611 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
612 {
613 if (isr & ISR_BED) {
614 /* what should we do here? */
615 } else {
616 u8 byte = 0;
617
618 if (i2c->slave != NULL)
619 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_PROCESSED,
620 &byte);
621
622 writel(byte, _IDBR(i2c));
623 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
624 }
625 }
626
627 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
628 {
629 u8 byte = readl(_IDBR(i2c));
630
631 if (i2c->slave != NULL)
632 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_RECEIVED, &byte);
633
634 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
635 }
636
637 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
638 {
639 int timeout;
640
641 if (i2c_debug > 0)
642 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
643 (isr & ISR_RWM) ? 'r' : 't');
644
645 if (i2c->slave != NULL) {
646 if (isr & ISR_RWM) {
647 u8 byte = 0;
648
649 i2c_slave_event(i2c->slave, I2C_SLAVE_READ_REQUESTED,
650 &byte);
651 writel(byte, _IDBR(i2c));
652 } else {
653 i2c_slave_event(i2c->slave, I2C_SLAVE_WRITE_REQUESTED,
654 NULL);
655 }
656 }
657
658 /*
659 * slave could interrupt in the middle of us generating a
660 * start condition... if this happens, we'd better back off
661 * and stop holding the poor thing up
662 */
663 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
664 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
665
666 timeout = 0x10000;
667
668 while (1) {
669 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
670 break;
671
672 timeout--;
673
674 if (timeout <= 0) {
675 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
676 break;
677 }
678 }
679
680 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
681 }
682
683 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
684 {
685 if (i2c_debug > 2)
686 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
687
688 if (i2c->slave != NULL)
689 i2c_slave_event(i2c->slave, I2C_SLAVE_STOP, NULL);
690
691 if (i2c_debug > 2)
692 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
693
694 /*
695 * If we have a master-mode message waiting,
696 * kick it off now that the slave has completed.
697 */
698 if (i2c->msg)
699 i2c_pxa_master_complete(i2c, I2C_RETRY);
700 }
701
702 static int i2c_pxa_slave_reg(struct i2c_client *slave)
703 {
704 struct pxa_i2c *i2c = slave->adapter->algo_data;
705
706 if (i2c->slave)
707 return -EBUSY;
708
709 if (!i2c->reg_isar)
710 return -EAFNOSUPPORT;
711
712 i2c->slave = slave;
713 i2c->slave_addr = slave->addr;
714
715 writel(i2c->slave_addr, _ISAR(i2c));
716
717 return 0;
718 }
719
720 static int i2c_pxa_slave_unreg(struct i2c_client *slave)
721 {
722 struct pxa_i2c *i2c = slave->adapter->algo_data;
723
724 WARN_ON(!i2c->slave);
725
726 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
727 writel(i2c->slave_addr, _ISAR(i2c));
728
729 i2c->slave = NULL;
730
731 return 0;
732 }
733 #else
734 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
735 {
736 if (isr & ISR_BED) {
737 /* what should we do here? */
738 } else {
739 writel(0, _IDBR(i2c));
740 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
741 }
742 }
743
744 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
745 {
746 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
747 }
748
749 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
750 {
751 int timeout;
752
753 /*
754 * slave could interrupt in the middle of us generating a
755 * start condition... if this happens, we'd better back off
756 * and stop holding the poor thing up
757 */
758 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
759 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
760
761 timeout = 0x10000;
762
763 while (1) {
764 if ((readl(_IBMR(i2c)) & IBMR_SCLS) == IBMR_SCLS)
765 break;
766
767 timeout--;
768
769 if (timeout <= 0) {
770 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
771 break;
772 }
773 }
774
775 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
776 }
777
778 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
779 {
780 if (i2c->msg)
781 i2c_pxa_master_complete(i2c, I2C_RETRY);
782 }
783 #endif
784
785 /*
786 * PXA I2C Master mode
787 */
788
789 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
790 {
791 u32 icr;
792
793 /*
794 * Step 1: target slave address into IDBR
795 */
796 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
797 writel(i2c->req_slave_addr, _IDBR(i2c));
798
799 /*
800 * Step 2: initiate the write.
801 */
802 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
803 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
804 }
805
806 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
807 {
808 u32 icr;
809
810 /* Clear the START, STOP, ACK, TB and MA flags */
811 icr = readl(_ICR(i2c));
812 icr &= ~(ICR_START | ICR_STOP | ICR_ACKNAK | ICR_TB | ICR_MA);
813 writel(icr, _ICR(i2c));
814 }
815
816 /*
817 * PXA I2C send master code
818 * 1. Load master code to IDBR and send it.
819 * Note for HS mode, set ICR [GPIOEN].
820 * 2. Wait until win arbitration.
821 */
822 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
823 {
824 u32 icr;
825 long timeout;
826
827 spin_lock_irq(&i2c->lock);
828 i2c->highmode_enter = true;
829 writel(i2c->master_code, _IDBR(i2c));
830
831 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
832 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
833 writel(icr, _ICR(i2c));
834
835 spin_unlock_irq(&i2c->lock);
836 timeout = wait_event_timeout(i2c->wait,
837 i2c->highmode_enter == false, HZ * 1);
838
839 i2c->highmode_enter = false;
840
841 return (timeout == 0) ? I2C_RETRY : 0;
842 }
843
844 /*
845 * i2c_pxa_master_complete - complete the message and wake up.
846 */
847 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
848 {
849 i2c->msg_ptr = 0;
850 i2c->msg = NULL;
851 i2c->msg_idx ++;
852 i2c->msg_num = 0;
853 if (ret)
854 i2c->msg_idx = ret;
855 if (!i2c->use_pio)
856 wake_up(&i2c->wait);
857 }
858
859 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
860 {
861 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
862
863 again:
864 /*
865 * If ISR_ALD is set, we lost arbitration.
866 */
867 if (isr & ISR_ALD) {
868 /*
869 * Do we need to do anything here? The PXA docs
870 * are vague about what happens.
871 */
872 i2c_pxa_scream_blue_murder(i2c, "ALD set");
873
874 /*
875 * We ignore this error. We seem to see spurious ALDs
876 * for seemingly no reason. If we handle them as I think
877 * they should, we end up causing an I2C error, which
878 * is painful for some systems.
879 */
880 return; /* ignore */
881 }
882
883 if ((isr & ISR_BED) &&
884 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
885 (isr & ISR_ACKNAK)))) {
886 int ret = BUS_ERROR;
887
888 /*
889 * I2C bus error - either the device NAK'd us, or
890 * something more serious happened. If we were NAK'd
891 * on the initial address phase, we can retry.
892 */
893 if (isr & ISR_ACKNAK) {
894 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
895 ret = NO_SLAVE;
896 else
897 ret = XFER_NAKED;
898 }
899 i2c_pxa_master_complete(i2c, ret);
900 } else if (isr & ISR_RWM) {
901 /*
902 * Read mode. We have just sent the address byte, and
903 * now we must initiate the transfer.
904 */
905 if (i2c->msg_ptr == i2c->msg->len - 1 &&
906 i2c->msg_idx == i2c->msg_num - 1)
907 icr |= ICR_STOP | ICR_ACKNAK;
908
909 icr |= ICR_ALDIE | ICR_TB;
910 } else if (i2c->msg_ptr < i2c->msg->len) {
911 /*
912 * Write mode. Write the next data byte.
913 */
914 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
915
916 icr |= ICR_ALDIE | ICR_TB;
917
918 /*
919 * If this is the last byte of the last message or last byte
920 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
921 */
922 if ((i2c->msg_ptr == i2c->msg->len) &&
923 ((i2c->msg->flags & I2C_M_STOP) ||
924 (i2c->msg_idx == i2c->msg_num - 1)))
925 icr |= ICR_STOP;
926
927 } else if (i2c->msg_idx < i2c->msg_num - 1) {
928 /*
929 * Next segment of the message.
930 */
931 i2c->msg_ptr = 0;
932 i2c->msg_idx ++;
933 i2c->msg++;
934
935 /*
936 * If we aren't doing a repeated start and address,
937 * go back and try to send the next byte. Note that
938 * we do not support switching the R/W direction here.
939 */
940 if (i2c->msg->flags & I2C_M_NOSTART)
941 goto again;
942
943 /*
944 * Write the next address.
945 */
946 i2c->req_slave_addr = i2c_8bit_addr_from_msg(i2c->msg);
947 writel(i2c->req_slave_addr, _IDBR(i2c));
948
949 /*
950 * And trigger a repeated start, and send the byte.
951 */
952 icr &= ~ICR_ALDIE;
953 icr |= ICR_START | ICR_TB;
954 } else {
955 if (i2c->msg->len == 0)
956 icr |= ICR_MA;
957 i2c_pxa_master_complete(i2c, 0);
958 }
959
960 i2c->icrlog[i2c->irqlogidx-1] = icr;
961
962 writel(icr, _ICR(i2c));
963 show_state(i2c);
964 }
965
966 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
967 {
968 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
969
970 /*
971 * Read the byte.
972 */
973 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
974
975 if (i2c->msg_ptr < i2c->msg->len) {
976 /*
977 * If this is the last byte of the last
978 * message, send a STOP.
979 */
980 if (i2c->msg_ptr == i2c->msg->len - 1)
981 icr |= ICR_STOP | ICR_ACKNAK;
982
983 icr |= ICR_ALDIE | ICR_TB;
984 } else {
985 i2c_pxa_master_complete(i2c, 0);
986 }
987
988 i2c->icrlog[i2c->irqlogidx-1] = icr;
989
990 writel(icr, _ICR(i2c));
991 }
992
993 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
994 ISR_SAD | ISR_BED)
995 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
996 {
997 struct pxa_i2c *i2c = dev_id;
998 u32 isr = readl(_ISR(i2c));
999
1000 if (!(isr & VALID_INT_SOURCE))
1001 return IRQ_NONE;
1002
1003 if (i2c_debug > 2 && 0) {
1004 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1005 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1006 decode_ISR(isr);
1007 }
1008
1009 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1010 i2c->isrlog[i2c->irqlogidx++] = isr;
1011
1012 show_state(i2c);
1013
1014 /*
1015 * Always clear all pending IRQs.
1016 */
1017 writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1018
1019 if (isr & ISR_SAD)
1020 i2c_pxa_slave_start(i2c, isr);
1021 if (isr & ISR_SSD)
1022 i2c_pxa_slave_stop(i2c);
1023
1024 if (i2c_pxa_is_slavemode(i2c)) {
1025 if (isr & ISR_ITE)
1026 i2c_pxa_slave_txempty(i2c, isr);
1027 if (isr & ISR_IRF)
1028 i2c_pxa_slave_rxfull(i2c, isr);
1029 } else if (i2c->msg && (!i2c->highmode_enter)) {
1030 if (isr & ISR_ITE)
1031 i2c_pxa_irq_txempty(i2c, isr);
1032 if (isr & ISR_IRF)
1033 i2c_pxa_irq_rxfull(i2c, isr);
1034 } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1035 i2c->highmode_enter = false;
1036 wake_up(&i2c->wait);
1037 } else {
1038 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1039 }
1040
1041 return IRQ_HANDLED;
1042 }
1043
1044 /*
1045 * We are protected by the adapter bus mutex.
1046 */
1047 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
1048 {
1049 long timeout;
1050 int ret;
1051
1052 /*
1053 * Wait for the bus to become free.
1054 */
1055 ret = i2c_pxa_wait_bus_not_busy(i2c);
1056 if (ret) {
1057 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
1058 i2c_recover_bus(&i2c->adap);
1059 goto out;
1060 }
1061
1062 /*
1063 * Set master mode.
1064 */
1065 ret = i2c_pxa_set_master(i2c);
1066 if (ret) {
1067 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
1068 goto out;
1069 }
1070
1071 if (i2c->high_mode) {
1072 ret = i2c_pxa_send_mastercode(i2c);
1073 if (ret) {
1074 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
1075 goto out;
1076 }
1077 }
1078
1079 spin_lock_irq(&i2c->lock);
1080
1081 i2c->msg = msg;
1082 i2c->msg_num = num;
1083 i2c->msg_idx = 0;
1084 i2c->msg_ptr = 0;
1085 i2c->irqlogidx = 0;
1086
1087 i2c_pxa_start_message(i2c);
1088
1089 spin_unlock_irq(&i2c->lock);
1090
1091 /*
1092 * The rest of the processing occurs in the interrupt handler.
1093 */
1094 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
1095 i2c_pxa_stop_message(i2c);
1096
1097 /*
1098 * We place the return code in i2c->msg_idx.
1099 */
1100 ret = i2c->msg_idx;
1101
1102 if (!timeout && i2c->msg_num) {
1103 i2c_pxa_scream_blue_murder(i2c, "timeout with active message");
1104 i2c_recover_bus(&i2c->adap);
1105 ret = I2C_RETRY;
1106 }
1107
1108 out:
1109 return ret;
1110 }
1111
1112 static int i2c_pxa_internal_xfer(struct pxa_i2c *i2c,
1113 struct i2c_msg *msgs, int num,
1114 int (*xfer)(struct pxa_i2c *,
1115 struct i2c_msg *, int num))
1116 {
1117 int ret, i;
1118
1119 for (i = 0; ; ) {
1120 ret = xfer(i2c, msgs, num);
1121 if (ret != I2C_RETRY && ret != NO_SLAVE)
1122 goto out;
1123 if (++i >= i2c->adap.retries)
1124 break;
1125
1126 if (i2c_debug)
1127 dev_dbg(&i2c->adap.dev, "Retrying transmission\n");
1128 udelay(100);
1129 }
1130 if (ret != NO_SLAVE)
1131 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1132 ret = -EREMOTEIO;
1133 out:
1134 i2c_pxa_set_slave(i2c, ret);
1135 return ret;
1136 }
1137
1138 static int i2c_pxa_xfer(struct i2c_adapter *adap,
1139 struct i2c_msg msgs[], int num)
1140 {
1141 struct pxa_i2c *i2c = adap->algo_data;
1142
1143 return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_xfer);
1144 }
1145
1146 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1147 {
1148 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1149 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1150 }
1151
1152 static const struct i2c_algorithm i2c_pxa_algorithm = {
1153 .master_xfer = i2c_pxa_xfer,
1154 .functionality = i2c_pxa_functionality,
1155 #ifdef CONFIG_I2C_PXA_SLAVE
1156 .reg_slave = i2c_pxa_slave_reg,
1157 .unreg_slave = i2c_pxa_slave_unreg,
1158 #endif
1159 };
1160
1161 /* Non-interrupt mode support */
1162 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
1163 {
1164 /* make timeout the same as for interrupt based functions */
1165 long timeout = 2 * DEF_TIMEOUT;
1166
1167 /*
1168 * Wait for the bus to become free.
1169 */
1170 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB))
1171 udelay(1000);
1172
1173 if (timeout < 0) {
1174 show_state(i2c);
1175 dev_err(&i2c->adap.dev,
1176 "i2c_pxa: timeout waiting for bus free (set_master)\n");
1177 return I2C_RETRY;
1178 }
1179
1180 /*
1181 * Set master mode.
1182 */
1183 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
1184
1185 return 0;
1186 }
1187
1188 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
1189 struct i2c_msg *msg, int num)
1190 {
1191 unsigned long timeout = 500000; /* 5 seconds */
1192 int ret = 0;
1193
1194 ret = i2c_pxa_pio_set_master(i2c);
1195 if (ret)
1196 goto out;
1197
1198 i2c->msg = msg;
1199 i2c->msg_num = num;
1200 i2c->msg_idx = 0;
1201 i2c->msg_ptr = 0;
1202 i2c->irqlogidx = 0;
1203
1204 i2c_pxa_start_message(i2c);
1205
1206 while (i2c->msg_num > 0 && --timeout) {
1207 i2c_pxa_handler(0, i2c);
1208 udelay(10);
1209 }
1210
1211 i2c_pxa_stop_message(i2c);
1212
1213 /*
1214 * We place the return code in i2c->msg_idx.
1215 */
1216 ret = i2c->msg_idx;
1217
1218 out:
1219 if (timeout == 0) {
1220 i2c_pxa_scream_blue_murder(i2c, "timeout (do_pio_xfer)");
1221 ret = I2C_RETRY;
1222 }
1223
1224 return ret;
1225 }
1226
1227 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
1228 struct i2c_msg msgs[], int num)
1229 {
1230 struct pxa_i2c *i2c = adap->algo_data;
1231
1232 /* If the I2C controller is disabled we need to reset it
1233 (probably due to a suspend/resume destroying state). We do
1234 this here as we can then avoid worrying about resuming the
1235 controller before its users. */
1236 if (!(readl(_ICR(i2c)) & ICR_IUE))
1237 i2c_pxa_reset(i2c);
1238
1239 return i2c_pxa_internal_xfer(i2c, msgs, num, i2c_pxa_do_pio_xfer);
1240 }
1241
1242 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1243 .master_xfer = i2c_pxa_pio_xfer,
1244 .functionality = i2c_pxa_functionality,
1245 #ifdef CONFIG_I2C_PXA_SLAVE
1246 .reg_slave = i2c_pxa_slave_reg,
1247 .unreg_slave = i2c_pxa_slave_unreg,
1248 #endif
1249 };
1250
1251 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1252 enum pxa_i2c_types *i2c_types)
1253 {
1254 struct device_node *np = pdev->dev.of_node;
1255 const struct of_device_id *of_id =
1256 of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1257
1258 if (!of_id)
1259 return 1;
1260
1261 /* For device tree we always use the dynamic or alias-assigned ID */
1262 i2c->adap.nr = -1;
1263
1264 if (of_get_property(np, "mrvl,i2c-polling", NULL))
1265 i2c->use_pio = 1;
1266 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1267 i2c->fast_mode = 1;
1268
1269 *i2c_types = (enum pxa_i2c_types)(of_id->data);
1270
1271 return 0;
1272 }
1273
1274 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1275 struct pxa_i2c *i2c,
1276 enum pxa_i2c_types *i2c_types)
1277 {
1278 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1279 const struct platform_device_id *id = platform_get_device_id(pdev);
1280
1281 *i2c_types = id->driver_data;
1282 if (plat) {
1283 i2c->use_pio = plat->use_pio;
1284 i2c->fast_mode = plat->fast_mode;
1285 i2c->high_mode = plat->high_mode;
1286 i2c->master_code = plat->master_code;
1287 if (!i2c->master_code)
1288 i2c->master_code = 0xe;
1289 i2c->rate = plat->rate;
1290 }
1291 return 0;
1292 }
1293
1294 static void i2c_pxa_prepare_recovery(struct i2c_adapter *adap)
1295 {
1296 struct pxa_i2c *i2c = adap->algo_data;
1297 u32 ibmr = readl(_IBMR(i2c));
1298
1299 /*
1300 * Program the GPIOs to reflect the current I2C bus state while
1301 * we transition to recovery; this avoids glitching the bus.
1302 */
1303 gpiod_set_value(i2c->recovery.scl_gpiod, ibmr & IBMR_SCLS);
1304 gpiod_set_value(i2c->recovery.sda_gpiod, ibmr & IBMR_SDAS);
1305 }
1306
1307 static void i2c_pxa_unprepare_recovery(struct i2c_adapter *adap)
1308 {
1309 struct pxa_i2c *i2c = adap->algo_data;
1310 struct i2c_bus_recovery_info *bri = adap->bus_recovery_info;
1311 u32 isr;
1312
1313 /*
1314 * The bus should now be free. Clear up the I2C controller before
1315 * handing control of the bus back to avoid the bus changing state.
1316 */
1317 isr = readl(_ISR(i2c));
1318 if (isr & (ISR_UB | ISR_IBB)) {
1319 dev_dbg(&i2c->adap.dev,
1320 "recovery: resetting controller, ISR=0x%08x\n", isr);
1321 i2c_pxa_do_reset(i2c);
1322 }
1323
1324 WARN_ON(pinctrl_select_state(bri->pinctrl, bri->pins_default));
1325
1326 dev_dbg(&i2c->adap.dev, "recovery: IBMR 0x%08x ISR 0x%08x\n",
1327 readl(_IBMR(i2c)), readl(_ISR(i2c)));
1328
1329 i2c_pxa_enable(i2c);
1330 }
1331
1332 static int i2c_pxa_init_recovery(struct pxa_i2c *i2c)
1333 {
1334 struct i2c_bus_recovery_info *bri = &i2c->recovery;
1335 struct device *dev = i2c->adap.dev.parent;
1336
1337 /*
1338 * When slave mode is enabled, we are not the only master on the bus.
1339 * Bus recovery can only be performed when we are the master, which
1340 * we can't be certain of. Therefore, when slave mode is enabled, do
1341 * not configure bus recovery.
1342 */
1343 if (IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
1344 return 0;
1345
1346 bri->pinctrl = devm_pinctrl_get(dev);
1347 if (PTR_ERR(bri->pinctrl) == -ENODEV) {
1348 bri->pinctrl = NULL;
1349 return 0;
1350 }
1351 if (IS_ERR(bri->pinctrl))
1352 return PTR_ERR(bri->pinctrl);
1353
1354 bri->prepare_recovery = i2c_pxa_prepare_recovery;
1355 bri->unprepare_recovery = i2c_pxa_unprepare_recovery;
1356
1357 i2c->adap.bus_recovery_info = bri;
1358
1359 return 0;
1360 }
1361
1362 static int i2c_pxa_probe(struct platform_device *dev)
1363 {
1364 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1365 enum pxa_i2c_types i2c_type;
1366 struct pxa_i2c *i2c;
1367 struct resource *res = NULL;
1368 int ret, irq;
1369
1370 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1371 if (!i2c)
1372 return -ENOMEM;
1373
1374 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1375 i2c->adap.nr = dev->id;
1376 i2c->adap.owner = THIS_MODULE;
1377 i2c->adap.retries = 5;
1378 i2c->adap.algo_data = i2c;
1379 i2c->adap.dev.parent = &dev->dev;
1380 #ifdef CONFIG_OF
1381 i2c->adap.dev.of_node = dev->dev.of_node;
1382 #endif
1383
1384 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1385 i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1386 if (IS_ERR(i2c->reg_base))
1387 return PTR_ERR(i2c->reg_base);
1388
1389 irq = platform_get_irq(dev, 0);
1390 if (irq < 0)
1391 return irq;
1392
1393 ret = i2c_pxa_init_recovery(i2c);
1394 if (ret)
1395 return ret;
1396
1397 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1398 if (ret > 0)
1399 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1400 if (ret < 0)
1401 return ret;
1402
1403 spin_lock_init(&i2c->lock);
1404 init_waitqueue_head(&i2c->wait);
1405
1406 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1407
1408 i2c->clk = devm_clk_get(&dev->dev, NULL);
1409 if (IS_ERR(i2c->clk)) {
1410 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1411 return PTR_ERR(i2c->clk);
1412 }
1413
1414 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1415 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1416 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1417 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1418 i2c->fm_mask = pxa_reg_layout[i2c_type].fm;
1419 i2c->hs_mask = pxa_reg_layout[i2c_type].hs;
1420
1421 if (i2c_type != REGS_CE4100)
1422 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1423
1424 if (i2c_type == REGS_PXA910) {
1425 i2c->reg_ilcr = i2c->reg_base + pxa_reg_layout[i2c_type].ilcr;
1426 i2c->reg_iwcr = i2c->reg_base + pxa_reg_layout[i2c_type].iwcr;
1427 }
1428
1429 i2c->iobase = res->start;
1430 i2c->iosize = resource_size(res);
1431
1432 i2c->irq = irq;
1433
1434 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1435 i2c->highmode_enter = false;
1436
1437 if (plat) {
1438 i2c->adap.class = plat->class;
1439 }
1440
1441 if (i2c->high_mode) {
1442 if (i2c->rate) {
1443 clk_set_rate(i2c->clk, i2c->rate);
1444 pr_info("i2c: <%s> set rate to %ld\n",
1445 i2c->adap.name, clk_get_rate(i2c->clk));
1446 } else
1447 pr_warn("i2c: <%s> clock rate not set\n",
1448 i2c->adap.name);
1449 }
1450
1451 clk_prepare_enable(i2c->clk);
1452
1453 if (i2c->use_pio) {
1454 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1455 } else {
1456 i2c->adap.algo = &i2c_pxa_algorithm;
1457 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1458 IRQF_SHARED | IRQF_NO_SUSPEND,
1459 dev_name(&dev->dev), i2c);
1460 if (ret) {
1461 dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1462 goto ereqirq;
1463 }
1464 }
1465
1466 i2c_pxa_reset(i2c);
1467
1468 ret = i2c_add_numbered_adapter(&i2c->adap);
1469 if (ret < 0)
1470 goto ereqirq;
1471
1472 platform_set_drvdata(dev, i2c);
1473
1474 #ifdef CONFIG_I2C_PXA_SLAVE
1475 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1476 i2c->slave_addr);
1477 #else
1478 dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1479 #endif
1480 return 0;
1481
1482 ereqirq:
1483 clk_disable_unprepare(i2c->clk);
1484 return ret;
1485 }
1486
1487 static int i2c_pxa_remove(struct platform_device *dev)
1488 {
1489 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1490
1491 i2c_del_adapter(&i2c->adap);
1492
1493 clk_disable_unprepare(i2c->clk);
1494
1495 return 0;
1496 }
1497
1498 #ifdef CONFIG_PM
1499 static int i2c_pxa_suspend_noirq(struct device *dev)
1500 {
1501 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1502
1503 clk_disable(i2c->clk);
1504
1505 return 0;
1506 }
1507
1508 static int i2c_pxa_resume_noirq(struct device *dev)
1509 {
1510 struct pxa_i2c *i2c = dev_get_drvdata(dev);
1511
1512 clk_enable(i2c->clk);
1513 i2c_pxa_reset(i2c);
1514
1515 return 0;
1516 }
1517
1518 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1519 .suspend_noirq = i2c_pxa_suspend_noirq,
1520 .resume_noirq = i2c_pxa_resume_noirq,
1521 };
1522
1523 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1524 #else
1525 #define I2C_PXA_DEV_PM_OPS NULL
1526 #endif
1527
1528 static struct platform_driver i2c_pxa_driver = {
1529 .probe = i2c_pxa_probe,
1530 .remove = i2c_pxa_remove,
1531 .driver = {
1532 .name = "pxa2xx-i2c",
1533 .pm = I2C_PXA_DEV_PM_OPS,
1534 .of_match_table = i2c_pxa_dt_ids,
1535 },
1536 .id_table = i2c_pxa_id_table,
1537 };
1538
1539 static int __init i2c_adap_pxa_init(void)
1540 {
1541 return platform_driver_register(&i2c_pxa_driver);
1542 }
1543
1544 static void __exit i2c_adap_pxa_exit(void)
1545 {
1546 platform_driver_unregister(&i2c_pxa_driver);
1547 }
1548
1549 MODULE_LICENSE("GPL");
1550 MODULE_ALIAS("platform:pxa2xx-i2c");
1551
1552 subsys_initcall(i2c_adap_pxa_init);
1553 module_exit(i2c_adap_pxa_exit);
Linux with added FPC-III support