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WIP FPC-III support
[linux/fpc-iii.git] / drivers / iio / adc / qcom-spmi-adc5.c
blobc10aa28be70af77f8a6d1c90c021e0d0fb292f98
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitops.h>
7 #include <linux/completion.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/iio/iio.h>
11 #include <linux/interrupt.h>
12 #include <linux/kernel.h>
13 #include <linux/log2.h>
14 #include <linux/math64.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20
21 #include <dt-bindings/iio/qcom,spmi-vadc.h>
22 #include "qcom-vadc-common.h"
23
24 #define ADC5_USR_REVISION1 0x0
25 #define ADC5_USR_STATUS1 0x8
26 #define ADC5_USR_STATUS1_CONV_FAULT BIT(7)
27 #define ADC5_USR_STATUS1_REQ_STS BIT(1)
28 #define ADC5_USR_STATUS1_EOC BIT(0)
29 #define ADC5_USR_STATUS1_REQ_STS_EOC_MASK 0x3
30
31 #define ADC5_USR_STATUS2 0x9
32 #define ADC5_USR_STATUS2_CONV_SEQ_MASK 0x70
33 #define ADC5_USR_STATUS2_CONV_SEQ_MASK_SHIFT 0x5
34
35 #define ADC5_USR_IBAT_MEAS 0xf
36 #define ADC5_USR_IBAT_MEAS_SUPPORTED BIT(0)
37
38 #define ADC5_USR_DIG_PARAM 0x42
39 #define ADC5_USR_DIG_PARAM_CAL_VAL BIT(6)
40 #define ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT 6
41 #define ADC5_USR_DIG_PARAM_CAL_SEL 0x30
42 #define ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT 4
43 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL 0xc
44 #define ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT 2
45
46 #define ADC5_USR_FAST_AVG_CTL 0x43
47 #define ADC5_USR_FAST_AVG_CTL_EN BIT(7)
48 #define ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK 0x7
49
50 #define ADC5_USR_CH_SEL_CTL 0x44
51
52 #define ADC5_USR_DELAY_CTL 0x45
53 #define ADC5_USR_HW_SETTLE_DELAY_MASK 0xf
54
55 #define ADC5_USR_EN_CTL1 0x46
56 #define ADC5_USR_EN_CTL1_ADC_EN BIT(7)
57
58 #define ADC5_USR_CONV_REQ 0x47
59 #define ADC5_USR_CONV_REQ_REQ BIT(7)
60
61 #define ADC5_USR_DATA0 0x50
62
63 #define ADC5_USR_DATA1 0x51
64
65 #define ADC5_USR_IBAT_DATA0 0x52
66
67 #define ADC5_USR_IBAT_DATA1 0x53
68
69 #define ADC_CHANNEL_OFFSET 0x8
70 #define ADC_CHANNEL_MASK GENMASK(7, 0)
71
72 /*
73 * Conversion time varies based on the decimation, clock rate, fast average
74 * samples and measurements queued across different VADC peripherals.
75 * Set the timeout to a max of 100ms.
76 */
77 #define ADC5_CONV_TIME_MIN_US 263
78 #define ADC5_CONV_TIME_MAX_US 264
79 #define ADC5_CONV_TIME_RETRY 400
80 #define ADC5_CONV_TIMEOUT msecs_to_jiffies(100)
81
82 /* Digital version >= 5.3 supports hw_settle_2 */
83 #define ADC5_HW_SETTLE_DIFF_MINOR 3
84 #define ADC5_HW_SETTLE_DIFF_MAJOR 5
85
86 /* For PMIC7 */
87 #define ADC_APP_SID 0x40
88 #define ADC_APP_SID_MASK GENMASK(3, 0)
89 #define ADC7_CONV_TIMEOUT msecs_to_jiffies(10)
90
91 enum adc5_cal_method {
92 ADC5_NO_CAL = 0,
93 ADC5_RATIOMETRIC_CAL,
94 ADC5_ABSOLUTE_CAL
95 };
96
97 enum adc5_cal_val {
98 ADC5_TIMER_CAL = 0,
99 ADC5_NEW_CAL
100 };
101
102 /**
103 * struct adc5_channel_prop - ADC channel property.
104 * @channel: channel number, refer to the channel list.
105 * @cal_method: calibration method.
106 * @cal_val: calibration value
107 * @decimation: sampling rate supported for the channel.
108 * @sid: slave id of PMIC owning the channel, for PMIC7.
109 * @prescale: channel scaling performed on the input signal.
110 * @hw_settle_time: the time between AMUX being configured and the
111 * start of conversion.
112 * @avg_samples: ability to provide single result from the ADC
113 * that is an average of multiple measurements.
114 * @scale_fn_type: Represents the scaling function to convert voltage
115 * physical units desired by the client for the channel.
116 * @datasheet_name: Channel name used in device tree.
117 */
118 struct adc5_channel_prop {
119 unsigned int channel;
120 enum adc5_cal_method cal_method;
121 enum adc5_cal_val cal_val;
122 unsigned int decimation;
123 unsigned int sid;
124 unsigned int prescale;
125 unsigned int hw_settle_time;
126 unsigned int avg_samples;
127 enum vadc_scale_fn_type scale_fn_type;
128 const char *datasheet_name;
129 };
130
131 /**
132 * struct adc5_chip - ADC private structure.
133 * @regmap: SPMI ADC5 peripheral register map field.
134 * @dev: SPMI ADC5 device.
135 * @base: base address for the ADC peripheral.
136 * @nchannels: number of ADC channels.
137 * @chan_props: array of ADC channel properties.
138 * @iio_chans: array of IIO channels specification.
139 * @poll_eoc: use polling instead of interrupt.
140 * @complete: ADC result notification after interrupt is received.
141 * @lock: ADC lock for access to the peripheral.
142 * @data: software configuration data.
143 */
144 struct adc5_chip {
145 struct regmap *regmap;
146 struct device *dev;
147 u16 base;
148 unsigned int nchannels;
149 struct adc5_channel_prop *chan_props;
150 struct iio_chan_spec *iio_chans;
151 bool poll_eoc;
152 struct completion complete;
153 struct mutex lock;
154 const struct adc5_data *data;
155 };
156
157 static const struct vadc_prescale_ratio adc5_prescale_ratios[] = {
158 {.num = 1, .den = 1},
159 {.num = 1, .den = 3},
160 {.num = 1, .den = 4},
161 {.num = 1, .den = 6},
162 {.num = 1, .den = 20},
163 {.num = 1, .den = 8},
164 {.num = 10, .den = 81},
165 {.num = 1, .den = 10},
166 {.num = 1, .den = 16}
167 };
168
169 static int adc5_read(struct adc5_chip *adc, u16 offset, u8 *data, int len)
170 {
171 return regmap_bulk_read(adc->regmap, adc->base + offset, data, len);
172 }
173
174 static int adc5_write(struct adc5_chip *adc, u16 offset, u8 *data, int len)
175 {
176 return regmap_bulk_write(adc->regmap, adc->base + offset, data, len);
177 }
178
179 static int adc5_masked_write(struct adc5_chip *adc, u16 offset, u8 mask, u8 val)
180 {
181 return regmap_update_bits(adc->regmap, adc->base + offset, mask, val);
182 }
183
184 static int adc5_prescaling_from_dt(u32 num, u32 den)
185 {
186 unsigned int pre;
187
188 for (pre = 0; pre < ARRAY_SIZE(adc5_prescale_ratios); pre++)
189 if (adc5_prescale_ratios[pre].num == num &&
190 adc5_prescale_ratios[pre].den == den)
191 break;
192
193 if (pre == ARRAY_SIZE(adc5_prescale_ratios))
194 return -EINVAL;
195
196 return pre;
197 }
198
199 static int adc5_hw_settle_time_from_dt(u32 value,
200 const unsigned int *hw_settle)
201 {
202 unsigned int i;
203
204 for (i = 0; i < VADC_HW_SETTLE_SAMPLES_MAX; i++) {
205 if (value == hw_settle[i])
206 return i;
207 }
208
209 return -EINVAL;
210 }
211
212 static int adc5_avg_samples_from_dt(u32 value)
213 {
214 if (!is_power_of_2(value) || value > ADC5_AVG_SAMPLES_MAX)
215 return -EINVAL;
216
217 return __ffs(value);
218 }
219
220 static int adc5_decimation_from_dt(u32 value,
221 const unsigned int *decimation)
222 {
223 unsigned int i;
224
225 for (i = 0; i < ADC5_DECIMATION_SAMPLES_MAX; i++) {
226 if (value == decimation[i])
227 return i;
228 }
229
230 return -EINVAL;
231 }
232
233 static int adc5_read_voltage_data(struct adc5_chip *adc, u16 *data)
234 {
235 int ret;
236 u8 rslt_lsb, rslt_msb;
237
238 ret = adc5_read(adc, ADC5_USR_DATA0, &rslt_lsb, sizeof(rslt_lsb));
239 if (ret)
240 return ret;
241
242 ret = adc5_read(adc, ADC5_USR_DATA1, &rslt_msb, sizeof(rslt_lsb));
243 if (ret)
244 return ret;
245
246 *data = (rslt_msb << 8) | rslt_lsb;
247
248 if (*data == ADC5_USR_DATA_CHECK) {
249 dev_err(adc->dev, "Invalid data:0x%x\n", *data);
250 return -EINVAL;
251 }
252
253 dev_dbg(adc->dev, "voltage raw code:0x%x\n", *data);
254
255 return 0;
256 }
257
258 static int adc5_poll_wait_eoc(struct adc5_chip *adc)
259 {
260 unsigned int count, retry = ADC5_CONV_TIME_RETRY;
261 u8 status1;
262 int ret;
263
264 for (count = 0; count < retry; count++) {
265 ret = adc5_read(adc, ADC5_USR_STATUS1, &status1,
266 sizeof(status1));
267 if (ret)
268 return ret;
269
270 status1 &= ADC5_USR_STATUS1_REQ_STS_EOC_MASK;
271 if (status1 == ADC5_USR_STATUS1_EOC)
272 return 0;
273
274 usleep_range(ADC5_CONV_TIME_MIN_US, ADC5_CONV_TIME_MAX_US);
275 }
276
277 return -ETIMEDOUT;
278 }
279
280 static void adc5_update_dig_param(struct adc5_chip *adc,
281 struct adc5_channel_prop *prop, u8 *data)
282 {
283 /* Update calibration value */
284 *data &= ~ADC5_USR_DIG_PARAM_CAL_VAL;
285 *data |= (prop->cal_val << ADC5_USR_DIG_PARAM_CAL_VAL_SHIFT);
286
287 /* Update calibration select */
288 *data &= ~ADC5_USR_DIG_PARAM_CAL_SEL;
289 *data |= (prop->cal_method << ADC5_USR_DIG_PARAM_CAL_SEL_SHIFT);
290
291 /* Update decimation ratio select */
292 *data &= ~ADC5_USR_DIG_PARAM_DEC_RATIO_SEL;
293 *data |= (prop->decimation << ADC5_USR_DIG_PARAM_DEC_RATIO_SEL_SHIFT);
294 }
295
296 static int adc5_configure(struct adc5_chip *adc,
297 struct adc5_channel_prop *prop)
298 {
299 int ret;
300 u8 buf[6];
301
302 /* Read registers 0x42 through 0x46 */
303 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
304 if (ret)
305 return ret;
306
307 /* Digital param selection */
308 adc5_update_dig_param(adc, prop, &buf[0]);
309
310 /* Update fast average sample value */
311 buf[1] &= (u8) ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
312 buf[1] |= prop->avg_samples;
313
314 /* Select ADC channel */
315 buf[2] = prop->channel;
316
317 /* Select HW settle delay for channel */
318 buf[3] &= (u8) ~ADC5_USR_HW_SETTLE_DELAY_MASK;
319 buf[3] |= prop->hw_settle_time;
320
321 /* Select ADC enable */
322 buf[4] |= ADC5_USR_EN_CTL1_ADC_EN;
323
324 /* Select CONV request */
325 buf[5] |= ADC5_USR_CONV_REQ_REQ;
326
327 if (!adc->poll_eoc)
328 reinit_completion(&adc->complete);
329
330 return adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
331 }
332
333 static int adc7_configure(struct adc5_chip *adc,
334 struct adc5_channel_prop *prop)
335 {
336 int ret;
337 u8 conv_req = 0, buf[4];
338
339 ret = adc5_masked_write(adc, ADC_APP_SID, ADC_APP_SID_MASK, prop->sid);
340 if (ret)
341 return ret;
342
343 ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
344 if (ret)
345 return ret;
346
347 /* Digital param selection */
348 adc5_update_dig_param(adc, prop, &buf[0]);
349
350 /* Update fast average sample value */
351 buf[1] &= ~ADC5_USR_FAST_AVG_CTL_SAMPLES_MASK;
352 buf[1] |= prop->avg_samples;
353
354 /* Select ADC channel */
355 buf[2] = prop->channel;
356
357 /* Select HW settle delay for channel */
358 buf[3] &= ~ADC5_USR_HW_SETTLE_DELAY_MASK;
359 buf[3] |= prop->hw_settle_time;
360
361 /* Select CONV request */
362 conv_req = ADC5_USR_CONV_REQ_REQ;
363
364 if (!adc->poll_eoc)
365 reinit_completion(&adc->complete);
366
367 ret = adc5_write(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
368 if (ret)
369 return ret;
370
371 return adc5_write(adc, ADC5_USR_CONV_REQ, &conv_req, 1);
372 }
373
374 static int adc5_do_conversion(struct adc5_chip *adc,
375 struct adc5_channel_prop *prop,
376 struct iio_chan_spec const *chan,
377 u16 *data_volt, u16 *data_cur)
378 {
379 int ret;
380
381 mutex_lock(&adc->lock);
382
383 ret = adc5_configure(adc, prop);
384 if (ret) {
385 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
386 goto unlock;
387 }
388
389 if (adc->poll_eoc) {
390 ret = adc5_poll_wait_eoc(adc);
391 if (ret) {
392 dev_err(adc->dev, "EOC bit not set\n");
393 goto unlock;
394 }
395 } else {
396 ret = wait_for_completion_timeout(&adc->complete,
397 ADC5_CONV_TIMEOUT);
398 if (!ret) {
399 dev_dbg(adc->dev, "Did not get completion timeout.\n");
400 ret = adc5_poll_wait_eoc(adc);
401 if (ret) {
402 dev_err(adc->dev, "EOC bit not set\n");
403 goto unlock;
404 }
405 }
406 }
407
408 ret = adc5_read_voltage_data(adc, data_volt);
409 unlock:
410 mutex_unlock(&adc->lock);
411
412 return ret;
413 }
414
415 static int adc7_do_conversion(struct adc5_chip *adc,
416 struct adc5_channel_prop *prop,
417 struct iio_chan_spec const *chan,
418 u16 *data_volt, u16 *data_cur)
419 {
420 int ret;
421 u8 status;
422
423 mutex_lock(&adc->lock);
424
425 ret = adc7_configure(adc, prop);
426 if (ret) {
427 dev_err(adc->dev, "ADC configure failed with %d\n", ret);
428 goto unlock;
429 }
430
431 /* No support for polling mode at present */
432 wait_for_completion_timeout(&adc->complete, ADC7_CONV_TIMEOUT);
433
434 ret = adc5_read(adc, ADC5_USR_STATUS1, &status, 1);
435 if (ret)
436 goto unlock;
437
438 if (status & ADC5_USR_STATUS1_CONV_FAULT) {
439 dev_err(adc->dev, "Unexpected conversion fault\n");
440 ret = -EIO;
441 goto unlock;
442 }
443
444 ret = adc5_read_voltage_data(adc, data_volt);
445
446 unlock:
447 mutex_unlock(&adc->lock);
448
449 return ret;
450 }
451
452 typedef int (*adc_do_conversion)(struct adc5_chip *adc,
453 struct adc5_channel_prop *prop,
454 struct iio_chan_spec const *chan,
455 u16 *data_volt, u16 *data_cur);
456
457 static irqreturn_t adc5_isr(int irq, void *dev_id)
458 {
459 struct adc5_chip *adc = dev_id;
460
461 complete(&adc->complete);
462
463 return IRQ_HANDLED;
464 }
465
466 static int adc5_of_xlate(struct iio_dev *indio_dev,
467 const struct of_phandle_args *iiospec)
468 {
469 struct adc5_chip *adc = iio_priv(indio_dev);
470 int i;
471
472 for (i = 0; i < adc->nchannels; i++)
473 if (adc->chan_props[i].channel == iiospec->args[0])
474 return i;
475
476 return -EINVAL;
477 }
478
479 static int adc7_of_xlate(struct iio_dev *indio_dev,
480 const struct of_phandle_args *iiospec)
481 {
482 struct adc5_chip *adc = iio_priv(indio_dev);
483 int i, v_channel;
484
485 for (i = 0; i < adc->nchannels; i++) {
486 v_channel = (adc->chan_props[i].sid << ADC_CHANNEL_OFFSET) |
487 adc->chan_props[i].channel;
488 if (v_channel == iiospec->args[0])
489 return i;
490 }
491
492 return -EINVAL;
493 }
494
495 static int adc_read_raw_common(struct iio_dev *indio_dev,
496 struct iio_chan_spec const *chan, int *val, int *val2,
497 long mask, adc_do_conversion do_conv)
498 {
499 struct adc5_chip *adc = iio_priv(indio_dev);
500 struct adc5_channel_prop *prop;
501 u16 adc_code_volt, adc_code_cur;
502 int ret;
503
504 prop = &adc->chan_props[chan->address];
505
506 switch (mask) {
507 case IIO_CHAN_INFO_PROCESSED:
508 ret = do_conv(adc, prop, chan,
509 &adc_code_volt, &adc_code_cur);
510 if (ret)
511 return ret;
512
513 ret = qcom_adc5_hw_scale(prop->scale_fn_type,
514 &adc5_prescale_ratios[prop->prescale],
515 adc->data,
516 adc_code_volt, val);
517 if (ret)
518 return ret;
519
520 return IIO_VAL_INT;
521 default:
522 return -EINVAL;
523 }
524 }
525
526 static int adc5_read_raw(struct iio_dev *indio_dev,
527 struct iio_chan_spec const *chan, int *val, int *val2,
528 long mask)
529 {
530 return adc_read_raw_common(indio_dev, chan, val, val2,
531 mask, adc5_do_conversion);
532 }
533
534 static int adc7_read_raw(struct iio_dev *indio_dev,
535 struct iio_chan_spec const *chan, int *val, int *val2,
536 long mask)
537 {
538 return adc_read_raw_common(indio_dev, chan, val, val2,
539 mask, adc7_do_conversion);
540 }
541
542 static const struct iio_info adc5_info = {
543 .read_raw = adc5_read_raw,
544 .of_xlate = adc5_of_xlate,
545 };
546
547 static const struct iio_info adc7_info = {
548 .read_raw = adc7_read_raw,
549 .of_xlate = adc7_of_xlate,
550 };
551
552 struct adc5_channels {
553 const char *datasheet_name;
554 unsigned int prescale_index;
555 enum iio_chan_type type;
556 long info_mask;
557 enum vadc_scale_fn_type scale_fn_type;
558 };
559
560 /* In these definitions, _pre refers to an index into adc5_prescale_ratios. */
561 #define ADC5_CHAN(_dname, _type, _mask, _pre, _scale) \
562 { \
563 .datasheet_name = _dname, \
564 .prescale_index = _pre, \
565 .type = _type, \
566 .info_mask = _mask, \
567 .scale_fn_type = _scale, \
568 }, \
569
570 #define ADC5_CHAN_TEMP(_dname, _pre, _scale) \
571 ADC5_CHAN(_dname, IIO_TEMP, \
572 BIT(IIO_CHAN_INFO_PROCESSED), \
573 _pre, _scale) \
574
575 #define ADC5_CHAN_VOLT(_dname, _pre, _scale) \
576 ADC5_CHAN(_dname, IIO_VOLTAGE, \
577 BIT(IIO_CHAN_INFO_PROCESSED), \
578 _pre, _scale) \
579
580 static const struct adc5_channels adc5_chans_pmic[ADC5_MAX_CHANNEL] = {
581 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
582 SCALE_HW_CALIB_DEFAULT)
583 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
584 SCALE_HW_CALIB_DEFAULT)
585 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
586 SCALE_HW_CALIB_DEFAULT)
587 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
588 SCALE_HW_CALIB_DEFAULT)
589 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
590 SCALE_HW_CALIB_PMIC_THERM)
591 [ADC5_USB_IN_I] = ADC5_CHAN_VOLT("usb_in_i_uv", 0,
592 SCALE_HW_CALIB_DEFAULT)
593 [ADC5_USB_IN_V_16] = ADC5_CHAN_VOLT("usb_in_v_div_16", 8,
594 SCALE_HW_CALIB_DEFAULT)
595 [ADC5_CHG_TEMP] = ADC5_CHAN_TEMP("chg_temp", 0,
596 SCALE_HW_CALIB_PM5_CHG_TEMP)
597 /* Charger prescales SBUx and MID_CHG to fit within 1.8V upper unit */
598 [ADC5_SBUx] = ADC5_CHAN_VOLT("chg_sbux", 1,
599 SCALE_HW_CALIB_DEFAULT)
600 [ADC5_MID_CHG_DIV6] = ADC5_CHAN_VOLT("chg_mid_chg", 3,
601 SCALE_HW_CALIB_DEFAULT)
602 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm", 0,
603 SCALE_HW_CALIB_XOTHERM)
604 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
605 SCALE_HW_CALIB_THERM_100K_PULLUP)
606 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
607 SCALE_HW_CALIB_THERM_100K_PULLUP)
608 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
609 SCALE_HW_CALIB_THERM_100K_PULLUP)
610 [ADC5_AMUX_THM2] = ADC5_CHAN_TEMP("amux_thm2", 0,
611 SCALE_HW_CALIB_PM5_SMB_TEMP)
612 };
613
614 static const struct adc5_channels adc7_chans_pmic[ADC5_MAX_CHANNEL] = {
615 [ADC7_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
616 SCALE_HW_CALIB_DEFAULT)
617 [ADC7_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
618 SCALE_HW_CALIB_DEFAULT)
619 [ADC7_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
620 SCALE_HW_CALIB_DEFAULT)
621 [ADC7_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 3,
622 SCALE_HW_CALIB_DEFAULT)
623 [ADC7_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
624 SCALE_HW_CALIB_PMIC_THERM_PM7)
625 [ADC7_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_pu2", 0,
626 SCALE_HW_CALIB_THERM_100K_PU_PM7)
627 [ADC7_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_pu2", 0,
628 SCALE_HW_CALIB_THERM_100K_PU_PM7)
629 [ADC7_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_pu2", 0,
630 SCALE_HW_CALIB_THERM_100K_PU_PM7)
631 [ADC7_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_pu2", 0,
632 SCALE_HW_CALIB_THERM_100K_PU_PM7)
633 [ADC7_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_pu2", 0,
634 SCALE_HW_CALIB_THERM_100K_PU_PM7)
635 [ADC7_AMUX_THM6_100K_PU] = ADC5_CHAN_TEMP("amux_thm6_pu2", 0,
636 SCALE_HW_CALIB_THERM_100K_PU_PM7)
637 [ADC7_GPIO1_100K_PU] = ADC5_CHAN_TEMP("gpio1_pu2", 0,
638 SCALE_HW_CALIB_THERM_100K_PU_PM7)
639 [ADC7_GPIO2_100K_PU] = ADC5_CHAN_TEMP("gpio2_pu2", 0,
640 SCALE_HW_CALIB_THERM_100K_PU_PM7)
641 [ADC7_GPIO3_100K_PU] = ADC5_CHAN_TEMP("gpio3_pu2", 0,
642 SCALE_HW_CALIB_THERM_100K_PU_PM7)
643 [ADC7_GPIO4_100K_PU] = ADC5_CHAN_TEMP("gpio4_pu2", 0,
644 SCALE_HW_CALIB_THERM_100K_PU_PM7)
645 };
646
647 static const struct adc5_channels adc5_chans_rev2[ADC5_MAX_CHANNEL] = {
648 [ADC5_REF_GND] = ADC5_CHAN_VOLT("ref_gnd", 0,
649 SCALE_HW_CALIB_DEFAULT)
650 [ADC5_1P25VREF] = ADC5_CHAN_VOLT("vref_1p25", 0,
651 SCALE_HW_CALIB_DEFAULT)
652 [ADC5_VPH_PWR] = ADC5_CHAN_VOLT("vph_pwr", 1,
653 SCALE_HW_CALIB_DEFAULT)
654 [ADC5_VBAT_SNS] = ADC5_CHAN_VOLT("vbat_sns", 1,
655 SCALE_HW_CALIB_DEFAULT)
656 [ADC5_VCOIN] = ADC5_CHAN_VOLT("vcoin", 1,
657 SCALE_HW_CALIB_DEFAULT)
658 [ADC5_DIE_TEMP] = ADC5_CHAN_TEMP("die_temp", 0,
659 SCALE_HW_CALIB_PMIC_THERM)
660 [ADC5_AMUX_THM1_100K_PU] = ADC5_CHAN_TEMP("amux_thm1_100k_pu", 0,
661 SCALE_HW_CALIB_THERM_100K_PULLUP)
662 [ADC5_AMUX_THM2_100K_PU] = ADC5_CHAN_TEMP("amux_thm2_100k_pu", 0,
663 SCALE_HW_CALIB_THERM_100K_PULLUP)
664 [ADC5_AMUX_THM3_100K_PU] = ADC5_CHAN_TEMP("amux_thm3_100k_pu", 0,
665 SCALE_HW_CALIB_THERM_100K_PULLUP)
666 [ADC5_AMUX_THM4_100K_PU] = ADC5_CHAN_TEMP("amux_thm4_100k_pu", 0,
667 SCALE_HW_CALIB_THERM_100K_PULLUP)
668 [ADC5_AMUX_THM5_100K_PU] = ADC5_CHAN_TEMP("amux_thm5_100k_pu", 0,
669 SCALE_HW_CALIB_THERM_100K_PULLUP)
670 [ADC5_XO_THERM_100K_PU] = ADC5_CHAN_TEMP("xo_therm_100k_pu", 0,
671 SCALE_HW_CALIB_THERM_100K_PULLUP)
672 };
673
674 static int adc5_get_dt_channel_data(struct adc5_chip *adc,
675 struct adc5_channel_prop *prop,
676 struct device_node *node,
677 const struct adc5_data *data)
678 {
679 const char *name = node->name, *channel_name;
680 u32 chan, value, varr[2];
681 u32 sid = 0;
682 int ret;
683 struct device *dev = adc->dev;
684
685 ret = of_property_read_u32(node, "reg", &chan);
686 if (ret) {
687 dev_err(dev, "invalid channel number %s\n", name);
688 return ret;
689 }
690
691 /* Value read from "reg" is virtual channel number */
692
693 /* virtual channel number = sid << 8 | channel number */
694
695 if (adc->data->info == &adc7_info) {
696 sid = chan >> ADC_CHANNEL_OFFSET;
697 chan = chan & ADC_CHANNEL_MASK;
698 }
699
700 if (chan > ADC5_PARALLEL_ISENSE_VBAT_IDATA ||
701 !data->adc_chans[chan].datasheet_name) {
702 dev_err(dev, "%s invalid channel number %d\n", name, chan);
703 return -EINVAL;
704 }
705
706 /* the channel has DT description */
707 prop->channel = chan;
708 prop->sid = sid;
709
710 channel_name = of_get_property(node,
711 "label", NULL) ? : node->name;
712 if (!channel_name) {
713 dev_err(dev, "Invalid channel name\n");
714 return -EINVAL;
715 }
716 prop->datasheet_name = channel_name;
717
718 ret = of_property_read_u32(node, "qcom,decimation", &value);
719 if (!ret) {
720 ret = adc5_decimation_from_dt(value, data->decimation);
721 if (ret < 0) {
722 dev_err(dev, "%02x invalid decimation %d\n",
723 chan, value);
724 return ret;
725 }
726 prop->decimation = ret;
727 } else {
728 prop->decimation = ADC5_DECIMATION_DEFAULT;
729 }
730
731 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
732 if (!ret) {
733 ret = adc5_prescaling_from_dt(varr[0], varr[1]);
734 if (ret < 0) {
735 dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
736 chan, varr[0], varr[1]);
737 return ret;
738 }
739 prop->prescale = ret;
740 } else {
741 prop->prescale =
742 adc->data->adc_chans[prop->channel].prescale_index;
743 }
744
745 ret = of_property_read_u32(node, "qcom,hw-settle-time", &value);
746 if (!ret) {
747 u8 dig_version[2];
748
749 ret = adc5_read(adc, ADC5_USR_REVISION1, dig_version,
750 sizeof(dig_version));
751 if (ret) {
752 dev_err(dev, "Invalid dig version read %d\n", ret);
753 return ret;
754 }
755
756 dev_dbg(dev, "dig_ver:minor:%d, major:%d\n", dig_version[0],
757 dig_version[1]);
758 /* Digital controller >= 5.3 have hw_settle_2 option */
759 if ((dig_version[0] >= ADC5_HW_SETTLE_DIFF_MINOR &&
760 dig_version[1] >= ADC5_HW_SETTLE_DIFF_MAJOR) ||
761 adc->data->info == &adc7_info)
762 ret = adc5_hw_settle_time_from_dt(value,
763 data->hw_settle_2);
764 else
765 ret = adc5_hw_settle_time_from_dt(value,
766 data->hw_settle_1);
767
768 if (ret < 0) {
769 dev_err(dev, "%02x invalid hw-settle-time %d us\n",
770 chan, value);
771 return ret;
772 }
773 prop->hw_settle_time = ret;
774 } else {
775 prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
776 }
777
778 ret = of_property_read_u32(node, "qcom,avg-samples", &value);
779 if (!ret) {
780 ret = adc5_avg_samples_from_dt(value);
781 if (ret < 0) {
782 dev_err(dev, "%02x invalid avg-samples %d\n",
783 chan, value);
784 return ret;
785 }
786 prop->avg_samples = ret;
787 } else {
788 prop->avg_samples = VADC_DEF_AVG_SAMPLES;
789 }
790
791 if (of_property_read_bool(node, "qcom,ratiometric"))
792 prop->cal_method = ADC5_RATIOMETRIC_CAL;
793 else
794 prop->cal_method = ADC5_ABSOLUTE_CAL;
795
796 /*
797 * Default to using timer calibration. Using a fresh calibration value
798 * for every conversion will increase the overall time for a request.
799 */
800 prop->cal_val = ADC5_TIMER_CAL;
801
802 dev_dbg(dev, "%02x name %s\n", chan, name);
803
804 return 0;
805 }
806
807 static const struct adc5_data adc5_data_pmic = {
808 .full_scale_code_volt = 0x70e4,
809 .full_scale_code_cur = 0x2710,
810 .adc_chans = adc5_chans_pmic,
811 .info = &adc5_info,
812 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
813 {250, 420, 840},
814 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
815 {15, 100, 200, 300, 400, 500, 600, 700,
816 800, 900, 1, 2, 4, 6, 8, 10},
817 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
818 {15, 100, 200, 300, 400, 500, 600, 700,
819 1, 2, 4, 8, 16, 32, 64, 128},
820 };
821
822 static const struct adc5_data adc7_data_pmic = {
823 .full_scale_code_volt = 0x70e4,
824 .adc_chans = adc7_chans_pmic,
825 .info = &adc7_info,
826 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
827 {85, 340, 1360},
828 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
829 {15, 100, 200, 300, 400, 500, 600, 700,
830 1000, 2000, 4000, 8000, 16000, 32000,
831 64000, 128000},
832 };
833
834 static const struct adc5_data adc5_data_pmic_rev2 = {
835 .full_scale_code_volt = 0x4000,
836 .full_scale_code_cur = 0x1800,
837 .adc_chans = adc5_chans_rev2,
838 .info = &adc5_info,
839 .decimation = (unsigned int [ADC5_DECIMATION_SAMPLES_MAX])
840 {256, 512, 1024},
841 .hw_settle_1 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
842 {0, 100, 200, 300, 400, 500, 600, 700,
843 800, 900, 1, 2, 4, 6, 8, 10},
844 .hw_settle_2 = (unsigned int [VADC_HW_SETTLE_SAMPLES_MAX])
845 {15, 100, 200, 300, 400, 500, 600, 700,
846 1, 2, 4, 8, 16, 32, 64, 128},
847 };
848
849 static const struct of_device_id adc5_match_table[] = {
850 {
851 .compatible = "qcom,spmi-adc5",
852 .data = &adc5_data_pmic,
853 },
854 {
855 .compatible = "qcom,spmi-adc7",
856 .data = &adc7_data_pmic,
857 },
858 {
859 .compatible = "qcom,spmi-adc-rev2",
860 .data = &adc5_data_pmic_rev2,
861 },
862 { }
863 };
864 MODULE_DEVICE_TABLE(of, adc5_match_table);
865
866 static int adc5_get_dt_data(struct adc5_chip *adc, struct device_node *node)
867 {
868 const struct adc5_channels *adc_chan;
869 struct iio_chan_spec *iio_chan;
870 struct adc5_channel_prop prop, *chan_props;
871 struct device_node *child;
872 unsigned int index = 0;
873 const struct of_device_id *id;
874 const struct adc5_data *data;
875 int ret;
876
877 adc->nchannels = of_get_available_child_count(node);
878 if (!adc->nchannels)
879 return -EINVAL;
880
881 adc->iio_chans = devm_kcalloc(adc->dev, adc->nchannels,
882 sizeof(*adc->iio_chans), GFP_KERNEL);
883 if (!adc->iio_chans)
884 return -ENOMEM;
885
886 adc->chan_props = devm_kcalloc(adc->dev, adc->nchannels,
887 sizeof(*adc->chan_props), GFP_KERNEL);
888 if (!adc->chan_props)
889 return -ENOMEM;
890
891 chan_props = adc->chan_props;
892 iio_chan = adc->iio_chans;
893 id = of_match_node(adc5_match_table, node);
894 if (id)
895 data = id->data;
896 else
897 data = &adc5_data_pmic;
898 adc->data = data;
899
900 for_each_available_child_of_node(node, child) {
901 ret = adc5_get_dt_channel_data(adc, &prop, child, data);
902 if (ret) {
903 of_node_put(child);
904 return ret;
905 }
906
907 prop.scale_fn_type =
908 data->adc_chans[prop.channel].scale_fn_type;
909 *chan_props = prop;
910 adc_chan = &data->adc_chans[prop.channel];
911
912 iio_chan->channel = prop.channel;
913 iio_chan->datasheet_name = prop.datasheet_name;
914 iio_chan->extend_name = prop.datasheet_name;
915 iio_chan->info_mask_separate = adc_chan->info_mask;
916 iio_chan->type = adc_chan->type;
917 iio_chan->address = index;
918 iio_chan++;
919 chan_props++;
920 index++;
921 }
922
923 return 0;
924 }
925
926 static int adc5_probe(struct platform_device *pdev)
927 {
928 struct device_node *node = pdev->dev.of_node;
929 struct device *dev = &pdev->dev;
930 struct iio_dev *indio_dev;
931 struct adc5_chip *adc;
932 struct regmap *regmap;
933 int ret, irq_eoc;
934 u32 reg;
935
936 regmap = dev_get_regmap(dev->parent, NULL);
937 if (!regmap)
938 return -ENODEV;
939
940 ret = of_property_read_u32(node, "reg", &reg);
941 if (ret < 0)
942 return ret;
943
944 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
945 if (!indio_dev)
946 return -ENOMEM;
947
948 adc = iio_priv(indio_dev);
949 adc->regmap = regmap;
950 adc->dev = dev;
951 adc->base = reg;
952
953 init_completion(&adc->complete);
954 mutex_init(&adc->lock);
955
956 ret = adc5_get_dt_data(adc, node);
957 if (ret) {
958 dev_err(dev, "adc get dt data failed\n");
959 return ret;
960 }
961
962 irq_eoc = platform_get_irq(pdev, 0);
963 if (irq_eoc < 0) {
964 if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
965 return irq_eoc;
966 adc->poll_eoc = true;
967 } else {
968 ret = devm_request_irq(dev, irq_eoc, adc5_isr, 0,
969 "pm-adc5", adc);
970 if (ret)
971 return ret;
972 }
973
974 indio_dev->name = pdev->name;
975 indio_dev->modes = INDIO_DIRECT_MODE;
976 indio_dev->info = adc->data->info;
977 indio_dev->channels = adc->iio_chans;
978 indio_dev->num_channels = adc->nchannels;
979
980 return devm_iio_device_register(dev, indio_dev);
981 }
982
983 static struct platform_driver adc5_driver = {
984 .driver = {
985 .name = "qcom-spmi-adc5",
986 .of_match_table = adc5_match_table,
987 },
988 .probe = adc5_probe,
989 };
990 module_platform_driver(adc5_driver);
991
992 MODULE_ALIAS("platform:qcom-spmi-adc5");
993 MODULE_DESCRIPTION("Qualcomm Technologies Inc. PMIC5 ADC driver");
994 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support