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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / ethernet / intel / e1000e / hw.h
blob69a2329ea463d7bfe428b7e39539e61921680999
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #ifndef _E1000_HW_H_
5 #define _E1000_HW_H_
6
7 #include "regs.h"
8 #include "defines.h"
9
10 struct e1000_hw;
11
12 #define E1000_DEV_ID_82571EB_COPPER 0x105E
13 #define E1000_DEV_ID_82571EB_FIBER 0x105F
14 #define E1000_DEV_ID_82571EB_SERDES 0x1060
15 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
16 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
17 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
18 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
19 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
20 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
21 #define E1000_DEV_ID_82572EI_COPPER 0x107D
22 #define E1000_DEV_ID_82572EI_FIBER 0x107E
23 #define E1000_DEV_ID_82572EI_SERDES 0x107F
24 #define E1000_DEV_ID_82572EI 0x10B9
25 #define E1000_DEV_ID_82573E 0x108B
26 #define E1000_DEV_ID_82573E_IAMT 0x108C
27 #define E1000_DEV_ID_82573L 0x109A
28 #define E1000_DEV_ID_82574L 0x10D3
29 #define E1000_DEV_ID_82574LA 0x10F6
30 #define E1000_DEV_ID_82583V 0x150C
31 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
32 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
33 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
34 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
35 #define E1000_DEV_ID_ICH8_82567V_3 0x1501
36 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
37 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
38 #define E1000_DEV_ID_ICH8_IGP_C 0x104B
39 #define E1000_DEV_ID_ICH8_IFE 0x104C
40 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
41 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5
42 #define E1000_DEV_ID_ICH8_IGP_M 0x104D
43 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
44 #define E1000_DEV_ID_ICH9_BM 0x10E5
45 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
46 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF
47 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
48 #define E1000_DEV_ID_ICH9_IGP_C 0x294C
49 #define E1000_DEV_ID_ICH9_IFE 0x10C0
50 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
51 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2
52 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
53 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
54 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
55 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
56 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
57 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525
58 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
59 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
60 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
61 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
62 #define E1000_DEV_ID_PCH2_LV_LM 0x1502
63 #define E1000_DEV_ID_PCH2_LV_V 0x1503
64 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
65 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
66 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
67 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
68 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0
69 #define E1000_DEV_ID_PCH_I218_V2 0x15A1
70 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
71 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
72 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* SPT PCH */
73 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* SPT PCH */
74 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* SPT-H PCH */
75 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* SPT-H PCH */
76 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LBG PCH */
77 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7
78 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
79 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
80 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
81 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
82 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
83 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
84 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
85 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF
86 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0
87 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1
88 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2
89 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E
90 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F
91 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C
92 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D
93 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53
94 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55
95 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB
96 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC
97 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9
98 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA
99 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4
100 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5
101 #define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E
102 #define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F
103 #define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C
104 #define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D
105 #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A
106 #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B
107 #define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C
108 #define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D
109
110 #define E1000_REVISION_4 4
111
112 #define E1000_FUNC_1 1
113
114 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
115 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
116
117 enum e1000_mac_type {
118 e1000_82571,
119 e1000_82572,
120 e1000_82573,
121 e1000_82574,
122 e1000_82583,
123 e1000_80003es2lan,
124 e1000_ich8lan,
125 e1000_ich9lan,
126 e1000_ich10lan,
127 e1000_pchlan,
128 e1000_pch2lan,
129 e1000_pch_lpt,
130 e1000_pch_spt,
131 e1000_pch_cnp,
132 e1000_pch_tgp,
133 e1000_pch_adp,
134 e1000_pch_mtp,
135 };
136
137 enum e1000_media_type {
138 e1000_media_type_unknown = 0,
139 e1000_media_type_copper = 1,
140 e1000_media_type_fiber = 2,
141 e1000_media_type_internal_serdes = 3,
142 e1000_num_media_types
143 };
144
145 enum e1000_nvm_type {
146 e1000_nvm_unknown = 0,
147 e1000_nvm_none,
148 e1000_nvm_eeprom_spi,
149 e1000_nvm_flash_hw,
150 e1000_nvm_flash_sw
151 };
152
153 enum e1000_nvm_override {
154 e1000_nvm_override_none = 0,
155 e1000_nvm_override_spi_small,
156 e1000_nvm_override_spi_large
157 };
158
159 enum e1000_phy_type {
160 e1000_phy_unknown = 0,
161 e1000_phy_none,
162 e1000_phy_m88,
163 e1000_phy_igp,
164 e1000_phy_igp_2,
165 e1000_phy_gg82563,
166 e1000_phy_igp_3,
167 e1000_phy_ife,
168 e1000_phy_bm,
169 e1000_phy_82578,
170 e1000_phy_82577,
171 e1000_phy_82579,
172 e1000_phy_i217,
173 };
174
175 enum e1000_bus_width {
176 e1000_bus_width_unknown = 0,
177 e1000_bus_width_pcie_x1,
178 e1000_bus_width_pcie_x2,
179 e1000_bus_width_pcie_x4 = 4,
180 e1000_bus_width_pcie_x8 = 8,
181 e1000_bus_width_32,
182 e1000_bus_width_64,
183 e1000_bus_width_reserved
184 };
185
186 enum e1000_1000t_rx_status {
187 e1000_1000t_rx_status_not_ok = 0,
188 e1000_1000t_rx_status_ok,
189 e1000_1000t_rx_status_undefined = 0xFF
190 };
191
192 enum e1000_rev_polarity {
193 e1000_rev_polarity_normal = 0,
194 e1000_rev_polarity_reversed,
195 e1000_rev_polarity_undefined = 0xFF
196 };
197
198 enum e1000_fc_mode {
199 e1000_fc_none = 0,
200 e1000_fc_rx_pause,
201 e1000_fc_tx_pause,
202 e1000_fc_full,
203 e1000_fc_default = 0xFF
204 };
205
206 enum e1000_ms_type {
207 e1000_ms_hw_default = 0,
208 e1000_ms_force_master,
209 e1000_ms_force_slave,
210 e1000_ms_auto
211 };
212
213 enum e1000_smart_speed {
214 e1000_smart_speed_default = 0,
215 e1000_smart_speed_on,
216 e1000_smart_speed_off
217 };
218
219 enum e1000_serdes_link_state {
220 e1000_serdes_link_down = 0,
221 e1000_serdes_link_autoneg_progress,
222 e1000_serdes_link_autoneg_complete,
223 e1000_serdes_link_forced_up
224 };
225
226 /* Receive Descriptor - Extended */
227 union e1000_rx_desc_extended {
228 struct {
229 __le64 buffer_addr;
230 __le64 reserved;
231 } read;
232 struct {
233 struct {
234 __le32 mrq; /* Multiple Rx Queues */
235 union {
236 __le32 rss; /* RSS Hash */
237 struct {
238 __le16 ip_id; /* IP id */
239 __le16 csum; /* Packet Checksum */
240 } csum_ip;
241 } hi_dword;
242 } lower;
243 struct {
244 __le32 status_error; /* ext status/error */
245 __le16 length;
246 __le16 vlan; /* VLAN tag */
247 } upper;
248 } wb; /* writeback */
249 };
250
251 #define MAX_PS_BUFFERS 4
252
253 /* Number of packet split data buffers (not including the header buffer) */
254 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
255
256 /* Receive Descriptor - Packet Split */
257 union e1000_rx_desc_packet_split {
258 struct {
259 /* one buffer for protocol header(s), three data buffers */
260 __le64 buffer_addr[MAX_PS_BUFFERS];
261 } read;
262 struct {
263 struct {
264 __le32 mrq; /* Multiple Rx Queues */
265 union {
266 __le32 rss; /* RSS Hash */
267 struct {
268 __le16 ip_id; /* IP id */
269 __le16 csum; /* Packet Checksum */
270 } csum_ip;
271 } hi_dword;
272 } lower;
273 struct {
274 __le32 status_error; /* ext status/error */
275 __le16 length0; /* length of buffer 0 */
276 __le16 vlan; /* VLAN tag */
277 } middle;
278 struct {
279 __le16 header_status;
280 /* length of buffers 1-3 */
281 __le16 length[PS_PAGE_BUFFERS];
282 } upper;
283 __le64 reserved;
284 } wb; /* writeback */
285 };
286
287 /* Transmit Descriptor */
288 struct e1000_tx_desc {
289 __le64 buffer_addr; /* Address of the descriptor's data buffer */
290 union {
291 __le32 data;
292 struct {
293 __le16 length; /* Data buffer length */
294 u8 cso; /* Checksum offset */
295 u8 cmd; /* Descriptor control */
296 } flags;
297 } lower;
298 union {
299 __le32 data;
300 struct {
301 u8 status; /* Descriptor status */
302 u8 css; /* Checksum start */
303 __le16 special;
304 } fields;
305 } upper;
306 };
307
308 /* Offload Context Descriptor */
309 struct e1000_context_desc {
310 union {
311 __le32 ip_config;
312 struct {
313 u8 ipcss; /* IP checksum start */
314 u8 ipcso; /* IP checksum offset */
315 __le16 ipcse; /* IP checksum end */
316 } ip_fields;
317 } lower_setup;
318 union {
319 __le32 tcp_config;
320 struct {
321 u8 tucss; /* TCP checksum start */
322 u8 tucso; /* TCP checksum offset */
323 __le16 tucse; /* TCP checksum end */
324 } tcp_fields;
325 } upper_setup;
326 __le32 cmd_and_length;
327 union {
328 __le32 data;
329 struct {
330 u8 status; /* Descriptor status */
331 u8 hdr_len; /* Header length */
332 __le16 mss; /* Maximum segment size */
333 } fields;
334 } tcp_seg_setup;
335 };
336
337 /* Offload data descriptor */
338 struct e1000_data_desc {
339 __le64 buffer_addr; /* Address of the descriptor's buffer address */
340 union {
341 __le32 data;
342 struct {
343 __le16 length; /* Data buffer length */
344 u8 typ_len_ext;
345 u8 cmd;
346 } flags;
347 } lower;
348 union {
349 __le32 data;
350 struct {
351 u8 status; /* Descriptor status */
352 u8 popts; /* Packet Options */
353 __le16 special;
354 } fields;
355 } upper;
356 };
357
358 /* Statistics counters collected by the MAC */
359 struct e1000_hw_stats {
360 u64 crcerrs;
361 u64 algnerrc;
362 u64 symerrs;
363 u64 rxerrc;
364 u64 mpc;
365 u64 scc;
366 u64 ecol;
367 u64 mcc;
368 u64 latecol;
369 u64 colc;
370 u64 dc;
371 u64 tncrs;
372 u64 sec;
373 u64 cexterr;
374 u64 rlec;
375 u64 xonrxc;
376 u64 xontxc;
377 u64 xoffrxc;
378 u64 xofftxc;
379 u64 fcruc;
380 u64 prc64;
381 u64 prc127;
382 u64 prc255;
383 u64 prc511;
384 u64 prc1023;
385 u64 prc1522;
386 u64 gprc;
387 u64 bprc;
388 u64 mprc;
389 u64 gptc;
390 u64 gorc;
391 u64 gotc;
392 u64 rnbc;
393 u64 ruc;
394 u64 rfc;
395 u64 roc;
396 u64 rjc;
397 u64 mgprc;
398 u64 mgpdc;
399 u64 mgptc;
400 u64 tor;
401 u64 tot;
402 u64 tpr;
403 u64 tpt;
404 u64 ptc64;
405 u64 ptc127;
406 u64 ptc255;
407 u64 ptc511;
408 u64 ptc1023;
409 u64 ptc1522;
410 u64 mptc;
411 u64 bptc;
412 u64 tsctc;
413 u64 tsctfc;
414 u64 iac;
415 u64 icrxptc;
416 u64 icrxatc;
417 u64 ictxptc;
418 u64 ictxatc;
419 u64 ictxqec;
420 u64 ictxqmtc;
421 u64 icrxdmtc;
422 u64 icrxoc;
423 };
424
425 struct e1000_phy_stats {
426 u32 idle_errors;
427 u32 receive_errors;
428 };
429
430 struct e1000_host_mng_dhcp_cookie {
431 u32 signature;
432 u8 status;
433 u8 reserved0;
434 u16 vlan_id;
435 u32 reserved1;
436 u16 reserved2;
437 u8 reserved3;
438 u8 checksum;
439 };
440
441 /* Host Interface "Rev 1" */
442 struct e1000_host_command_header {
443 u8 command_id;
444 u8 command_length;
445 u8 command_options;
446 u8 checksum;
447 };
448
449 #define E1000_HI_MAX_DATA_LENGTH 252
450 struct e1000_host_command_info {
451 struct e1000_host_command_header command_header;
452 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
453 };
454
455 /* Host Interface "Rev 2" */
456 struct e1000_host_mng_command_header {
457 u8 command_id;
458 u8 checksum;
459 u16 reserved1;
460 u16 reserved2;
461 u16 command_length;
462 };
463
464 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
465 struct e1000_host_mng_command_info {
466 struct e1000_host_mng_command_header command_header;
467 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
468 };
469
470 #include "mac.h"
471 #include "phy.h"
472 #include "nvm.h"
473 #include "manage.h"
474
475 /* Function pointers for the MAC. */
476 struct e1000_mac_operations {
477 s32 (*id_led_init)(struct e1000_hw *);
478 s32 (*blink_led)(struct e1000_hw *);
479 bool (*check_mng_mode)(struct e1000_hw *);
480 s32 (*check_for_link)(struct e1000_hw *);
481 s32 (*cleanup_led)(struct e1000_hw *);
482 void (*clear_hw_cntrs)(struct e1000_hw *);
483 void (*clear_vfta)(struct e1000_hw *);
484 s32 (*get_bus_info)(struct e1000_hw *);
485 void (*set_lan_id)(struct e1000_hw *);
486 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
487 s32 (*led_on)(struct e1000_hw *);
488 s32 (*led_off)(struct e1000_hw *);
489 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
490 s32 (*reset_hw)(struct e1000_hw *);
491 s32 (*init_hw)(struct e1000_hw *);
492 s32 (*setup_link)(struct e1000_hw *);
493 s32 (*setup_physical_interface)(struct e1000_hw *);
494 s32 (*setup_led)(struct e1000_hw *);
495 void (*write_vfta)(struct e1000_hw *, u32, u32);
496 void (*config_collision_dist)(struct e1000_hw *);
497 int (*rar_set)(struct e1000_hw *, u8 *, u32);
498 s32 (*read_mac_addr)(struct e1000_hw *);
499 u32 (*rar_get_count)(struct e1000_hw *);
500 };
501
502 /* When to use various PHY register access functions:
503 *
504 * Func Caller
505 * Function Does Does When to use
506 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
507 * X_reg L,P,A n/a for simple PHY reg accesses
508 * X_reg_locked P,A L for multiple accesses of different regs
509 * on different pages
510 * X_reg_page A L,P for multiple accesses of different regs
511 * on the same page
512 *
513 * Where X=[read|write], L=locking, P=sets page, A=register access
514 *
515 */
516 struct e1000_phy_operations {
517 s32 (*acquire)(struct e1000_hw *);
518 s32 (*cfg_on_link_up)(struct e1000_hw *);
519 s32 (*check_polarity)(struct e1000_hw *);
520 s32 (*check_reset_block)(struct e1000_hw *);
521 s32 (*commit)(struct e1000_hw *);
522 s32 (*force_speed_duplex)(struct e1000_hw *);
523 s32 (*get_cfg_done)(struct e1000_hw *hw);
524 s32 (*get_cable_length)(struct e1000_hw *);
525 s32 (*get_info)(struct e1000_hw *);
526 s32 (*set_page)(struct e1000_hw *, u16);
527 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
528 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
529 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *);
530 void (*release)(struct e1000_hw *);
531 s32 (*reset)(struct e1000_hw *);
532 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
533 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
534 s32 (*write_reg)(struct e1000_hw *, u32, u16);
535 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
536 s32 (*write_reg_page)(struct e1000_hw *, u32, u16);
537 void (*power_up)(struct e1000_hw *);
538 void (*power_down)(struct e1000_hw *);
539 };
540
541 /* Function pointers for the NVM. */
542 struct e1000_nvm_operations {
543 s32 (*acquire)(struct e1000_hw *);
544 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
545 void (*release)(struct e1000_hw *);
546 void (*reload)(struct e1000_hw *);
547 s32 (*update)(struct e1000_hw *);
548 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
549 s32 (*validate)(struct e1000_hw *);
550 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
551 };
552
553 struct e1000_mac_info {
554 struct e1000_mac_operations ops;
555 u8 addr[ETH_ALEN];
556 u8 perm_addr[ETH_ALEN];
557
558 enum e1000_mac_type type;
559
560 u32 collision_delta;
561 u32 ledctl_default;
562 u32 ledctl_mode1;
563 u32 ledctl_mode2;
564 u32 mc_filter_type;
565 u32 tx_packet_delta;
566 u32 txcw;
567
568 u16 current_ifs_val;
569 u16 ifs_max_val;
570 u16 ifs_min_val;
571 u16 ifs_ratio;
572 u16 ifs_step_size;
573 u16 mta_reg_count;
574
575 /* Maximum size of the MTA register table in all supported adapters */
576 #define MAX_MTA_REG 128
577 u32 mta_shadow[MAX_MTA_REG];
578 u16 rar_entry_count;
579
580 u8 forced_speed_duplex;
581
582 bool adaptive_ifs;
583 bool has_fwsm;
584 bool arc_subsystem_valid;
585 bool autoneg;
586 bool autoneg_failed;
587 bool get_link_status;
588 bool in_ifs_mode;
589 bool serdes_has_link;
590 bool tx_pkt_filtering;
591 enum e1000_serdes_link_state serdes_link_state;
592 };
593
594 struct e1000_phy_info {
595 struct e1000_phy_operations ops;
596
597 enum e1000_phy_type type;
598
599 enum e1000_1000t_rx_status local_rx;
600 enum e1000_1000t_rx_status remote_rx;
601 enum e1000_ms_type ms_type;
602 enum e1000_ms_type original_ms_type;
603 enum e1000_rev_polarity cable_polarity;
604 enum e1000_smart_speed smart_speed;
605
606 u32 addr;
607 u32 id;
608 u32 reset_delay_us; /* in usec */
609 u32 revision;
610
611 enum e1000_media_type media_type;
612
613 u16 autoneg_advertised;
614 u16 autoneg_mask;
615 u16 cable_length;
616 u16 max_cable_length;
617 u16 min_cable_length;
618
619 u8 mdix;
620
621 bool disable_polarity_correction;
622 bool is_mdix;
623 bool polarity_correction;
624 bool speed_downgraded;
625 bool autoneg_wait_to_complete;
626 };
627
628 struct e1000_nvm_info {
629 struct e1000_nvm_operations ops;
630
631 enum e1000_nvm_type type;
632 enum e1000_nvm_override override;
633
634 u32 flash_bank_size;
635 u32 flash_base_addr;
636
637 u16 word_size;
638 u16 delay_usec;
639 u16 address_bits;
640 u16 opcode_bits;
641 u16 page_size;
642 };
643
644 struct e1000_bus_info {
645 enum e1000_bus_width width;
646
647 u16 func;
648 };
649
650 struct e1000_fc_info {
651 u32 high_water; /* Flow control high-water mark */
652 u32 low_water; /* Flow control low-water mark */
653 u16 pause_time; /* Flow control pause timer */
654 u16 refresh_time; /* Flow control refresh timer */
655 bool send_xon; /* Flow control send XON */
656 bool strict_ieee; /* Strict IEEE mode */
657 enum e1000_fc_mode current_mode; /* FC mode in effect */
658 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
659 };
660
661 struct e1000_dev_spec_82571 {
662 bool laa_is_present;
663 u32 smb_counter;
664 };
665
666 struct e1000_dev_spec_80003es2lan {
667 bool mdic_wa_enable;
668 };
669
670 struct e1000_shadow_ram {
671 u16 value;
672 bool modified;
673 };
674
675 #define E1000_ICH8_SHADOW_RAM_WORDS 2048
676
677 /* I218 PHY Ultra Low Power (ULP) states */
678 enum e1000_ulp_state {
679 e1000_ulp_state_unknown,
680 e1000_ulp_state_off,
681 e1000_ulp_state_on,
682 };
683
684 struct e1000_dev_spec_ich8lan {
685 bool kmrn_lock_loss_workaround_enabled;
686 struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
687 bool nvm_k1_enabled;
688 bool eee_disable;
689 u16 eee_lp_ability;
690 enum e1000_ulp_state ulp_state;
691 };
692
693 struct e1000_hw {
694 struct e1000_adapter *adapter;
695
696 void __iomem *hw_addr;
697 void __iomem *flash_address;
698
699 struct e1000_mac_info mac;
700 struct e1000_fc_info fc;
701 struct e1000_phy_info phy;
702 struct e1000_nvm_info nvm;
703 struct e1000_bus_info bus;
704 struct e1000_host_mng_dhcp_cookie mng_cookie;
705
706 union {
707 struct e1000_dev_spec_82571 e82571;
708 struct e1000_dev_spec_80003es2lan e80003es2lan;
709 struct e1000_dev_spec_ich8lan ich8lan;
710 } dev_spec;
711 };
712
713 #include "82571.h"
714 #include "80003es2lan.h"
715 #include "ich8lan.h"
716
717 #endif
Linux with added FPC-III support