| blob | e9b82c209c2df60534a2eef83fe5d8e230846554 |
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/delay.h>
13 #include <linux/netdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/tcp.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/cpu.h>
23 #include <linux/smp.h>
24 #include <linux/pm_qos.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/aer.h>
27 #include <linux/prefetch.h>
33 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
53 };
56 u32 ofs;
58 };
61 /* General Registers */
66 /* Interrupt Registers */
69 /* Rx Registers */
85 /* Tx Registers */
102 /* List Terminator */
104 };
106 /**
107 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
108 * @hw: pointer to the HW structure
109 *
110 * When updating the MAC CSR registers, the Manageability Engine (ME) could
111 * be accessing the registers at the same time. Normally, this is handled in
112 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
113 * accesses later than it should which could result in the register to have
114 * an incorrect value. Workaround this by checking the FWSM register which
115 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
116 * and try again a number of times.
117 **/
119 {
124 }
127 {
132 }
134 /**
135 * e1000_regdump - register printout routine
136 * @hw: pointer to the HW structure
137 * @reginfo: pointer to the register info table
138 **/
140 {
162 }
166 }
170 {
182 }
183 }
184 }
186 /**
187 * e1000e_dump - Print registers, Tx-ring and Rx-ring
188 * @adapter: board private structure
189 **/
191 {
198 __le64 a;
199 __le64 b;
206 __le64 a;
207 __le64 b;
208 __le64 c;
209 __le64 d;
211 u32 staterr;
217 /* Print netdevice Info */
223 }
225 /* Print Registers */
231 }
233 /* Print Tx Ring Summary */
247 /* Print Tx Ring */
253 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
254 *
255 * Legacy Transmit Descriptor
256 * +--------------------------------------------------------------+
257 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
258 * +--------------------------------------------------------------+
259 * 8 | Special | CSS | Status | CMD | CSO | Length |
260 * +--------------------------------------------------------------+
261 * 63 48 47 36 35 32 31 24 23 16 15 0
262 *
263 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
264 * 63 48 47 40 39 32 31 16 15 8 7 0
265 * +----------------------------------------------------------------+
266 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
267 * +----------------------------------------------------------------+
268 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
269 * +----------------------------------------------------------------+
270 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
271 *
272 * Extended Data Descriptor (DTYP=0x1)
273 * +----------------------------------------------------------------+
274 * 0 | Buffer Address [63:0] |
275 * +----------------------------------------------------------------+
276 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
277 * +----------------------------------------------------------------+
278 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
279 */
280 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
281 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
282 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
294 else
299 i,
311 }
313 /* Print Rx Ring Summary */
314 rx_ring_summary:
320 /* Print Rx Ring */
329 /* [Extended] Packet Split Receive Descriptor Format
330 *
331 * +-----------------------------------------------------+
332 * 0 | Buffer Address 0 [63:0] |
333 * +-----------------------------------------------------+
334 * 8 | Buffer Address 1 [63:0] |
335 * +-----------------------------------------------------+
336 * 16 | Buffer Address 2 [63:0] |
337 * +-----------------------------------------------------+
338 * 24 | Buffer Address 3 [63:0] |
339 * +-----------------------------------------------------+
340 */
341 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
342 /* [Extended] Receive Descriptor (Write-Back) Format
343 *
344 * 63 48 47 32 31 13 12 8 7 4 3 0
345 * +------------------------------------------------------+
346 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
347 * | Checksum | Ident | | Queue | | Type |
348 * +------------------------------------------------------+
349 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
350 * +------------------------------------------------------+
351 * 63 48 47 32 31 20 19 0
352 */
353 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
359 staterr =
366 else
370 /* Descriptor Done */
390 buffer_info);
391 }
392 }
396 /* Extended Receive Descriptor (Read) Format
397 *
398 * +-----------------------------------------------------+
399 * 0 | Buffer Address [63:0] |
400 * +-----------------------------------------------------+
401 * 8 | Reserved |
402 * +-----------------------------------------------------+
403 */
404 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
405 /* Extended Receive Descriptor (Write-Back) Format
406 *
407 * 63 48 47 32 31 24 23 4 3 0
408 * +------------------------------------------------------+
409 * | RSS Hash | | | |
410 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
411 * | Packet | IP | | | Type |
412 * | Checksum | Ident | | | |
413 * +------------------------------------------------------+
414 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
415 * +------------------------------------------------------+
416 * 63 48 47 32 31 20 19 0
417 */
432 else
436 /* Descriptor Done */
458 }
459 }
460 }
461 }
463 /**
464 * e1000_desc_unused - calculate if we have unused descriptors
465 * @ring: pointer to ring struct to perform calculation on
466 **/
468 {
473 }
475 /**
476 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
477 * @adapter: board private structure
478 * @hwtstamps: time stamp structure to update
479 * @systim: unsigned 64bit system time value.
480 *
481 * Convert the system time value stored in the RX/TXSTMP registers into a
482 * hwtstamp which can be used by the upper level time stamping functions.
483 *
484 * The 'systim_lock' spinlock is used to protect the consistency of the
485 * system time value. This is needed because reading the 64 bit time
486 * value involves reading two 32 bit registers. The first read latches the
487 * value.
488 **/
491 u64 systim)
492 {
493 u64 ns;
502 }
504 /**
505 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
506 * @adapter: board private structure
507 * @status: descriptor extended error and status field
508 * @skb: particular skb to include time stamp
509 *
510 * If the time stamp is valid, convert it into the timecounter ns value
511 * and store that result into the shhwtstamps structure which is passed
512 * up the network stack.
513 **/
516 {
518 u64 rxstmp;
525 /* The Rx time stamp registers contain the time stamp. No other
526 * received packet will be time stamped until the Rx time stamp
527 * registers are read. Because only one packet can be time stamped
528 * at a time, the register values must belong to this packet and
529 * therefore none of the other additional attributes need to be
530 * compared.
531 */
537 }
539 /**
540 * e1000_receive_skb - helper function to handle Rx indications
541 * @adapter: board private structure
542 * @netdev: pointer to netdev struct
543 * @staterr: descriptor extended error and status field as written by hardware
544 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
545 * @skb: pointer to sk_buff to be indicated to stack
546 **/
550 {
561 }
563 /**
564 * e1000_rx_checksum - Receive Checksum Offload
565 * @adapter: board private structure
566 * @status_err: receive descriptor status and error fields
567 * @skb: socket buffer with received data
568 **/
571 {
577 /* Rx checksum disabled */
581 /* Ignore Checksum bit is set */
585 /* TCP/UDP checksum error bit or IP checksum error bit is set */
587 /* let the stack verify checksum errors */
590 }
592 /* TCP/UDP Checksum has not been calculated */
596 /* It must be a TCP or UDP packet with a valid checksum */
599 }
602 {
615 }
616 }
619 {
632 }
633 }
635 /**
636 * e1000_alloc_rx_buffers - Replace used receive buffers
637 * @rx_ring: Rx descriptor ring
638 * @cleaned_count: number to reallocate
639 * @gfp: flags for allocation
640 **/
643 {
661 }
665 /* Better luck next round */
668 }
671 map_skb:
674 DMA_FROM_DEVICE);
679 }
685 /* Force memory writes to complete before letting h/w
686 * know there are new descriptors to fetch. (Only
687 * applicable for weak-ordered memory model archs,
688 * such as IA-64).
689 */
693 else
695 }
696 i++;
700 }
703 }
705 /**
706 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
707 * @rx_ring: Rx descriptor ring
708 * @cleaned_count: number to reallocate
709 * @gfp: flags for allocation
710 **/
713 {
732 /* all unused desc entries get hw null ptr */
736 }
742 }
746 DMA_FROM_DEVICE);
753 }
754 }
755 /* Refresh the desc even if buffer_addrs
756 * didn't change because each write-back
757 * erases this info.
758 */
761 }
764 gfp);
769 }
774 DMA_FROM_DEVICE);
778 /* cleanup skb */
782 }
787 /* Force memory writes to complete before letting h/w
788 * know there are new descriptors to fetch. (Only
789 * applicable for weak-ordered memory model archs,
790 * such as IA-64).
791 */
795 else
797 }
799 i++;
803 }
805 no_buffers:
807 }
809 /**
810 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
811 * @rx_ring: Rx descriptor ring
812 * @cleaned_count: number of buffers to allocate this pass
813 * @gfp: flags for allocation
814 **/
818 {
836 }
840 /* Better luck next round */
843 }
846 check_page:
847 /* allocate a new page if necessary */
853 }
854 }
859 PAGE_SIZE,
860 DMA_FROM_DEVICE);
864 }
865 }
873 }
880 /* Force memory writes to complete before letting h/w
881 * know there are new descriptors to fetch. (Only
882 * applicable for weak-ordered memory model archs,
883 * such as IA-64).
884 */
888 else
890 }
891 }
895 {
898 }
900 /**
901 * e1000_clean_rx_irq - Send received data up the network stack
902 * @rx_ring: Rx descriptor ring
903 * @work_done: output parameter for indicating completed work
904 * @work_to_do: how many packets we can clean
905 *
906 * the return value indicates whether actual cleaning was done, there
907 * is no guarantee that everything was cleaned
908 **/
911 {
942 i++;
951 cleaned_count++;
958 /* !EOP means multiple descriptors were used to store a single
959 * packet, if that's the case we need to toss it. In fact, we
960 * need to toss every packet with the EOP bit clear and the
961 * next frame that _does_ have the EOP bit set, as it is by
962 * definition only a frame fragment
963 */
968 /* All receives must fit into a single buffer */
970 /* recycle */
975 }
979 /* recycle */
982 }
984 /* adjust length to remove Ethernet CRC */
986 /* If configured to store CRC, don't subtract FCS,
987 * but keep the FCS bytes out of the total_rx_bytes
988 * counter
989 */
992 else
994 }
997 total_rx_packets++;
999 /* code added for copybreak, this should improve
1000 * performance for small packets with large amounts
1001 * of reassembly being done in the stack
1002 */
1010 NET_IP_ALIGN),
1012 NET_IP_ALIGN));
1013 /* save the skb in buffer_info as good */
1016 }
1017 /* else just continue with the old one */
1018 }
1019 /* end copybreak code */
1022 /* Receive Checksum Offload */
1030 next_desc:
1033 /* return some buffers to hardware, one at a time is too slow */
1036 GFP_ATOMIC);
1038 }
1040 /* use prefetched values */
1045 }
1055 }
1060 {
1067 else
1071 }
1075 else
1078 }
1080 }
1083 {
1086 print_hang_task);
1094 u16 pci_status;
1100 /* May be block on write-back, flush and detect again
1101 * flush pending descriptor writebacks to memory
1102 */
1104 /* execute the writes immediately */
1106 /* Due to rare timing issues, write to TIDV again to ensure
1107 * the write is successful
1108 */
1110 /* execute the writes immediately */
1114 }
1120 }
1122 /* Real hang detected */
1131 /* detected Hardware unit hang */
1154 /* Suggest workaround for known h/w issue */
1157 }
1159 /**
1160 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1161 * @work: pointer to work struct
1162 *
1163 * This work function polls the TSYNCTXCTL valid bit to determine when a
1164 * timestamp has been taken for the current stored skb. The timestamp must
1165 * be for this skb because only one such packet is allowed in the queue.
1166 */
1168 {
1170 tx_hwtstamp_work);
1176 u64 txstmp;
1183 /* Clear the global tx_hwtstamp_skb pointer and force writes
1184 * prior to notifying the stack of a Tx timestamp.
1185 */
1198 /* reschedule to check later */
1200 }
1201 }
1203 /**
1204 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1205 * @tx_ring: Tx descriptor ring
1206 *
1207 * the return value indicates whether actual cleaning was done, there
1208 * is no guarantee that everything was cleaned
1209 **/
1211 {
1241 pkts_compl++;
1242 }
1243 }
1248 i++;
1251 }
1257 }
1263 #define TX_WAKE_THRESHOLD 32
1266 /* Make sure that anybody stopping the queue after this
1267 * sees the new next_to_clean.
1268 */
1275 }
1276 }
1279 /* Detect a transmit hang in hardware, this serializes the
1280 * check with the clearing of time_stamp and movement of i
1281 */
1288 else
1290 }
1294 }
1296 /**
1297 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1298 * @rx_ring: Rx descriptor ring
1299 * @work_done: output parameter for indicating completed work
1300 * @work_to_do: how many packets we can clean
1301 *
1302 * the return value indicates whether actual cleaning was done, there
1303 * is no guarantee that everything was cleaned
1304 **/
1307 {
1334 /* in the packet split case this is header only */
1337 i++;
1346 cleaned_count++;
1351 /* see !EOP comment in other Rx routine */
1361 }
1367 }
1375 }
1377 /* Good Receive */
1380 {
1381 /* this looks ugly, but it seems compiler issues make
1382 * it more efficient than reusing j
1383 */
1386 /* page alloc/put takes too long and effects small
1387 * packet throughput, so unsplit small packets and
1388 * save the alloc/put only valid in softirq (napi)
1389 * context to call kmap_*
1390 */
1397 /* there is no documentation about how to call
1398 * kmap_atomic, so we can't hold the mapping
1399 * very long
1400 */
1403 PAGE_SIZE,
1404 DMA_FROM_DEVICE);
1410 PAGE_SIZE,
1411 DMA_FROM_DEVICE);
1413 /* remove the CRC */
1417 }
1422 }
1431 DMA_FROM_DEVICE);
1438 }
1440 /* strip the ethernet crc, problem is we're using pages now so
1441 * this whole operation can get a little cpu intensive
1442 */
1446 }
1448 copydone:
1450 total_rx_packets++;
1463 next_desc:
1467 /* return some buffers to hardware, one at a time is too slow */
1470 GFP_ATOMIC);
1472 }
1474 /* use prefetched values */
1479 }
1489 }
1492 u16 length)
1493 {
1498 }
1500 /**
1501 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1502 * @rx_ring: Rx descriptor ring
1503 * @work_done: output parameter for indicating completed work
1504 * @work_to_do: how many packets we can clean
1505 *
1506 * the return value indicates whether actual cleaning was done, there
1507 * is no guarantee that everything was cleaned
1508 **/
1511 {
1549 cleaned_count++;
1551 DMA_FROM_DEVICE);
1556 /* errors is only valid for DD + EOP descriptors */
1560 /* recycle both page and skb */
1562 /* an error means any chain goes out the window too */
1567 }
1568 #define rxtop (rx_ring->rx_skb_top)
1570 /* this descriptor is only the beginning (or middle) */
1572 /* this is the beginning of a chain */
1577 /* this is the middle of a chain */
1581 length);
1582 /* re-use the skb, only consumed the page */
1584 }
1589 /* end of the chain */
1593 length);
1594 /* re-use the current skb, we only consumed the
1595 * page
1596 */
1602 /* no chain, got EOP, this buf is the packet
1603 * copybreak to save the put_page/alloc_page
1604 */
1610 length);
1612 /* re-use the page, so don't erase
1613 * buffer_info->page
1614 */
1619 length);
1621 length);
1622 }
1623 }
1624 }
1626 /* Receive Checksum Offload */
1631 /* probably a little skewed due to removing CRC */
1633 total_rx_packets++;
1635 /* eth type trans needs skb->data to point to something */
1640 }
1645 next_desc:
1648 /* return some buffers to hardware, one at a time is too slow */
1651 GFP_ATOMIC);
1653 }
1655 /* use prefetched values */
1660 }
1670 }
1672 /**
1673 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1674 * @rx_ring: Rx descriptor ring
1675 **/
1677 {
1684 /* Free all the Rx ring sk_buffs */
1691 DMA_FROM_DEVICE);
1698 DMA_FROM_DEVICE);
1700 }
1705 }
1710 }
1717 DMA_FROM_DEVICE);
1721 }
1722 }
1724 /* there also may be some cached data from a chained receive */
1728 }
1730 /* Zero out the descriptor ring */
1736 }
1739 {
1742 downshift_task);
1748 }
1750 /**
1751 * e1000_intr_msi - Interrupt Handler
1752 * @irq: interrupt number
1753 * @data: pointer to a network interface device structure
1754 **/
1756 {
1762 /* read ICR disables interrupts using IAM */
1765 /* ICH8 workaround-- Call gig speed drop workaround on cable
1766 * disconnect (LSC) before accessing any PHY registers
1767 */
1772 /* 80003ES2LAN workaround-- For packet buffer work-around on
1773 * link down event; disable receives here in the ISR and reset
1774 * adapter in watchdog
1775 */
1778 /* disable receives */
1783 }
1784 /* guard against interrupt when we're going down */
1787 }
1789 /* Reset on uncorrectable ECC error */
1797 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1799 /* Do the reset outside of interrupt context */
1802 /* return immediately since reset is imminent */
1804 }
1812 }
1815 }
1817 /**
1818 * e1000_intr - Interrupt Handler
1819 * @irq: interrupt number
1820 * @data: pointer to a network interface device structure
1821 **/
1823 {
1832 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1833 * not set, then the adapter didn't send an interrupt
1834 */
1838 /* Interrupt Auto-Mask...upon reading ICR,
1839 * interrupts are masked. No need for the
1840 * IMC write
1841 */
1845 /* ICH8 workaround-- Call gig speed drop workaround on cable
1846 * disconnect (LSC) before accessing any PHY registers
1847 */
1852 /* 80003ES2LAN workaround--
1853 * For packet buffer work-around on link down event;
1854 * disable receives here in the ISR and
1855 * reset adapter in watchdog
1856 */
1859 /* disable receives */
1863 }
1864 /* guard against interrupt when we're going down */
1867 }
1869 /* Reset on uncorrectable ECC error */
1877 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1879 /* Do the reset outside of interrupt context */
1882 /* return immediately since reset is imminent */
1884 }
1892 }
1895 }
1898 {
1909 /* guard against interrupt when we're going down */
1912 }
1918 }
1921 {
1931 /* Ring was not completely cleaned, so fire another interrupt */
1938 }
1941 {
1946 /* Write the ITR value calculated at the end of the
1947 * previous interrupt.
1948 */
1955 }
1961 }
1963 }
1965 /**
1966 * e1000_configure_msix - Configure MSI-X hardware
1967 * @adapter: board private structure
1968 *
1969 * e1000_configure_msix sets up the hardware to properly
1970 * generate MSI-X interrupts.
1971 **/
1973 {
1982 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1988 }
1990 /* Configure Rx vector */
1996 else
2000 /* Configure Tx vector */
2002 vector++;
2006 else
2011 /* set vector for Other Causes, e.g. link changes */
2012 vector++;
2017 else
2020 /* Cause Tx interrupts on every write back */
2025 /* enable MSI-X PBA support */
2030 }
2033 {
2041 }
2042 }
2044 /**
2045 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2046 * @adapter: board private structure
2047 *
2048 * Attempt to configure interrupts using the best available
2049 * capabilities of the hardware and kernel.
2050 **/
2052 {
2062 msix_entry),
2063 GFP_KERNEL);
2076 }
2077 /* MSI-X failed, so fall through and try MSI */
2080 }
2082 fallthrough;
2089 }
2090 fallthrough;
2092 /* Don't do anything; this is the system default */
2094 }
2096 /* store the number of vectors being used */
2098 }
2100 /**
2101 * e1000_request_msix - Initialize MSI-X interrupts
2102 * @adapter: board private structure
2103 *
2104 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2105 * kernel.
2106 **/
2108 {
2116 else
2120 netdev);
2126 vector++;
2132 else
2136 netdev);
2142 vector++;
2152 }
2154 /**
2155 * e1000_request_irq - initialize interrupts
2156 * @adapter: board private structure
2157 *
2158 * Attempts to configure interrupts using the best available
2159 * capabilities of the hardware and kernel.
2160 **/
2162 {
2170 /* fall back to MSI */
2174 }
2181 /* fall back to legacy interrupt */
2184 }
2192 }
2195 {
2202 vector++;
2205 vector++;
2207 /* Other Causes interrupt vector */
2210 }
2213 }
2215 /**
2216 * e1000_irq_disable - Mask off interrupt generation on the NIC
2217 * @adapter: board private structure
2218 **/
2220 {
2235 }
2236 }
2238 /**
2239 * e1000_irq_enable - Enable default interrupt generation settings
2240 * @adapter: board private structure
2241 **/
2243 {
2249 IMS_OTHER_MASK);
2254 }
2256 }
2258 /**
2259 * e1000e_get_hw_control - get control of the h/w from f/w
2260 * @adapter: address of board private structure
2261 *
2262 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2263 * For ASF and Pass Through versions of f/w this means that
2264 * the driver is loaded. For AMT version (only with 82573)
2265 * of the f/w this means that the network i/f is open.
2266 **/
2268 {
2270 u32 ctrl_ext;
2271 u32 swsm;
2273 /* Let firmware know the driver has taken over */
2280 }
2281 }
2283 /**
2284 * e1000e_release_hw_control - release control of the h/w to f/w
2285 * @adapter: address of board private structure
2286 *
2287 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2288 * For ASF and Pass Through versions of f/w this means that the
2289 * driver is no longer loaded. For AMT version (only with 82573) i
2290 * of the f/w this means that the network i/f is closed.
2291 *
2292 **/
2294 {
2296 u32 ctrl_ext;
2297 u32 swsm;
2299 /* Let firmware taken over control of h/w */
2306 }
2307 }
2309 /**
2310 * e1000_alloc_ring_dma - allocate memory for a ring structure
2311 * @adapter: board private structure
2312 * @ring: ring struct for which to allocate dma
2313 **/
2316 {
2320 GFP_KERNEL);
2325 }
2327 /**
2328 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2329 * @tx_ring: Tx descriptor ring
2330 *
2331 * Return 0 on success, negative on failure
2332 **/
2334 {
2343 /* round up to nearest 4K */
2355 err:
2359 }
2361 /**
2362 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2363 * @rx_ring: Rx descriptor ring
2364 *
2365 * Returns 0 on success, negative on failure
2366 **/
2368 {
2382 GFP_KERNEL);
2385 }
2389 /* Round up to nearest 4K */
2403 err_pages:
2407 }
2408 err:
2412 }
2414 /**
2415 * e1000_clean_tx_ring - Free Tx Buffers
2416 * @tx_ring: Tx descriptor ring
2417 **/
2419 {
2428 }
2438 }
2440 /**
2441 * e1000e_free_tx_resources - Free Tx Resources per Queue
2442 * @tx_ring: Tx descriptor ring
2443 *
2444 * Free all transmit software resources
2445 **/
2447 {
2459 }
2461 /**
2462 * e1000e_free_rx_resources - Free Rx Resources
2463 * @rx_ring: Rx descriptor ring
2464 *
2465 * Free all receive software resources
2466 **/
2468 {
2484 }
2486 /**
2487 * e1000_update_itr - update the dynamic ITR value based on statistics
2488 * @itr_setting: current adapter->itr
2489 * @packets: the number of packets during this measurement interval
2490 * @bytes: the number of bytes during this measurement interval
2491 *
2492 * Stores a new ITR value based on packets and byte
2493 * counts during the last interrupt. The advantage of per interrupt
2494 * computation is faster updates and more accurate ITR for the current
2495 * traffic pattern. Constants in this function were computed
2496 * based on theoretical maximum wire speed and thresholds were set based
2497 * on testing data as well as attempting to minimize response time
2498 * while increasing bulk throughput. This functionality is controlled
2499 * by the InterruptThrottleRate module parameter.
2500 **/
2502 {
2510 /* handle TSO and jumbo frames */
2518 /* this if handles the TSO accounting */
2529 }
2537 }
2539 }
2542 }
2545 {
2546 u16 current_itr;
2549 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2554 }
2559 }
2564 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2571 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2577 /* counts and packets in update_itr are dependent on these numbers */
2590 }
2592 set_itr_now:
2594 /* this attempts to bias the interrupt rate towards Bulk
2595 * by adding intermediate steps when interrupt rate is
2596 * increasing
2597 */
2604 else
2606 }
2607 }
2609 /**
2610 * e1000e_write_itr - write the ITR value to the appropriate registers
2611 * @adapter: address of board private structure
2612 * @itr: new ITR value to program
2613 *
2614 * e1000e_write_itr determines if the adapter is in MSI-X mode
2615 * and, if so, writes the EITR registers with the ITR value.
2616 * Otherwise, it writes the ITR value into the ITR register.
2617 **/
2619 {
2630 }
2631 }
2633 /**
2634 * e1000_alloc_queues - Allocate memory for all rings
2635 * @adapter: board private structure to initialize
2636 **/
2638 {
2654 err:
2659 }
2661 /**
2662 * e1000e_poll - NAPI Rx polling callback
2663 * @napi: struct associated with this polling callback
2664 * @budget: number of packets driver is allowed to process this poll
2665 **/
2667 {
2669 napi);
2685 /* Exit the polling mode, but don't re-enable interrupts if stack might
2686 * poll us due to busy-polling
2687 */
2694 else
2696 }
2697 }
2700 }
2704 {
2709 /* don't update vlan cookie if already programmed */
2711 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2715 /* add VID to filter table */
2721 }
2726 }
2730 {
2736 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2738 /* release control to f/w */
2741 }
2743 /* remove VID from filter table */
2749 }
2754 }
2756 /**
2757 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2758 * @adapter: board private structure to initialize
2759 **/
2761 {
2764 u32 rctl;
2767 /* disable VLAN receive filtering */
2776 }
2777 }
2778 }
2780 /**
2781 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2782 * @adapter: board private structure to initialize
2783 **/
2785 {
2787 u32 rctl;
2790 /* enable VLAN receive filtering */
2795 }
2796 }
2798 /**
2799 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2800 * @adapter: board private structure to initialize
2801 **/
2803 {
2805 u32 ctrl;
2807 /* disable VLAN tag insert/strip */
2811 }
2813 /**
2814 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2815 * @adapter: board private structure to initialize
2816 **/
2818 {
2820 u32 ctrl;
2822 /* enable VLAN tag insert/strip */
2826 }
2829 {
2837 }
2841 }
2844 {
2845 u16 vid;
2851 }
2854 {
2863 /* enable receiving management packets to the host. this will probably
2864 * generate destination unreachable messages from the host OS, but
2865 * the packets will be handled on SMBUS
2866 */
2876 /* Check if IPMI pass-through decision filter already exists;
2877 * if so, enable it.
2878 */
2882 /* Ignore filters with anything other than IPMI ports */
2886 /* Enable this decision filter in MANC2H */
2891 }
2896 /* Create new decision filter in an empty filter */
2900 E1000_MDEF_PORT_664));
2902 j++;
2904 }
2909 }
2913 }
2915 /**
2916 * e1000_configure_tx - Configure Transmit Unit after Reset
2917 * @adapter: board private structure
2918 *
2919 * Configure the Tx unit of the MAC after a reset.
2920 **/
2922 {
2925 u64 tdba;
2928 /* Setup the HW Tx Head and Tail descriptor pointers */
2942 else
2945 /* Set the Tx Interrupt Delay register */
2947 /* Tx irq moderation */
2954 E1000_TXDCTL_WTHRESH);
2955 /* set up some performance related parameters to encourage the
2956 * hardware to use the bus more efficiently in bursts, depends
2957 * on the tx_int_delay to be enabled,
2958 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2959 * hthresh = 1 ==> prefetch when one or more available
2960 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2961 * BEWARE: this seems to work but should be considered first if
2962 * there are Tx hangs or other Tx related bugs
2963 */
2966 }
2967 /* erratum work around: set txdctl the same for both queues */
2970 /* Program the Transmit Control Register */
2978 /* set the speed mode bit, we'll clear it if we're not at
2979 * gigabit link later
2980 */
2981 #define SPEED_MODE_BIT BIT(21)
2984 }
2986 /* errata: program both queues to unweighted RR */
2994 }
2996 /* Setup Transmit Descriptor Settings for eop descriptor */
2999 /* only set IDE if we are delaying interrupts using the timers */
3003 /* enable Report Status bit */
3010 /* SPT and KBL Si errata workaround to avoid data corruption */
3012 u32 reg_val;
3019 /* SPT and KBL Si errata workaround to avoid Tx hang.
3020 * Dropping the number of outstanding requests from
3021 * 3 to 2 in order to avoid a buffer overrun.
3022 */
3026 }
3027 }
3029 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3030 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3032 /**
3033 * e1000_setup_rctl - configure the receive control registers
3034 * @adapter: Board private structure
3035 **/
3037 {
3042 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3043 * If jumbo frames not set, program related MAC/PHY registers
3044 * to h/w defaults
3045 */
3047 s32 ret_val;
3051 else
3056 }
3058 /* Program MC offset vector base */
3065 /* Do not Store bad packets */
3068 /* Enable Long Packet receive */
3071 else
3074 /* Some systems expect that the CRC is included in SMBUS traffic. The
3075 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3076 * host memory when this is enabled
3077 */
3081 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3083 u16 phy_data;
3096 }
3098 /* Setup buffer sizes */
3116 }
3118 /* Enable Extended Status in all Receive Descriptors */
3123 /* 82571 and greater support packet-split where the protocol
3124 * header is placed in skb->data and the packet data is
3125 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3126 * In the case of a non-split, skb->data is linearly filled,
3127 * followed by the page buffers. Therefore, skb->data is
3128 * sized to hold the largest protocol header.
3129 *
3130 * allocations using alloc_page take too long for regular MTU
3131 * so only enable packet split for jumbo frames
3132 *
3133 * Using pages when the page size is greater than 16k wastes
3134 * a lot of memory, since we allocate 3 pages at all times
3135 * per packet.
3136 */
3140 else
3146 /* Enable Packet split descriptors */
3154 fallthrough;
3157 fallthrough;
3161 }
3164 }
3166 /* This is useful for sniffing bad packets. */
3168 /* UPE and MPE will be handled by normal PROMISC logic
3169 * in e1000e_set_rx_mode
3170 */
3178 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3179 * and that breaks VLANs.
3180 */
3181 }
3184 /* just started the receive unit, no need to restart */
3186 }
3188 /**
3189 * e1000_configure_rx - Configure Receive Unit after Reset
3190 * @adapter: board private structure
3191 *
3192 * Configure the Rx unit of the MAC after a reset.
3193 **/
3195 {
3198 u64 rdba;
3202 /* this is a 32 byte descriptor */
3215 }
3217 /* disable receives while setting up the descriptors */
3225 /* set the writeback threshold (only takes effect if the RDTR
3226 * is set). set GRAN=1 and write back up to 0x4 worth, and
3227 * enable prefetching of 0x20 Rx descriptors
3228 * granularity = 01
3229 * wthresh = 04,
3230 * hthresh = 04,
3231 * pthresh = 0x20
3232 */
3235 }
3237 /* set the Receive Delay Timer Register */
3240 /* irq moderation */
3246 /* Auto-Mask interrupts upon ICR access */
3252 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3253 * the Base and Length of the Rx Descriptor Ring
3254 */
3267 else
3270 /* Enable Receive Checksum Offload for TCP and UDP */
3274 else
3278 /* With jumbo frames, excessive C-state transition latencies result
3279 * in dropped transactions.
3280 */
3282 u32 lat =
3290 }
3297 PM_QOS_DEFAULT_VALUE);
3298 }
3300 /* Enable Receives */
3302 }
3304 /**
3305 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3306 * @netdev: network interface device structure
3307 *
3308 * Writes multicast address list to the MTA hash table.
3309 * Returns: -ENOMEM on failure
3310 * 0 on no addresses written
3311 * X on writing X addresses to MTA
3312 */
3314 {
3322 /* nothing to program, so clear mc list */
3325 }
3331 /* update_mc_addr_list expects a packed array of only addresses. */
3340 }
3342 /**
3343 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3344 * @netdev: network interface device structure
3345 *
3346 * Writes unicast address list to the RAR table.
3347 * Returns: -ENOMEM on failure/insufficient address space
3348 * 0 on no addresses written
3349 * X on writing X addresses to the RAR table
3350 **/
3352 {
3360 /* save a rar entry for our hardware address */
3361 rar_entries--;
3363 /* save a rar entry for the LAA workaround */
3365 rar_entries--;
3367 /* return ENOMEM indicating insufficient memory for addresses */
3374 /* write the addresses in reverse order to avoid write
3375 * combining
3376 */
3385 count++;
3386 }
3387 }
3389 /* zero out the remaining RAR entries not used above */
3393 }
3397 }
3399 /**
3400 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3401 * @netdev: network interface device structure
3402 *
3403 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3404 * address list or the network interface flags are updated. This routine is
3405 * responsible for configuring the hardware for proper unicast, multicast,
3406 * promiscuous mode, and all-multi behavior.
3407 **/
3409 {
3412 u32 rctl;
3417 /* Check for Promiscuous and All Multicast modes */
3420 /* clear the affected bits */
3425 /* Do not hardware filter VLANs in promisc mode */
3433 /* Write addresses to the MTA, if the attempt fails
3434 * then we should just turn on promiscuous mode so
3435 * that we can at least receive multicast traffic
3436 */
3440 }
3442 /* Write addresses to available RAR registers, if there is not
3443 * sufficient space to store all the addresses then enable
3444 * unicast promiscuous mode
3445 */
3449 }
3455 else
3457 }
3460 {
3470 /* Direct all traffic to queue 0 */
3474 /* Disable raw packet checksumming so that RSS hash is placed in
3475 * descriptor on writeback.
3476 */
3483 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3484 E1000_MRQC_RSS_FIELD_IPV6 |
3485 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3486 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3489 }
3491 /**
3492 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3493 * @adapter: board private structure
3494 * @timinca: pointer to returned time increment attributes
3495 *
3496 * Get attributes for incrementing the System Time Register SYSTIML/H at
3497 * the default base frequency, and set the cyclecounter shift value.
3498 **/
3500 {
3504 /* Make sure clock is enabled on I217/I218/I219 before checking
3505 * the frequency
3506 */
3515 }
3516 }
3520 /* Stable 96MHz frequency */
3528 /* Stable 96MHz frequency */
3534 /* Stable 25MHz frequency */
3539 }
3542 /* Stable 24MHz frequency */
3553 /* Stable 24MHz frequency */
3559 /* Stable 38400KHz frequency */
3564 }
3568 /* Stable 25MHz frequency */
3576 }
3582 }
3584 /**
3585 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3586 * @adapter: board private structure
3587 * @config: timestamp configuration
3588 *
3589 * Outgoing time stamping can be enabled and disabled. Play nice and
3590 * disable it when requested, although it shouldn't cause any overhead
3591 * when no packet needs it. At most one packet in the queue may be
3592 * marked for time stamping, otherwise it would be impossible to tell
3593 * for sure to which packet the hardware time stamp belongs.
3594 *
3595 * Incoming time stamping has to be configured via the hardware filters.
3596 * Not all combinations are supported, in particular event type has to be
3597 * specified. Matching the kind of event packet is not supported, with the
3598 * exception of "all V2 events regardless of level 2 or 4".
3599 **/
3602 {
3610 u32 regval;
3615 /* flags reserved for future extensions - must be zero */
3627 }
3644 /* Also time stamps V2 L2 Path Delay Request/Response */
3650 /* Also time stamps V2 L2 Path Delay Request/Response. */
3656 /* Hardware cannot filter just V2 L4 Sync messages */
3657 fallthrough;
3659 /* Also time stamps V2 Path Delay Request/Response. */
3666 /* Hardware cannot filter just V2 L4 Delay Request messages */
3667 fallthrough;
3669 /* Also time stamps V2 Path Delay Request/Response. */
3677 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3678 fallthrough;
3686 /* For V1, the hardware can only filter Sync messages or
3687 * Delay Request messages but not both so fall-through to
3688 * time stamp all packets.
3689 */
3690 fallthrough;
3700 }
3704 /* enable/disable Tx h/w time stamping */
3713 }
3715 /* enable/disable Rx h/w time stamping */
3721 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3723 E1000_TSYNCRXCTL_TYPE_MASK))) {
3726 }
3728 /* L2: define ethertype filter for time stamped packets */
3732 /* define which PTP packets get time stamped */
3735 /* Filter by destination port */
3739 }
3744 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3749 }
3751 /**
3752 * e1000_configure - configure the hardware for Rx and Tx
3753 * @adapter: private board structure
3754 **/
3756 {
3771 }
3773 /**
3774 * e1000e_power_up_phy - restore link in case the phy was powered down
3775 * @adapter: address of board private structure
3776 *
3777 * The phy may be powered down to save power and turn off link when the
3778 * driver is unloaded and wake on lan is not enabled (among others)
3779 * *** this routine MUST be followed by a call to e1000e_reset ***
3780 **/
3782 {
3787 }
3789 /**
3790 * e1000_power_down_phy - Power down the PHY
3791 * @adapter: board private structure
3792 *
3793 * Power down the PHY so no link is implied when interface is down.
3794 * The PHY cannot be powered down if management or WoL is active.
3795 */
3797 {
3800 }
3802 /**
3803 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3804 * @adapter: board private structure
3805 *
3806 * We want to clear all pending descriptors from the TX ring.
3807 * zeroing happens when the HW reads the regs. We assign the ring itself as
3808 * the data of the next descriptor. We don't care about the data we are about
3809 * to reset the HW.
3810 */
3812 {
3828 /* flush descriptors to memory before notifying the HW */
3835 }
3837 /**
3838 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3839 * @adapter: board private structure
3840 *
3841 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3842 */
3844 {
3854 /* zero the lower 14 bits (prefetch and host thresholds) */
3857 /* update thresholds: prefetch threshold to 31, host threshold to 1
3858 * and make sure the granularity is "descriptors" and not "cache lines"
3859 */
3863 /* momentarily enable the RX ring for the changes to take effect */
3868 }
3870 /**
3871 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3872 * @adapter: board private structure
3873 *
3874 * In i219, the descriptor rings must be emptied before resetting the HW
3875 * or before changing the device state to D3 during runtime (runtime PM).
3876 *
3877 * Failure to do this will cause the HW to enter a unit hang state which can
3878 * only be released by PCI reset on the device
3879 *
3880 */
3883 {
3884 u16 hang_state;
3888 /* First, disable MULR fix in FEXTNVM11 */
3892 /* do nothing if we're not in faulty state, or if the queue is empty */
3899 /* recheck, maybe the fault is caused by the rx ring */
3904 }
3906 /**
3907 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3908 * @adapter: board private structure
3909 *
3910 * When the MAC is reset, all hardware bits for timesync will be reset to the
3911 * default values. This function will restore the settings last in place.
3912 * Since the clock SYSTIME registers are reset, we will simply restore the
3913 * cyclecounter to the kernel real clock time.
3914 **/
3916 {
3920 u32 timinca;
3921 s32 ret_val;
3927 /* restore the previous ptp frequency delta */
3930 /* set the default base frequency if no adjustment possible */
3934 }
3939 ret_val);
3941 }
3943 /* reset the systim ns time counter */
3949 /* restore the previous hwtstamp configuration settings */
3951 }
3953 /**
3954 * e1000e_reset - bring the hardware into a known good state
3955 * @adapter: board private structure
3956 *
3957 * This function boots the hardware and enables some settings that
3958 * require a configuration cycle of the hardware - those cannot be
3959 * set/changed during runtime. After reset the device needs to be
3960 * properly configured for Rx, Tx etc.
3961 */
3963 {
3969 u16 hwm;
3971 /* reset Packet Buffer Allocation to default */
3975 /* To maintain wire speed transmits, the Tx FIFO should be
3976 * large enough to accommodate two full transmit packets,
3977 * rounded up to the next 1KB and expressed in KB. Likewise,
3978 * the Rx FIFO should be large enough to accommodate at least
3979 * one full receive packet and is similarly rounded up and
3980 * expressed in KB.
3981 */
3983 /* upper 16 bits has Tx packet buffer allocation size in KB */
3985 /* lower 16 bits has Rx packet buffer allocation size in KB */
3987 /* the Tx fifo also stores 16 bytes of information about the Tx
3988 * but don't include ethernet FCS because hardware appends it
3989 */
3994 /* software strips receive CRC, so leave room for it */
3999 /* If current Tx allocation is less than the min Tx FIFO size,
4000 * and the min Tx FIFO size is less than the current Rx FIFO
4001 * allocation, take space away from current Rx allocation
4002 */
4007 /* if short on Rx space, Rx wins and must trump Tx
4008 * adjustment
4009 */
4012 }
4015 }
4017 /* flow control settings
4018 *
4019 * The high water mark must be low enough to fit one full frame
4020 * (or the size used for early receive) above it in the Rx FIFO.
4021 * Set it to the lower of:
4022 * - 90% of the Rx FIFO size, and
4023 * - the full Rx FIFO size minus one full frame
4024 */
4027 else
4041 }
4042 fallthrough;
4051 /* Workaround PCH LOM adapter hangs with certain network
4052 * loads. If hangs persist, try disabling Tx flow control.
4053 */
4060 }
4077 }
4084 }
4086 /* Alignment of Tx data is on an arbitrary byte boundary with the
4087 * maximum size per Tx descriptor limited only to the transmit
4088 * allocation of the packet buffer minus 96 bytes with an upper
4089 * limit of 24KB due to receive synchronization limitations.
4090 */
4094 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4095 * fit in receive buffer.
4096 */
4104 }
4111 }
4112 }
4116 /* Allow time for pending master requests to run */
4119 /* For parts with AMT enabled, let the firmware know
4120 * that the network interface is in control
4121 */
4132 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4137 /* restore systim and hwtstamp settings */
4140 /* Set EEE advertisement as appropriate */
4142 s32 ret_val;
4143 u16 adv_addr;
4156 }
4163 }
4170 }
4181 /* speed up time to link by disabling smart power down, ignore
4182 * the return value of this function because there is nothing
4183 * different we would do if it failed
4184 */
4188 }
4190 u32 reg;
4192 /* Fextnvm7 @ 0xe4[2] = 1 */
4196 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4199 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4201 }
4203 }
4205 /**
4206 * e1000e_trigger_lsc - trigger an LSC interrupt
4207 * @adapter:
4208 *
4209 * Fire a link status change interrupt to start the watchdog.
4210 **/
4212 {
4217 else
4219 }
4222 {
4223 /* hardware has been reset, we need to reload some things */
4232 /* Tx queue started by watchdog timer when link is up */
4235 }
4238 {
4244 /* flush pending descriptor writebacks to memory */
4248 /* execute the writes immediately */
4251 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4252 * write is successful
4253 */
4257 /* execute the writes immediately */
4259 }
4263 /**
4264 * e1000e_down - quiesce the device and optionally reset the hardware
4265 * @adapter: board private structure
4266 * @reset: boolean flag to reset the hardware or not
4267 */
4269 {
4274 /* signal that we're down so the interrupt handler does not
4275 * reschedule our watchdog timer
4276 */
4281 /* disable receives in the hardware */
4285 /* flush and sleep below */
4289 /* disable transmits in the hardware */
4294 /* flush both disables and wait for them to finish */
4314 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4325 }
4328 }
4331 {
4338 }
4340 /**
4341 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4342 * @hw: pointer to the HW structure
4343 * @systim: PHC time value read, sanitized and returned
4344 * @sts: structure to hold system time before and after reading SYSTIML,
4345 * may be NULL
4346 *
4347 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4348 * check to see that the time is incrementing at a reasonable
4349 * rate and is a multiple of incvalue.
4350 **/
4353 {
4355 u64 systim_next;
4356 u32 incvalue;
4361 /* latch SYSTIMH on read of SYSTIML */
4369 /* VMWare users have seen incvalue of zero, don't div / 0 */
4376 }
4379 }
4381 /**
4382 * e1000e_read_systim - read SYSTIM register
4383 * @adapter: board private structure
4384 * @sts: structure which will contain system time before and after reading
4385 * SYSTIML, may be NULL
4386 **/
4389 {
4392 u64 systim;
4393 /* SYSTIMH latching upon SYSTIML read does not work well.
4394 * This means that if SYSTIML overflows after we read it but before
4395 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4396 * will experience a huge non linear increment in the systime value
4397 * to fix that we test for overflow and if true, we re-read systime.
4398 */
4403 /* Is systimel is so large that overflow is possible? */
4409 /* There was an overflow, read again SYSTIMH, and use
4410 * systimel_2
4411 */
4414 }
4415 }
4423 }
4425 /**
4426 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4427 * @cc: cyclecounter structure
4428 **/
4430 {
4432 cc);
4435 }
4437 /**
4438 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4439 * @adapter: board private structure to initialize
4440 *
4441 * e1000_sw_init initializes the Adapter private data structure.
4442 * Fields are initialized based on PCI device information and
4443 * OS network device settings (MTU size).
4444 **/
4446 {
4463 /* Setup hardware time stamping cyclecounter */
4468 /* cc.shift set in e1000e_get_base_tininca() */
4472 }
4474 /* Explicitly disable IRQ since the NIC can be in any state. */
4479 }
4481 /**
4482 * e1000_intr_msi_test - Interrupt Handler
4483 * @irq: interrupt number
4484 * @data: pointer to a network interface device structure
4485 **/
4487 {
4496 /* Force memory writes to complete before acknowledging the
4497 * interrupt is handled.
4498 */
4500 }
4503 }
4505 /**
4506 * e1000_test_msi_interrupt - Returns 0 for successful test
4507 * @adapter: board private struct
4508 *
4509 * code flow taken from tg3.c
4510 **/
4512 {
4517 /* poll_enable hasn't been called yet, so don't need disable */
4518 /* clear any pending events */
4521 /* free the real vector and request a test handler */
4525 /* Assume that the test fails, if it succeeds then the test
4526 * MSI irq handler will unset this flag
4527 */
4539 }
4541 /* Force memory writes to complete before enabling and firing an
4542 * interrupt.
4543 */
4548 /* fire an unusual interrupt on the test handler */
4562 }
4567 msi_test_failed:
4570 }
4572 /**
4573 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4574 * @adapter: board private struct
4575 *
4576 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4577 **/
4579 {
4581 u16 pci_cmd;
4586 /* disable SERR in case the MSI write causes a master abort */
4594 /* re-enable SERR */
4599 }
4602 }
4604 /**
4605 * e1000e_open - Called when a network interface is made active
4606 * @netdev: network interface device structure
4607 *
4608 * Returns 0 on success, negative value on failure
4609 *
4610 * The open entry point is called when a network interface is made
4611 * active by the system (IFF_UP). At this point all resources needed
4612 * for transmit and receive operations are allocated, the interrupt
4613 * handler is registered with the OS, the watchdog timer is started,
4614 * and the stack is notified that the interface is ready.
4615 **/
4617 {
4623 /* disallow open during test */
4632 /* allocate transmit descriptors */
4637 /* allocate receive descriptors */
4642 /* If AMT is enabled, let the firmware know that the network
4643 * interface is now open and reset the part to a known state.
4644 */
4648 }
4656 /* DMA latency requirement to workaround jumbo issue */
4659 /* before we allocate an interrupt, we must be ready to handle it.
4660 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4661 * as soon as we call pci_request_irq, so we have to setup our
4662 * clean_rx handler before we do so.
4663 */
4670 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4671 * ignore e1000e MSI messages, which means we need to test our MSI
4672 * interrupt now
4673 */
4679 }
4680 }
4682 /* From here on the code is the same as e1000e_up() */
4698 err_req_irq:
4703 err_setup_rx:
4705 err_setup_tx:
4710 }
4712 /**
4713 * e1000e_close - Disables a network interface
4714 * @netdev: network interface device structure
4715 *
4716 * Returns 0, this is not allowed to fail
4717 *
4718 * The close entry point is called when an interface is de-activated
4719 * by the OS. The hardware is still under the drivers control, but
4720 * needs to be disabled. A global MAC reset is issued to stop the
4721 * hardware, and all transmit and receive resources are freed.
4722 **/
4724 {
4740 /* Link status message must follow this format */
4742 }
4749 /* kill manageability vlan ID if supported, but not if a vlan with
4750 * the same ID is registered on the host OS (let 8021q kill it)
4751 */
4756 /* If AMT is enabled, let the firmware know that the network
4757 * interface is now closed
4758 */
4768 }
4770 /**
4771 * e1000_set_mac - Change the Ethernet Address of the NIC
4772 * @netdev: network interface device structure
4773 * @p: pointer to an address structure
4774 *
4775 * Returns 0 on success, negative on failure
4776 **/
4778 {
4792 /* activate the work around */
4795 /* Hold a copy of the LAA in RAR[14] This is done so that
4796 * between the time RAR[0] gets clobbered and the time it
4797 * gets fixed (in e1000_watchdog), the actual LAA is in one
4798 * of the RARs and no incoming packets directed to this port
4799 * are dropped. Eventually the LAA will be in RAR[0] and
4800 * RAR[14]
4801 */
4804 }
4807 }
4809 /**
4810 * e1000e_update_phy_task - work thread to update phy
4811 * @work: pointer to our work struct
4812 *
4813 * this worker thread exists because we must acquire a
4814 * semaphore to read the phy, which we could msleep while
4815 * waiting for it, and we can't msleep in a timer.
4816 **/
4818 {
4821 update_phy_task);
4829 /* Enable EEE on 82579 after link up */
4832 }
4834 /**
4835 * e1000_update_phy_info - timre call-back to update PHY info
4836 * @t: pointer to timer_list containing private info adapter
4837 *
4838 * Need to wait a few seconds after link up to get diagnostic information from
4839 * the phy
4840 **/
4842 {
4849 }
4851 /**
4852 * e1000e_update_phy_stats - Update the PHY statistics counters
4853 * @adapter: board private structure
4854 *
4855 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4856 **/
4858 {
4860 s32 ret_val;
4861 u16 phy_data;
4867 /* A page set is expensive so check if already on desired page.
4868 * If not, set to the page with the PHY status registers.
4869 */
4880 }
4882 /* Single Collision Count */
4888 /* Excessive Collision Count */
4894 /* Multiple Collision Count */
4900 /* Late Collision Count */
4906 /* Collision Count - also used for adaptive IFS */
4912 /* Defer Count */
4918 /* Transmit with no CRS */
4924 release:
4926 }
4928 /**
4929 * e1000e_update_stats - Update the board statistics counters
4930 * @adapter: board private structure
4931 **/
4933 {
4938 /* Prevent stats update while adapter is being reset, or if the pci
4939 * connection is down.
4940 */
4956 /* Half-duplex statistics */
4972 }
4974 }
4989 /* used for adaptive IFS */
5000 /* Fill out the OS statistics structure */
5004 /* Rx Errors */
5006 /* RLEC on some newer hardware can be incorrect so build
5007 * our own version based on RUC and ROC
5008 */
5018 /* Tx Errors */
5024 /* Tx Dropped needs to be maintained elsewhere */
5026 /* Management Stats */
5031 /* Correctable ECC Errors */
5039 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5040 }
5041 }
5043 /**
5044 * e1000_phy_read_status - Update the PHY register status snapshot
5045 * @adapter: board private structure
5046 **/
5048 {
5068 /* Do not read PHY registers if link is not up
5069 * Set values to typical power-on defaults
5070 */
5074 BMSR_ERCAP);
5082 }
5083 }
5086 {
5090 /* Link status message must follow this format for user tools */
5098 }
5101 {
5106 /* get_link_status is set on LSC (link status) interrupt or
5107 * Rx sequence error interrupt. get_link_status will stay
5108 * true until the check_for_link establishes link
5109 * for copper adapters ONLY
5110 */
5118 }
5131 }
5135 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5137 }
5140 }
5143 {
5144 /* make sure the receive unit is started */
5152 }
5153 }
5156 {
5159 /* With 82574 controllers, PHY needs to be checked periodically
5160 * for hung state and reset, if two calls return true
5161 */
5164 else
5171 }
5172 }
5174 /**
5175 * e1000_watchdog - Timer Call-back
5176 * @t: pointer to timer_list containing private info adapter
5177 **/
5179 {
5182 /* Do the rest outside of interrupt context */
5185 /* TODO: make this use queue_delayed_work() */
5186 }
5189 {
5192 watchdog_task);
5206 /* Cancel scheduled suspend requests. */
5211 }
5221 /* Cancel scheduled suspend requests. */
5224 /* Checking if MAC is in DMoff state*/
5230 }
5234 /* Checking if MAC exited DMoff state */
5237 }
5239 /* update snapshot of PHY registers on LSC */
5246 /* check if SmartSpeed worked */
5252 /* On supported PHYs, check for duplex mismatch only
5253 * if link has autonegotiated at 10/100 half
5254 */
5261 u16 autoneg_exp;
5266 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5267 }
5269 /* adjust timeout factor according to speed/duplex */
5280 }
5282 /* workaround: re-program speed mode bit after
5283 * link-up event
5284 */
5287 u32 tarc0;
5292 }
5294 /* disable TSO for pcie and 10/100 speeds, to avoid
5295 * some hardware issues
5296 */
5310 /* oops */
5312 }
5316 }
5317 }
5319 /* enable transmits in the hardware, need to do this
5320 * after setting TARC(0)
5321 */
5326 /* Perform any post-link-up configuration before
5327 * reporting link up.
5328 */
5338 }
5343 /* Link status message must follow this format */
5351 /* 8000ES2LAN requires a Rx packet buffer work-around
5352 * on link down event; reset the controller to flush
5353 * the Rx packet buffer.
5354 */
5357 else
5359 LINK_TIMEOUT);
5360 }
5361 }
5363 link_up:
5378 /* If the link is lost the controller stops DMA, but
5379 * if there is queued Tx work it cannot be done. So
5380 * reset the controller to flush the Tx packet buffers.
5381 */
5386 /* If reset is necessary, do it outside of interrupt context. */
5389 /* return immediately since reset is imminent */
5391 }
5395 /* Simple mode for Interrupt Throttle Rate (ITR) */
5397 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5398 * Total asymmetrical Tx or Rx gets ITR=8000;
5399 * everyone else is between 2000-8000.
5400 */
5408 }
5410 /* Cause software interrupt to ensure Rx ring is cleaned */
5413 else
5416 /* flush pending descriptors to memory before detecting Tx hang */
5419 /* Force detection of hung controller every watchdog period */
5422 /* With 82571 controllers, LAA may be overwritten due to controller
5423 * reset from the other port. Set the appropriate LAA in RAR[0]
5424 */
5431 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5439 }
5440 }
5442 /* Reset the timer */
5446 }
5448 #define E1000_TX_FLAGS_CSUM 0x00000001
5449 #define E1000_TX_FLAGS_VLAN 0x00000002
5450 #define E1000_TX_FLAGS_TSO 0x00000004
5451 #define E1000_TX_FLAGS_IPV4 0x00000008
5452 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5453 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5454 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5455 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5458 __be16 protocol)
5459 {
5488 }
5514 i++;
5520 }
5523 __be16 protocol)
5524 {
5529 u8 css;
5541 /* XXX not handling all IPV6 headers */
5550 }
5568 i++;
5574 }
5579 {
5605 count++;
5608 i++;
5611 }
5612 }
5621 i++;
5633 DMA_TO_DEVICE);
5640 count++;
5641 }
5642 }
5645 /* multiply data chunks by size of headers */
5655 dma_error:
5659 count--;
5664 i--;
5667 }
5670 }
5673 {
5682 E1000_TXD_CMD_TSE;
5687 }
5692 }
5697 }
5705 }
5717 i++;
5724 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5728 /* Force memory writes to complete before letting h/w
5729 * know there are new descriptors to fetch. (Only
5730 * applicable for weak-ordered memory model archs,
5731 * such as IA-64).
5732 */
5736 }
5738 #define MINIMUM_DHCP_PACKET_SIZE 282
5741 {
5748 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5757 {
5771 }
5774 }
5777 {
5781 /* Herbert's original patch had:
5782 * smp_mb__after_netif_stop_queue();
5783 * but since that doesn't exist yet, just open code it.
5784 */
5787 /* We need to check again in a case another CPU has just
5788 * made room available.
5789 */
5793 /* A reprieve! */
5797 }
5800 {
5806 }
5810 {
5826 }
5831 }
5833 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5834 * pad skb in order to meet this minimum size requirement
5835 */
5841 u8 hdr_len;
5843 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5844 * points to just header, pull a few bytes of payload from
5845 * frags into skb->data
5846 */
5848 /* we do this workaround for ES2LAN, but it is un-necessary,
5849 * avoiding it could save a lot of cycles
5850 */
5859 }
5861 }
5862 }
5864 /* reserve a descriptor for the offload context */
5866 count++;
5867 count++;
5879 /* need: count + 2 desc gap to keep tail from touching
5880 * head, otherwise try next time
5881 */
5888 E1000_TX_FLAGS_VLAN_SHIFT);
5889 }
5897 }
5904 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5905 * 82571 hardware supports TSO capabilities for IPv6 as well...
5906 * no longer assume, we must.
5907 */
5914 /* if count is 0 then mapping error has occurred */
5916 nr_frags);
5928 }
5929 }
5935 /* Make sure there is space in the ring for the next send. */
5946 else
5948 }
5953 }
5956 }
5958 /**
5959 * e1000_tx_timeout - Respond to a Tx Hang
5960 * @netdev: network interface device structure
5961 * @txqueue: index of the hung queue (unused)
5962 **/
5964 {
5967 /* Do the reset outside of interrupt context */
5970 }
5973 {
5977 /* don't run the task if already down */
5984 }
5986 }
5988 /**
5989 * e1000_get_stats64 - Get System Network Statistics
5990 * @netdev: network interface device structure
5991 * @stats: rtnl_link_stats64 pointer
5992 *
5993 * Returns the address of the device statistics structure.
5994 **/
5997 {
6002 /* Fill out the OS statistics structure */
6010 /* Rx Errors */
6012 /* RLEC on some newer hardware can be incorrect so build
6013 * our own version based on RUC and ROC
6014 */
6023 /* Tx Errors */
6029 /* Tx Dropped needs to be maintained elsewhere */
6032 }
6034 /**
6035 * e1000_change_mtu - Change the Maximum Transfer Unit
6036 * @netdev: network interface device structure
6037 * @new_mtu: new value for maximum frame size
6038 *
6039 * Returns 0 on success, negative on failure
6040 **/
6042 {
6046 /* Jumbo frame support */
6051 }
6053 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6059 }
6063 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6074 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6075 * means we reserve 2 more, this pushes us to allocate from the next
6076 * larger slab size.
6077 * i.e. RXBUFFER_2048 --> size-4096 slab
6078 * However with the new *_jumbo_rx* routines, jumbo receives will use
6079 * fragmented skbs
6080 */
6084 else
6087 /* adjust allocation if LPE protects us, and we aren't using SBP */
6093 else
6101 }
6105 {
6152 }
6157 }
6159 }
6161 /**
6162 * e1000e_hwtstamp_ioctl - control hardware time stamping
6163 * @netdev: network interface device structure
6164 * @ifr: interface request
6165 *
6166 * Outgoing time stamping can be enabled and disabled. Play nice and
6167 * disable it when requested, although it shouldn't cause any overhead
6168 * when no packet needs it. At most one packet in the queue may be
6169 * marked for time stamping, otherwise it would be impossible to tell
6170 * for sure to which packet the hardware time stamp belongs.
6171 *
6172 * Incoming time stamping has to be configured via the hardware filters.
6173 * Not all combinations are supported, in particular event type has to be
6174 * specified. Matching the kind of event packet is not supported, with the
6175 * exception of "all V2 events regardless of level 2 or 4".
6176 **/
6178 {
6197 /* With V2 type filters which specify a Sync or Delay Request,
6198 * Path Delay Request/Response messages are also time stamped
6199 * by hardware so notify the caller the requested packets plus
6200 * some others are time stamped.
6201 */
6206 }
6210 }
6213 {
6218 }
6221 {
6233 }
6234 }
6237 {
6243 /* copy MAC RARs to PHY RARs */
6250 }
6252 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6257 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6264 }
6266 /* configure PHY Rx Control register */
6290 /* enable PHY wakeup in MAC register */
6295 /* configure and enable PHY wakeup in PHY registers */
6299 /* activate PHY wakeup */
6304 release:
6308 }
6311 {
6315 u32 ret_val;
6328 fl_out:
6330 }
6332 /* S0ix implementation */
6334 {
6336 u32 mac_data;
6337 u16 phy_data;
6339 /* Disable the periodic inband message,
6340 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6341 */
6347 /* Make sure we don't exit K1 every time a new packet arrives
6348 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6349 */
6354 /* Change the MAC/PHY interface to SMBus
6355 * Force the SMBus in PHY page769_23[0] = 1
6356 * Force the SMBus in MAC CTRL_EXT[11] = 1
6357 */
6365 /* DFT control: PHY bit: page769_20[0] = 1
6366 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6367 */
6376 /* Check MAC Tx/Rx packet buffer pointers.
6377 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6378 * pending traffic indication that would prevent power gating.
6379 */
6411 /* Enable the Dynamic Power Gating in the MAC */
6416 /* Disable the time synchronization clock */
6422 /* Dynamic Power Gating Enable */
6427 /* Disable disconnected cable conditioning for Power Gating */
6432 /* Don't wake from dynamic Power Gating with clock request */
6437 /* Ungate PGCB clock */
6442 /* Enable K1 off to enable mPHY Power Gating */
6447 /* Enable mPHY power gating for any link and speed */
6452 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6457 /* No MAC DPG gating SLP_S0 in modern standby
6458 * Switch the logic of the lanphypc to use PMC counter
6459 */
6463 }
6466 {
6468 u32 mac_data;
6469 u16 phy_data;
6471 /* Disable the Dynamic Power Gating in the MAC */
6476 /* Enable the time synchronization clock */
6481 /* Disable mPHY power gating for any link and speed */
6486 /* Disable K1 off */
6491 /* Disable Ungate PGCB clock */
6496 /* Cancel not waking from dynamic
6497 * Power Gating with clock request
6498 */
6503 /* Cancel disable disconnected cable conditioning
6504 * for Power Gating
6505 */
6510 /* Disable Dynamic Power Gating */
6515 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6520 /* Revert the lanphypc logic to use the internal Gbe counter
6521 * and not the PMC counter
6522 */
6527 /* Enable the periodic inband message,
6528 * Request PCIe clock in K1 page770_17[10:9] =01b
6529 */
6535 /* Return back configuration
6536 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6537 */
6542 /* Change the MAC/PHY interface to Kumeran
6543 * Unforce the SMBus in PHY page769_23[0] = 0
6544 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6545 */
6552 }
6555 {
6573 /* Quiesce the device without resetting the hardware */
6576 }
6581 /* Allow time for pending master requests to run */
6585 }
6588 {
6595 /* Runtime suspend should only enable wakeup for link changes */
6600 else
6611 /* turn on all-multi mode if wake on multicast is enabled */
6616 }
6626 e1000_media_type_internal_serdes) {
6627 /* keep the laser running in D3 */
6631 }
6640 /* enable wakeup by the PHY */
6645 /* enable wakeup by the MAC */
6648 }
6654 }
6660 /* ULP does not support wake from unicast, multicast
6661 * or broadcast.
6662 */
6667 }
6669 /* Ensure that the appropriate bits are set in LPI_CTRL
6670 * for EEE in Sx
6671 */
6683 I82579_EEE_100_SUPPORTED)
6687 I82579_EEE_1000_SUPPORTED)
6691 lpi_ctrl);
6692 }
6693 }
6695 }
6697 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6698 * would have already happened in close and is redundant.
6699 */
6704 /* The pci-e switch on some quad port adapters will report a
6705 * correctable error when the MAC transitions from D0 to D3. To
6706 * prevent this we need to mask off the correctable errors on the
6707 * downstream port of the pci-e switch.
6708 *
6709 * We don't have the associated upstream bridge while assigning
6710 * the PCI device into guest. For example, the KVM on power is
6711 * one of the cases.
6712 */
6715 u16 devctl;
6728 }
6731 }
6733 /**
6734 * __e1000e_disable_aspm - Disable ASPM states
6735 * @pdev: pointer to PCI device struct
6736 * @state: bit-mask of ASPM states to disable
6737 * @locked: indication if this context holds pci_bus_sem locked.
6738 *
6739 * Some devices *must* have certain ASPM states disabled per hardware errata.
6740 **/
6742 {
6757 }
6766 }
6768 /* Nothing to do if the ASPM states to be disabled already are */
6779 #ifdef CONFIG_PCIEASPM
6782 else
6785 /* Double-check ASPM control. If not disabled by the above, the
6786 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6787 * not enabled); override by writing PCI config space directly.
6788 */
6794 #endif
6796 /* Both device and parent should have the same ASPM setting.
6797 * Disable ASPM in downstream component first and then upstream.
6798 */
6803 aspm_dis_mask);
6804 }
6806 /**
6807 * e1000e_disable_aspm - Disable ASPM states.
6808 * @pdev: pointer to PCI device struct
6809 * @state: bit-mask of ASPM states to disable
6810 *
6811 * This function acquires the pci_bus_sem!
6812 * Some devices *must* have certain ASPM states disabled per hardware errata.
6813 **/
6815 {
6817 }
6819 /**
6820 * e1000e_disable_aspm_locked Disable ASPM states.
6821 * @pdev: pointer to PCI device struct
6822 * @state: bit-mask of ASPM states to disable
6823 *
6824 * This function must be called with pci_bus_sem acquired!
6825 * Some devices *must* have certain ASPM states disabled per hardware errata.
6826 **/
6828 {
6830 }
6833 {
6847 }
6850 err_irq:
6854 }
6857 {
6877 /* report the system wakeup cause from S3/S4 */
6879 u16 phy_data;
6890 }
6903 }
6905 }
6911 /* If the controller has AMT, do not set DRV_LOAD until the interface
6912 * is up. For all other cases, let the f/w know that the h/w is now
6913 * under the control of the driver.
6914 */
6919 }
6922 {
6936 /* Introduce S0ix implementation */
6939 }
6942 }
6945 {
6951 /* Introduce S0ix implementation */
6960 }
6963 {
6966 u16 eee_lp;
6973 }
6976 }
6979 {
6993 }
6996 {
7009 /* Down the device without resetting the hardware */
7011 }
7016 }
7019 }
7022 {
7028 }
7030 #ifdef CONFIG_NET_POLL_CONTROLLER
7033 {
7046 vector++;
7052 vector++;
7057 }
7060 }
7062 /**
7063 * e1000_netpoll
7064 * @netdev: network interface device structure
7065 *
7066 * Polling 'interrupt' - used by things like netconsole to send skbs
7067 * without having to re-enable interrupts. It's not called while
7068 * the interrupt routine is executing.
7069 */
7071 {
7088 }
7089 }
7090 #endif
7092 /**
7093 * e1000_io_error_detected - called when PCI error is detected
7094 * @pdev: Pointer to PCI device
7095 * @state: The current pci connection state
7096 *
7097 * This function is called after a PCI bus error affecting
7098 * this device has been detected.
7099 */
7101 pci_channel_state_t state)
7102 {
7110 /* Request a slot slot reset. */
7112 }
7114 /**
7115 * e1000_io_slot_reset - called after the pci bus has been reset.
7116 * @pdev: Pointer to PCI device
7117 *
7118 * Restart the card from scratch, as if from a cold-boot. Implementation
7119 * resembles the first-half of the e1000e_pm_resume routine.
7120 */
7122 {
7128 pci_ers_result_t result;
7153 }
7156 }
7158 /**
7159 * e1000_io_resume - called when traffic can start flowing again.
7160 * @pdev: Pointer to PCI device
7161 *
7162 * This callback is called when the error recovery driver tells us that
7163 * its OK to resume normal operation. Implementation resembles the
7164 * second-half of the e1000e_pm_resume routine.
7165 */
7167 {
7175 /* If the controller has AMT, do not set DRV_LOAD until the interface
7176 * is up. For all other cases, let the f/w know that the h/w is now
7177 * under the control of the driver.
7178 */
7181 }
7184 {
7187 u32 ret_val;
7190 /* print bus type/speed/width info */
7192 /* bus width */
7195 /* MAC address */
7200 E1000_PBANUM_LENGTH);
7205 }
7208 {
7219 /* Deep Smart Power Down (DSPD) */
7222 }
7223 }
7226 netdev_features_t features)
7227 {
7231 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7235 /* Since there is no support for separate Rx/Tx vlan accel
7236 * enable/disable make sure Tx flag is always in same state as Rx.
7237 */
7240 else
7244 }
7247 netdev_features_t features)
7248 {
7257 NETIF_F_RXALL)))
7264 /* We need to take it back to defaults, which might mean
7265 * stripping is still disabled at the adapter level.
7266 */
7269 else
7271 }
7272 }
7278 else
7282 }
7298 #ifdef CONFIG_NET_POLL_CONTROLLER
7300 #endif
7304 };
7306 /**
7307 * e1000_probe - Device Initialization Routine
7308 * @pdev: PCI device information struct
7309 * @ent: entry in e1000_pci_tbl
7310 *
7311 * Returns 0 on success, negative on failure
7312 *
7313 * e1000_probe initializes an adapter identified by a pci_dev structure.
7314 * The OS initialization, configuring of the adapter private structure,
7315 * and a hardware reset occur.
7316 **/
7318 {
7353 }
7354 }
7358 e1000e_driver_name);
7362 /* AER (Advanced Error Reporting) hooks */
7366 /* PCI config space info */
7410 }
7412 /* Set default EEE advertisement */
7416 /* construct the net_device struct */
7430 /* setup adapter struct */
7452 /* Copper options */
7457 }
7463 /* Set initial default active device features */
7465 NETIF_F_HW_VLAN_CTAG_RX |
7466 NETIF_F_HW_VLAN_CTAG_TX |
7467 NETIF_F_TSO |
7468 NETIF_F_TSO6 |
7469 NETIF_F_RXHASH |
7470 NETIF_F_RXCSUM |
7471 NETIF_F_HW_CSUM);
7473 /* Set user-changeable features (subset of all device features) */
7483 NETIF_F_TSO |
7484 NETIF_F_TSO6 |
7485 NETIF_F_HW_CSUM);
7492 }
7494 /* MTU range: 68 - max_hw_frame_size */
7502 /* before reading the NVM, reset the controller to
7503 * put the device in a known good starting state
7504 */
7507 /* systems with ASPM and others may see the checksum fail on the first
7508 * attempt. Let's give it a few tries
7509 */
7517 }
7518 }
7522 /* copy the MAC address */
7534 }
7545 /* Initialize link parameters. User can change them with ethtool */
7552 /* Initial Wake on LAN setting - If APM wake is enabled in
7553 * the EEPROM, enable the ACPI Magic Packet filter
7554 */
7556 /* APME bit in EEPROM is mapped to WUC.APME */
7566 NVM_INIT_CONTROL3_PORT_B,
7568 else
7570 NVM_INIT_CONTROL3_PORT_A,
7572 }
7574 /* fetch WoL from EEPROM */
7580 /* now that we have the eeprom settings, apply the special cases
7581 * where the eeprom may be wrong or the board simply won't support
7582 * wake on lan on a particular port
7583 */
7587 /* initialize the wol settings based on the eeprom settings */
7590 /* make sure adapter isn't asleep if manageability is enabled */
7595 /* save off EEPROM version number */
7601 }
7603 /* init PTP hardware clock */
7606 /* reset the hardware with the new settings */
7609 /* If the controller has AMT, do not set DRV_LOAD until the interface
7610 * is up. For all other cases, let the f/w know that the h/w is now
7611 * under the control of the driver.
7612 */
7624 /* carrier off reporting is important to ethtool even BEFORE open */
7636 err_register:
7639 err_eeprom:
7642 err_hw_init:
7645 err_sw_init:
7649 err_flashmap:
7651 err_ioremap:
7653 err_alloc_etherdev:
7655 err_pci_reg:
7656 err_dma:
7659 }
7661 /**
7662 * e1000_remove - Device Removal Routine
7663 * @pdev: PCI device information struct
7664 *
7665 * e1000_remove is called by the PCI subsystem to alert the driver
7666 * that it should release a PCI device. The could be caused by a
7667 * Hot-Plug event, or because the driver is going to be removed from
7668 * memory.
7669 **/
7671 {
7677 /* The timers may be rescheduled, so explicitly disable them
7678 * from being rescheduled.
7679 */
7695 }
7696 }
7703 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7704 * would have already happened in close and is redundant.
7705 */
7720 /* AER disable */
7724 }
7726 /* PCI Error Recovery (ERS) */
7731 };
7738 board_82571 },
7759 board_80003es2lan },
7761 board_80003es2lan },
7763 board_80003es2lan },
7765 board_80003es2lan },
7849 };
7853 #ifdef CONFIG_PM_SLEEP
7860 #endif
7862 e1000e_pm_runtime_idle)
7863 };
7865 /* PCI Device API Driver */
7873 },
7876 };
7878 /**
7879 * e1000_init_module - Driver Registration Routine
7880 *
7881 * e1000_init_module is the first routine called when the driver is
7882 * loaded. All it does is register with the PCI subsystem.
7883 **/
7885 {
7890 }
7893 /**
7894 * e1000_exit_module - Driver Exit Cleanup Routine
7895 *
7896 * e1000_exit_module is called just before the driver is removed
7897 * from memory.
7898 **/
7900 {
7902 }
7909 /* netdev.c */