drivers/net/usb/smsc95xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2  /***************************************************************************
   3  *
   4  * Copyright (C) 2007-2008 SMSC
   5  *
   6  *****************************************************************************/
   7
   8 #ifndef _SMSC95XX_H
   9 #define _SMSC95XX_H
  10
  11 /* Tx command words */
  12 #define TX_CMD_A_DATA_OFFSET_   (0x001F0000)    /* Data Start Offset */
  13 #define TX_CMD_A_FIRST_SEG_     (0x00002000)    /* First Segment */
  14 #define TX_CMD_A_LAST_SEG_      (0x00001000)    /* Last Segment */
  15 #define TX_CMD_A_BUF_SIZE_      (0x000007FF)    /* Buffer Size */
  16
  17 #define TX_CMD_B_CSUM_ENABLE    (0x00004000)    /* TX Checksum Enable */
  18 #define TX_CMD_B_ADD_CRC_DIS_   (0x00002000)    /* Add CRC Disable */
  19 #define TX_CMD_B_DIS_PADDING_   (0x00001000)    /* Disable Frame Padding */
  20 #define TX_CMD_B_FRAME_LENGTH_  (0x000007FF)    /* Frame Length (bytes) */
  21
  22 /* Rx status word */
  23 #define RX_STS_FF_              (0x40000000)    /* Filter Fail */
  24 #define RX_STS_FL_              (0x3FFF0000)    /* Frame Length */
  25 #define RX_STS_ES_              (0x00008000)    /* Error Summary */
  26 #define RX_STS_BF_              (0x00002000)    /* Broadcast Frame */
  27 #define RX_STS_LE_              (0x00001000)    /* Length Error */
  28 #define RX_STS_RF_              (0x00000800)    /* Runt Frame */
  29 #define RX_STS_MF_              (0x00000400)    /* Multicast Frame */
  30 #define RX_STS_TL_              (0x00000080)    /* Frame too long */
  31 #define RX_STS_CS_              (0x00000040)    /* Collision Seen */
  32 #define RX_STS_FT_              (0x00000020)    /* Frame Type */
  33 #define RX_STS_RW_              (0x00000010)    /* Receive Watchdog */
  34 #define RX_STS_ME_              (0x00000008)    /* MII Error */
  35 #define RX_STS_DB_              (0x00000004)    /* Dribbling */
  36 #define RX_STS_CRC_             (0x00000002)    /* CRC Error */
  37
  38 /* SCSRs - System Control and Status Registers */
  39 /* Device ID and Revision Register */
  40 #define ID_REV                  (0x00)
  41 #define ID_REV_CHIP_ID_MASK_    (0xFFFF0000)
  42 #define ID_REV_CHIP_REV_MASK_   (0x0000FFFF)
  43 #define ID_REV_CHIP_ID_9500_    (0x9500)
  44 #define ID_REV_CHIP_ID_9500A_   (0x9E00)
  45 #define ID_REV_CHIP_ID_9512_    (0xEC00)
  46 #define ID_REV_CHIP_ID_9530_    (0x9530)
  47 #define ID_REV_CHIP_ID_89530_   (0x9E08)
  48 #define ID_REV_CHIP_ID_9730_    (0x9730)
  49
  50 /* Interrupt Status Register */
  51 #define INT_STS                 (0x08)
  52 #define INT_STS_MAC_RTO_        (0x00040000)    /* MAC Reset Time Out */
  53 #define INT_STS_TX_STOP_        (0x00020000)    /* TX Stopped */
  54 #define INT_STS_RX_STOP_        (0x00010000)    /* RX Stopped */
  55 #define INT_STS_PHY_INT_        (0x00008000)    /* PHY Interrupt */
  56 #define INT_STS_TXE_            (0x00004000)    /* Transmitter Error */
  57 #define INT_STS_TDFU_           (0x00002000)    /* TX Data FIFO Underrun */
  58 #define INT_STS_TDFO_           (0x00001000)    /* TX Data FIFO Overrun */
  59 #define INT_STS_RXDF_           (0x00000800)    /* RX Dropped Frame */
  60 #define INT_STS_GPIOS_          (0x000007FF)    /* GPIOs Interrupts */
  61 #define INT_STS_CLEAR_ALL_      (0xFFFFFFFF)
  62
  63 /* Receive Configuration Register */
  64 #define RX_CFG                  (0x0C)
  65 #define RX_FIFO_FLUSH_          (0x00000001)    /* Receive FIFO Flush */
  66
  67 /* Transmit Configuration Register */
  68 #define TX_CFG                  (0x10)
  69 #define TX_CFG_ON_              (0x00000004)    /* Transmitter Enable */
  70 #define TX_CFG_STOP_            (0x00000002)    /* Stop Transmitter */
  71 #define TX_CFG_FIFO_FLUSH_      (0x00000001)    /* Transmit FIFO Flush */
  72
  73 /* Hardware Configuration Register */
  74 #define HW_CFG                  (0x14)
  75 #define HW_CFG_BIR_             (0x00001000)    /* Bulk In Empty Response */
  76 #define HW_CFG_LEDB_            (0x00000800)    /* Activity LED 80ms Bypass */
  77 #define HW_CFG_RXDOFF_          (0x00000600)    /* RX Data Offset */
  78 #define HW_CFG_SBP_             (0x00000100)    /* Stall Bulk Out Pipe Dis. */
  79 #define HW_CFG_IME_             (0x00000080)    /* Internal MII Visi. Enable */
  80 #define HW_CFG_DRP_             (0x00000040)    /* Discard Errored RX Frame */
  81 #define HW_CFG_MEF_             (0x00000020)    /* Mult. ETH Frames/USB pkt */
  82 #define HW_CFG_ETC_             (0x00000010)    /* EEPROM Timeout Control */
  83 #define HW_CFG_LRST_            (0x00000008)    /* Soft Lite Reset */
  84 #define HW_CFG_PSEL_            (0x00000004)    /* External PHY Select */
  85 #define HW_CFG_BCE_             (0x00000002)    /* Burst Cap Enable */
  86 #define HW_CFG_SRST_            (0x00000001)    /* Soft Reset */
  87
  88 /* Receive FIFO Information Register */
  89 #define RX_FIFO_INF             (0x18)
  90 #define RX_FIFO_INF_USED_       (0x0000FFFF)    /* RX Data FIFO Used Space */
  91
  92 /* Transmit FIFO Information Register */
  93 #define TX_FIFO_INF             (0x1C)
  94 #define TX_FIFO_INF_FREE_       (0x0000FFFF)    /* TX Data FIFO Free Space */
  95
  96 /* Power Management Control Register */
  97 #define PM_CTRL                 (0x20)
  98 #define PM_CTL_RES_CLR_WKP_STS  (0x00000200)    /* Resume Clears Wakeup STS */
  99 #define PM_CTL_RES_CLR_WKP_EN   (0x00000100)    /* Resume Clears Wkp Enables */
 100 #define PM_CTL_DEV_RDY_         (0x00000080)    /* Device Ready */
 101 #define PM_CTL_SUS_MODE_        (0x00000060)    /* Suspend Mode */
 102 #define PM_CTL_SUS_MODE_0       (0x00000000)
 103 #define PM_CTL_SUS_MODE_1       (0x00000020)
 104 #define PM_CTL_SUS_MODE_2       (0x00000040)
 105 #define PM_CTL_SUS_MODE_3       (0x00000060)
 106 #define PM_CTL_PHY_RST_         (0x00000010)    /* PHY Reset */
 107 #define PM_CTL_WOL_EN_          (0x00000008)    /* Wake On Lan Enable */
 108 #define PM_CTL_ED_EN_           (0x00000004)    /* Energy Detect Enable */
 109 #define PM_CTL_WUPS_            (0x00000003)    /* Wake Up Status */
 110 #define PM_CTL_WUPS_NO_         (0x00000000)    /* No Wake Up Event Detected */
 111 #define PM_CTL_WUPS_ED_         (0x00000001)    /* Energy Detect */
 112 #define PM_CTL_WUPS_WOL_        (0x00000002)    /* Wake On Lan */
 113 #define PM_CTL_WUPS_MULTI_      (0x00000003)    /* Multiple Events Occurred */
 114
 115 /* LED General Purpose IO Configuration Register */
 116 #define LED_GPIO_CFG            (0x24)
 117 #define LED_GPIO_CFG_SPD_LED    (0x01000000)    /* GPIOz as Speed LED */
 118 #define LED_GPIO_CFG_LNK_LED    (0x00100000)    /* GPIOy as Link LED */
 119 #define LED_GPIO_CFG_FDX_LED    (0x00010000)    /* GPIOx as Full Duplex LED */
 120
 121 /* General Purpose IO Configuration Register */
 122 #define GPIO_CFG                (0x28)
 123
 124 /* Automatic Flow Control Configuration Register */
 125 #define AFC_CFG                 (0x2C)
 126 #define AFC_CFG_HI_             (0x00FF0000)    /* Auto Flow Ctrl High Level */
 127 #define AFC_CFG_LO_             (0x0000FF00)    /* Auto Flow Ctrl Low Level */
 128 #define AFC_CFG_BACK_DUR_       (0x000000F0)    /* Back Pressure Duration */
 129 #define AFC_CFG_FC_MULT_        (0x00000008)    /* Flow Ctrl on Mcast Frame */
 130 #define AFC_CFG_FC_BRD_         (0x00000004)    /* Flow Ctrl on Bcast Frame */
 131 #define AFC_CFG_FC_ADD_         (0x00000002)    /* Flow Ctrl on Addr. Decode */
 132 #define AFC_CFG_FC_ANY_         (0x00000001)    /* Flow Ctrl on Any Frame */
 133 /* Hi watermark = 15.5Kb (~10 mtu pkts) */
 134 /* low watermark = 3k (~2 mtu pkts) */
 135 /* backpressure duration = ~ 350us */
 136 /* Apply FC on any frame. */
 137 #define AFC_CFG_DEFAULT         (0x00F830A1)
 138
 139 /* EEPROM Command Register */
 140 #define E2P_CMD                 (0x30)
 141 #define E2P_CMD_BUSY_           (0x80000000)    /* E2P Controller Busy */
 142 #define E2P_CMD_MASK_           (0x70000000)    /* Command Mask (see below) */
 143 #define E2P_CMD_READ_           (0x00000000)    /* Read Location */
 144 #define E2P_CMD_EWDS_           (0x10000000)    /* Erase/Write Disable */
 145 #define E2P_CMD_EWEN_           (0x20000000)    /* Erase/Write Enable */
 146 #define E2P_CMD_WRITE_          (0x30000000)    /* Write Location */
 147 #define E2P_CMD_WRAL_           (0x40000000)    /* Write All */
 148 #define E2P_CMD_ERASE_          (0x50000000)    /* Erase Location */
 149 #define E2P_CMD_ERAL_           (0x60000000)    /* Erase All */
 150 #define E2P_CMD_RELOAD_         (0x70000000)    /* Data Reload */
 151 #define E2P_CMD_TIMEOUT_        (0x00000400)    /* Set if no resp within 30ms */
 152 #define E2P_CMD_LOADED_         (0x00000200)    /* Valid EEPROM found */
 153 #define E2P_CMD_ADDR_           (0x000001FF)    /* Byte aligned address */
 154
 155 #define MAX_EEPROM_SIZE         (512)
 156
 157 /* EEPROM Data Register */
 158 #define E2P_DATA                (0x34)
 159 #define E2P_DATA_MASK_          (0x000000FF)    /* EEPROM Data Mask */
 160
 161 /* Burst Cap Register */
 162 #define BURST_CAP               (0x38)
 163 #define BURST_CAP_MASK_         (0x000000FF)    /* Max burst sent by the UTX */
 164
 165 /* Configuration Straps Status Register */
 166 #define STRAP_STATUS                    (0x3C)
 167 #define STRAP_STATUS_PWR_SEL_           (0x00000020) /* Device self-powered */
 168 #define STRAP_STATUS_AMDIX_EN_          (0x00000010) /* Auto-MDIX Enabled */
 169 #define STRAP_STATUS_PORT_SWAP_         (0x00000008) /* USBD+/USBD- Swapped */
 170 #define STRAP_STATUS_EEP_SIZE_          (0x00000004) /* EEPROM Size */
 171 #define STRAP_STATUS_RMT_WKP_           (0x00000002) /* Remote Wkp supported */
 172 #define STRAP_STATUS_EEP_DISABLE_       (0x00000001) /* EEPROM Disabled */
 173
 174 /* Data Port Select Register */
 175 #define DP_SEL                  (0x40)
 176
 177 /* Data Port Command Register */
 178 #define DP_CMD                  (0x44)
 179
 180 /* Data Port Address Register */
 181 #define DP_ADDR                 (0x48)
 182
 183 /* Data Port Data 0 Register */
 184 #define DP_DATA0                (0x4C)
 185
 186 /* Data Port Data 1 Register */
 187 #define DP_DATA1                (0x50)
 188
 189 /* General Purpose IO Wake Enable and Polarity Register */
 190 #define GPIO_WAKE               (0x64)
 191
 192 /* Interrupt Endpoint Control Register */
 193 #define INT_EP_CTL              (0x68)
 194 #define INT_EP_CTL_INTEP_       (0x80000000)    /* Always TX Interrupt PKT */
 195 #define INT_EP_CTL_MAC_RTO_     (0x00080000)    /* MAC Reset Time Out */
 196 #define INT_EP_CTL_RX_FIFO_     (0x00040000)    /* RX FIFO Has Frame */
 197 #define INT_EP_CTL_TX_STOP_     (0x00020000)    /* TX Stopped */
 198 #define INT_EP_CTL_RX_STOP_     (0x00010000)    /* RX Stopped */
 199 #define INT_EP_CTL_PHY_INT_     (0x00008000)    /* PHY Interrupt */
 200 #define INT_EP_CTL_TXE_         (0x00004000)    /* TX Error */
 201 #define INT_EP_CTL_TDFU_        (0x00002000)    /* TX Data FIFO Underrun */
 202 #define INT_EP_CTL_TDFO_        (0x00001000)    /* TX Data FIFO Overrun */
 203 #define INT_EP_CTL_RXDF_        (0x00000800)    /* RX Dropped Frame */
 204 #define INT_EP_CTL_GPIOS_       (0x000007FF)    /* GPIOs Interrupt Enable */
 205
 206 /* Bulk In Delay Register (units of 16.667ns, until ~1092µs) */
 207 #define BULK_IN_DLY             (0x6C)
 208
 209 /* MAC CSRs - MAC Control and Status Registers */
 210 /* MAC Control Register */
 211 #define MAC_CR                  (0x100)
 212 #define MAC_CR_RXALL_           (0x80000000)    /* Receive All Mode */
 213 #define MAC_CR_RCVOWN_          (0x00800000)    /* Disable Receive Own */
 214 #define MAC_CR_LOOPBK_          (0x00200000)    /* Loopback Operation Mode */
 215 #define MAC_CR_FDPX_            (0x00100000)    /* Full Duplex Mode */
 216 #define MAC_CR_MCPAS_           (0x00080000)    /* Pass All Multicast */
 217 #define MAC_CR_PRMS_            (0x00040000)    /* Promiscuous Mode */
 218 #define MAC_CR_INVFILT_         (0x00020000)    /* Inverse Filtering */
 219 #define MAC_CR_PASSBAD_         (0x00010000)    /* Pass Bad Frames */
 220 #define MAC_CR_HFILT_           (0x00008000)    /* Hash Only Filtering Mode */
 221 #define MAC_CR_HPFILT_          (0x00002000)    /* Hash/Perfect Filt. Mode */
 222 #define MAC_CR_LCOLL_           (0x00001000)    /* Late Collision Control */
 223 #define MAC_CR_BCAST_           (0x00000800)    /* Disable Broadcast Frames */
 224 #define MAC_CR_DISRTY_          (0x00000400)    /* Disable Retry */
 225 #define MAC_CR_PADSTR_          (0x00000100)    /* Automatic Pad Stripping */
 226 #define MAC_CR_BOLMT_MASK       (0x000000C0)    /* BackOff Limit */
 227 #define MAC_CR_DFCHK_           (0x00000020)    /* Deferral Check */
 228 #define MAC_CR_TXEN_            (0x00000008)    /* Transmitter Enable */
 229 #define MAC_CR_RXEN_            (0x00000004)    /* Receiver Enable */
 230
 231 /* MAC Address High Register */
 232 #define ADDRH                   (0x104)
 233
 234 /* MAC Address Low Register */
 235 #define ADDRL                   (0x108)
 236
 237 /* Multicast Hash Table High Register */
 238 #define HASHH                   (0x10C)
 239
 240 /* Multicast Hash Table Low Register */
 241 #define HASHL                   (0x110)
 242
 243 /* MII Access Register */
 244 #define MII_ADDR                (0x114)
 245 #define MII_WRITE_              (0x02)
 246 #define MII_BUSY_               (0x01)
 247 #define MII_READ_               (0x00) /* ~of MII Write bit */
 248
 249 /* MII Data Register */
 250 #define MII_DATA                (0x118)
 251
 252 /* Flow Control Register */
 253 #define FLOW                    (0x11C)
 254 #define FLOW_FCPT_              (0xFFFF0000)    /* Pause Time */
 255 #define FLOW_FCPASS_            (0x00000004)    /* Pass Control Frames */
 256 #define FLOW_FCEN_              (0x00000002)    /* Flow Control Enable */
 257 #define FLOW_FCBSY_             (0x00000001)    /* Flow Control Busy */
 258
 259 /* VLAN1 Tag Register */
 260 #define VLAN1                   (0x120)
 261
 262 /* VLAN2 Tag Register */
 263 #define VLAN2                   (0x124)
 264
 265 /* Wake Up Frame Filter Register */
 266 #define WUFF                    (0x128)
 267 #define LAN9500_WUFF_NUM        (4)
 268 #define LAN9500A_WUFF_NUM       (8)
 269
 270 /* Wake Up Control and Status Register */
 271 #define WUCSR                   (0x12C)
 272 #define WUCSR_WFF_PTR_RST_      (0x80000000)    /* WFrame Filter Pointer Rst */
 273 #define WUCSR_GUE_              (0x00000200)    /* Global Unicast Enable */
 274 #define WUCSR_WUFR_             (0x00000040)    /* Wakeup Frame Received */
 275 #define WUCSR_MPR_              (0x00000020)    /* Magic Packet Received */
 276 #define WUCSR_WAKE_EN_          (0x00000004)    /* Wakeup Frame Enable */
 277 #define WUCSR_MPEN_             (0x00000002)    /* Magic Packet Enable */
 278
 279 /* Checksum Offload Engine Control Register */
 280 #define COE_CR                  (0x130)
 281 #define Tx_COE_EN_              (0x00010000)    /* TX Csum Offload Enable */
 282 #define Rx_COE_MODE_            (0x00000002)    /* RX Csum Offload Mode */
 283 #define Rx_COE_EN_              (0x00000001)    /* RX Csum Offload Enable */
 284
 285 /* Vendor-specific PHY Definitions (via MII access) */
 286 /* EDPD NLP / crossover time configuration (LAN9500A only) */
 287 #define PHY_EDPD_CONFIG                 (16)
 288 #define PHY_EDPD_CONFIG_TX_NLP_EN_      ((u16)0x8000)
 289 #define PHY_EDPD_CONFIG_TX_NLP_1000_    ((u16)0x0000)
 290 #define PHY_EDPD_CONFIG_TX_NLP_768_     ((u16)0x2000)
 291 #define PHY_EDPD_CONFIG_TX_NLP_512_     ((u16)0x4000)
 292 #define PHY_EDPD_CONFIG_TX_NLP_256_     ((u16)0x6000)
 293 #define PHY_EDPD_CONFIG_RX_1_NLP_       ((u16)0x1000)
 294 #define PHY_EDPD_CONFIG_RX_NLP_64_      ((u16)0x0000)
 295 #define PHY_EDPD_CONFIG_RX_NLP_256_     ((u16)0x0400)
 296 #define PHY_EDPD_CONFIG_RX_NLP_512_     ((u16)0x0800)
 297 #define PHY_EDPD_CONFIG_RX_NLP_1000_    ((u16)0x0C00)
 298 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_  ((u16)0x0001)
 299 #define PHY_EDPD_CONFIG_DEFAULT         (PHY_EDPD_CONFIG_TX_NLP_EN_ | \
 300                                          PHY_EDPD_CONFIG_TX_NLP_768_ | \
 301                                          PHY_EDPD_CONFIG_RX_1_NLP_)
 302
 303 /* Mode Control/Status Register */
 304 #define PHY_MODE_CTRL_STS               (17)
 305 #define MODE_CTRL_STS_EDPWRDOWN_        ((u16)0x2000)
 306 #define MODE_CTRL_STS_ENERGYON_         ((u16)0x0002)
 307
 308 /* Control/Status Indication Register */
 309 #define SPECIAL_CTRL_STS                (27)
 310 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_   ((u16)0x8000)
 311 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_  ((u16)0x4000)
 312 #define SPECIAL_CTRL_STS_AMDIX_STATE_   ((u16)0x2000)
 313
 314 /* Interrupt Source Register */
 315 #define PHY_INT_SRC                     (29)
 316 #define PHY_INT_SRC_ENERGY_ON_          ((u16)0x0080)
 317 #define PHY_INT_SRC_ANEG_COMP_          ((u16)0x0040)
 318 #define PHY_INT_SRC_REMOTE_FAULT_       ((u16)0x0020)
 319 #define PHY_INT_SRC_LINK_DOWN_          ((u16)0x0010)
 320
 321 /* Interrupt Mask Register */
 322 #define PHY_INT_MASK                    (30)
 323 #define PHY_INT_MASK_ENERGY_ON_         ((u16)0x0080)
 324 #define PHY_INT_MASK_ANEG_COMP_         ((u16)0x0040)
 325 #define PHY_INT_MASK_REMOTE_FAULT_      ((u16)0x0020)
 326 #define PHY_INT_MASK_LINK_DOWN_         ((u16)0x0010)
 327 #define PHY_INT_MASK_DEFAULT_           (PHY_INT_MASK_ANEG_COMP_ | \
 328                                          PHY_INT_MASK_LINK_DOWN_)
 329 /* PHY Special Control/Status Register */
 330 #define PHY_SPECIAL                     (31)
 331 #define PHY_SPECIAL_SPD_                ((u16)0x001C)
 332 #define PHY_SPECIAL_SPD_10HALF_         ((u16)0x0004)
 333 #define PHY_SPECIAL_SPD_10FULL_         ((u16)0x0014)
 334 #define PHY_SPECIAL_SPD_100HALF_        ((u16)0x0008)
 335 #define PHY_SPECIAL_SPD_100FULL_        ((u16)0x0018)
 336
 337 /* USB Vendor Requests */
 338 #define USB_VENDOR_REQUEST_WRITE_REGISTER       0xA0
 339 #define USB_VENDOR_REQUEST_READ_REGISTER        0xA1
 340 #define USB_VENDOR_REQUEST_GET_STATS            0xA2
 341
 342 /* Interrupt Endpoint status word bitfields */
 343 #define INT_ENP_MAC_RTO_                ((u32)BIT(18))  /* MAC Reset Time Out */
 344 #define INT_ENP_TX_STOP_                ((u32)BIT(17))  /* TX Stopped */
 345 #define INT_ENP_RX_STOP_                ((u32)BIT(16))  /* RX Stopped */
 346 #define INT_ENP_PHY_INT_                ((u32)BIT(15))  /* PHY Interrupt */
 347 #define INT_ENP_TXE_                    ((u32)BIT(14))  /* TX Error */
 348 #define INT_ENP_TDFU_                   ((u32)BIT(13))  /* TX FIFO Underrun */
 349 #define INT_ENP_TDFO_                   ((u32)BIT(12))  /* TX FIFO Overrun */
 350 #define INT_ENP_RXDF_                   ((u32)BIT(11))  /* RX Dropped Frame */
 351
 352 #endif /* _SMSC95XX_H */