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WIP FPC-III support
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath10k / htt.h
blobcad59494f1752b44aaf9e8a9864a70bb2d7ce391
1 /* SPDX-License-Identifier: ISC */
2 /*
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6 */
7
8 #ifndef _HTT_H_
9 #define _HTT_H_
10
11 #include <linux/bug.h>
12 #include <linux/interrupt.h>
13 #include <linux/dmapool.h>
14 #include <linux/hashtable.h>
15 #include <linux/kfifo.h>
16 #include <net/mac80211.h>
17
18 #include "htc.h"
19 #include "hw.h"
20 #include "rx_desc.h"
21
22 enum htt_dbg_stats_type {
23 HTT_DBG_STATS_WAL_PDEV_TXRX = 1 << 0,
24 HTT_DBG_STATS_RX_REORDER = 1 << 1,
25 HTT_DBG_STATS_RX_RATE_INFO = 1 << 2,
26 HTT_DBG_STATS_TX_PPDU_LOG = 1 << 3,
27 HTT_DBG_STATS_TX_RATE_INFO = 1 << 4,
28 /* bits 5-23 currently reserved */
29
30 HTT_DBG_NUM_STATS /* keep this last */
31 };
32
33 enum htt_h2t_msg_type { /* host-to-target */
34 HTT_H2T_MSG_TYPE_VERSION_REQ = 0,
35 HTT_H2T_MSG_TYPE_TX_FRM = 1,
36 HTT_H2T_MSG_TYPE_RX_RING_CFG = 2,
37 HTT_H2T_MSG_TYPE_STATS_REQ = 3,
38 HTT_H2T_MSG_TYPE_SYNC = 4,
39 HTT_H2T_MSG_TYPE_AGGR_CFG = 5,
40 HTT_H2T_MSG_TYPE_FRAG_DESC_BANK_CFG = 6,
41
42 /* This command is used for sending management frames in HTT < 3.0.
43 * HTT >= 3.0 uses TX_FRM for everything.
44 */
45 HTT_H2T_MSG_TYPE_MGMT_TX = 7,
46 HTT_H2T_MSG_TYPE_TX_FETCH_RESP = 11,
47
48 HTT_H2T_NUM_MSGS /* keep this last */
49 };
50
51 struct htt_cmd_hdr {
52 u8 msg_type;
53 } __packed;
54
55 struct htt_ver_req {
56 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
57 } __packed;
58
59 /*
60 * HTT tx MSDU descriptor
61 *
62 * The HTT tx MSDU descriptor is created by the host HTT SW for each
63 * tx MSDU. The HTT tx MSDU descriptor contains the information that
64 * the target firmware needs for the FW's tx processing, particularly
65 * for creating the HW msdu descriptor.
66 * The same HTT tx descriptor is used for HL and LL systems, though
67 * a few fields within the tx descriptor are used only by LL or
68 * only by HL.
69 * The HTT tx descriptor is defined in two manners: by a struct with
70 * bitfields, and by a series of [dword offset, bit mask, bit shift]
71 * definitions.
72 * The target should use the struct def, for simplicitly and clarity,
73 * but the host shall use the bit-mast + bit-shift defs, to be endian-
74 * neutral. Specifically, the host shall use the get/set macros built
75 * around the mask + shift defs.
76 */
77 struct htt_data_tx_desc_frag {
78 union {
79 struct double_word_addr {
80 __le32 paddr;
81 __le32 len;
82 } __packed dword_addr;
83 struct triple_word_addr {
84 __le32 paddr_lo;
85 __le16 paddr_hi;
86 __le16 len_16;
87 } __packed tword_addr;
88 } __packed;
89 } __packed;
90
91 struct htt_msdu_ext_desc {
92 __le32 tso_flag[3];
93 __le16 ip_identification;
94 u8 flags;
95 u8 reserved;
96 struct htt_data_tx_desc_frag frags[6];
97 };
98
99 struct htt_msdu_ext_desc_64 {
100 __le32 tso_flag[5];
101 __le16 ip_identification;
102 u8 flags;
103 u8 reserved;
104 struct htt_data_tx_desc_frag frags[6];
105 };
106
107 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE BIT(0)
108 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE BIT(1)
109 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE BIT(2)
110 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE BIT(3)
111 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE BIT(4)
112
113 #define HTT_MSDU_CHECKSUM_ENABLE (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE \
114 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE \
115 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE \
116 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE \
117 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE)
118
119 #define HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 BIT(16)
120 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 BIT(17)
121 #define HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 BIT(18)
122 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 BIT(19)
123 #define HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64 BIT(20)
124 #define HTT_MSDU_EXT_DESC_FLAG_PARTIAL_CSUM_ENABLE_64 BIT(21)
125
126 #define HTT_MSDU_CHECKSUM_ENABLE_64 (HTT_MSDU_EXT_DESC_FLAG_IPV4_CSUM_ENABLE_64 \
127 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV4_CSUM_ENABLE_64 \
128 | HTT_MSDU_EXT_DESC_FLAG_UDP_IPV6_CSUM_ENABLE_64 \
129 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV4_CSUM_ENABLE_64 \
130 | HTT_MSDU_EXT_DESC_FLAG_TCP_IPV6_CSUM_ENABLE_64)
131
132 enum htt_data_tx_desc_flags0 {
133 HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT = 1 << 0,
134 HTT_DATA_TX_DESC_FLAGS0_NO_AGGR = 1 << 1,
135 HTT_DATA_TX_DESC_FLAGS0_NO_ENCRYPT = 1 << 2,
136 HTT_DATA_TX_DESC_FLAGS0_NO_CLASSIFY = 1 << 3,
137 HTT_DATA_TX_DESC_FLAGS0_RSVD0 = 1 << 4
138 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_MASK 0xE0
139 #define HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE_LSB 5
140 };
141
142 enum htt_data_tx_desc_flags1 {
143 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_BITS 6
144 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_MASK 0x003F
145 #define HTT_DATA_TX_DESC_FLAGS1_VDEV_ID_LSB 0
146 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_BITS 5
147 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_MASK 0x07C0
148 #define HTT_DATA_TX_DESC_FLAGS1_EXT_TID_LSB 6
149 HTT_DATA_TX_DESC_FLAGS1_POSTPONED = 1 << 11,
150 HTT_DATA_TX_DESC_FLAGS1_MORE_IN_BATCH = 1 << 12,
151 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L3_OFFLOAD = 1 << 13,
152 HTT_DATA_TX_DESC_FLAGS1_CKSUM_L4_OFFLOAD = 1 << 14,
153 HTT_DATA_TX_DESC_FLAGS1_TX_COMPLETE = 1 << 15
154 };
155
156 #define HTT_TX_CREDIT_DELTA_ABS_M 0xffff0000
157 #define HTT_TX_CREDIT_DELTA_ABS_S 16
158 #define HTT_TX_CREDIT_DELTA_ABS_GET(word) \
159 (((word) & HTT_TX_CREDIT_DELTA_ABS_M) >> HTT_TX_CREDIT_DELTA_ABS_S)
160
161 #define HTT_TX_CREDIT_SIGN_BIT_M 0x00000100
162 #define HTT_TX_CREDIT_SIGN_BIT_S 8
163 #define HTT_TX_CREDIT_SIGN_BIT_GET(word) \
164 (((word) & HTT_TX_CREDIT_SIGN_BIT_M) >> HTT_TX_CREDIT_SIGN_BIT_S)
165
166 enum htt_data_tx_ext_tid {
167 HTT_DATA_TX_EXT_TID_NON_QOS_MCAST_BCAST = 16,
168 HTT_DATA_TX_EXT_TID_MGMT = 17,
169 HTT_DATA_TX_EXT_TID_INVALID = 31
170 };
171
172 #define HTT_INVALID_PEERID 0xFFFF
173
174 /*
175 * htt_data_tx_desc - used for data tx path
176 *
177 * Note: vdev_id irrelevant for pkt_type == raw and no_classify == 1.
178 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_
179 * for special kinds of tids
180 * postponed: only for HL hosts. indicates if this is a resend
181 * (HL hosts manage queues on the host )
182 * more_in_batch: only for HL hosts. indicates if more packets are
183 * pending. this allows target to wait and aggregate
184 * freq: 0 means home channel of given vdev. intended for offchannel
185 */
186 struct htt_data_tx_desc {
187 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
188 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
189 __le16 len;
190 __le16 id;
191 __le32 frags_paddr;
192 union {
193 __le32 peerid;
194 struct {
195 __le16 peerid;
196 __le16 freq;
197 } __packed offchan_tx;
198 } __packed;
199 u8 prefetch[0]; /* start of frame, for FW classification engine */
200 } __packed;
201
202 struct htt_data_tx_desc_64 {
203 u8 flags0; /* %HTT_DATA_TX_DESC_FLAGS0_ */
204 __le16 flags1; /* %HTT_DATA_TX_DESC_FLAGS1_ */
205 __le16 len;
206 __le16 id;
207 __le64 frags_paddr;
208 union {
209 __le32 peerid;
210 struct {
211 __le16 peerid;
212 __le16 freq;
213 } __packed offchan_tx;
214 } __packed;
215 u8 prefetch[0]; /* start of frame, for FW classification engine */
216 } __packed;
217
218 enum htt_rx_ring_flags {
219 HTT_RX_RING_FLAGS_MAC80211_HDR = 1 << 0,
220 HTT_RX_RING_FLAGS_MSDU_PAYLOAD = 1 << 1,
221 HTT_RX_RING_FLAGS_PPDU_START = 1 << 2,
222 HTT_RX_RING_FLAGS_PPDU_END = 1 << 3,
223 HTT_RX_RING_FLAGS_MPDU_START = 1 << 4,
224 HTT_RX_RING_FLAGS_MPDU_END = 1 << 5,
225 HTT_RX_RING_FLAGS_MSDU_START = 1 << 6,
226 HTT_RX_RING_FLAGS_MSDU_END = 1 << 7,
227 HTT_RX_RING_FLAGS_RX_ATTENTION = 1 << 8,
228 HTT_RX_RING_FLAGS_FRAG_INFO = 1 << 9,
229 HTT_RX_RING_FLAGS_UNICAST_RX = 1 << 10,
230 HTT_RX_RING_FLAGS_MULTICAST_RX = 1 << 11,
231 HTT_RX_RING_FLAGS_CTRL_RX = 1 << 12,
232 HTT_RX_RING_FLAGS_MGMT_RX = 1 << 13,
233 HTT_RX_RING_FLAGS_NULL_RX = 1 << 14,
234 HTT_RX_RING_FLAGS_PHY_DATA_RX = 1 << 15
235 };
236
237 #define HTT_RX_RING_SIZE_MIN 128
238 #define HTT_RX_RING_SIZE_MAX 2048
239 #define HTT_RX_RING_SIZE HTT_RX_RING_SIZE_MAX
240 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1)
241 #define HTT_RX_RING_FILL_LEVEL_DUAL_MAC (HTT_RX_RING_SIZE - 1)
242
243 struct htt_rx_ring_setup_ring32 {
244 __le32 fw_idx_shadow_reg_paddr;
245 __le32 rx_ring_base_paddr;
246 __le16 rx_ring_len; /* in 4-byte words */
247 __le16 rx_ring_bufsize; /* rx skb size - in bytes */
248 __le16 flags; /* %HTT_RX_RING_FLAGS_ */
249 __le16 fw_idx_init_val;
250
251 /* the following offsets are in 4-byte units */
252 __le16 mac80211_hdr_offset;
253 __le16 msdu_payload_offset;
254 __le16 ppdu_start_offset;
255 __le16 ppdu_end_offset;
256 __le16 mpdu_start_offset;
257 __le16 mpdu_end_offset;
258 __le16 msdu_start_offset;
259 __le16 msdu_end_offset;
260 __le16 rx_attention_offset;
261 __le16 frag_info_offset;
262 } __packed;
263
264 struct htt_rx_ring_setup_ring64 {
265 __le64 fw_idx_shadow_reg_paddr;
266 __le64 rx_ring_base_paddr;
267 __le16 rx_ring_len; /* in 4-byte words */
268 __le16 rx_ring_bufsize; /* rx skb size - in bytes */
269 __le16 flags; /* %HTT_RX_RING_FLAGS_ */
270 __le16 fw_idx_init_val;
271
272 /* the following offsets are in 4-byte units */
273 __le16 mac80211_hdr_offset;
274 __le16 msdu_payload_offset;
275 __le16 ppdu_start_offset;
276 __le16 ppdu_end_offset;
277 __le16 mpdu_start_offset;
278 __le16 mpdu_end_offset;
279 __le16 msdu_start_offset;
280 __le16 msdu_end_offset;
281 __le16 rx_attention_offset;
282 __le16 frag_info_offset;
283 } __packed;
284
285 struct htt_rx_ring_setup_hdr {
286 u8 num_rings; /* supported values: 1, 2 */
287 __le16 rsvd0;
288 } __packed;
289
290 struct htt_rx_ring_setup_32 {
291 struct htt_rx_ring_setup_hdr hdr;
292 struct htt_rx_ring_setup_ring32 rings[];
293 } __packed;
294
295 struct htt_rx_ring_setup_64 {
296 struct htt_rx_ring_setup_hdr hdr;
297 struct htt_rx_ring_setup_ring64 rings[];
298 } __packed;
299
300 /*
301 * htt_stats_req - request target to send specified statistics
302 *
303 * @msg_type: hardcoded %HTT_H2T_MSG_TYPE_STATS_REQ
304 * @upload_types: see %htt_dbg_stats_type. this is 24bit field actually
305 * so make sure its little-endian.
306 * @reset_types: see %htt_dbg_stats_type. this is 24bit field actually
307 * so make sure its little-endian.
308 * @cfg_val: stat_type specific configuration
309 * @stat_type: see %htt_dbg_stats_type
310 * @cookie_lsb: used for confirmation message from target->host
311 * @cookie_msb: ditto as %cookie
312 */
313 struct htt_stats_req {
314 u8 upload_types[3];
315 u8 rsvd0;
316 u8 reset_types[3];
317 struct {
318 u8 mpdu_bytes;
319 u8 mpdu_num_msdus;
320 u8 msdu_bytes;
321 } __packed;
322 u8 stat_type;
323 __le32 cookie_lsb;
324 __le32 cookie_msb;
325 } __packed;
326
327 #define HTT_STATS_REQ_CFG_STAT_TYPE_INVALID 0xff
328 #define HTT_STATS_BIT_MASK GENMASK(16, 0)
329
330 /*
331 * htt_oob_sync_req - request out-of-band sync
332 *
333 * The HTT SYNC tells the target to suspend processing of subsequent
334 * HTT host-to-target messages until some other target agent locally
335 * informs the target HTT FW that the current sync counter is equal to
336 * or greater than (in a modulo sense) the sync counter specified in
337 * the SYNC message.
338 *
339 * This allows other host-target components to synchronize their operation
340 * with HTT, e.g. to ensure that tx frames don't get transmitted until a
341 * security key has been downloaded to and activated by the target.
342 * In the absence of any explicit synchronization counter value
343 * specification, the target HTT FW will use zero as the default current
344 * sync value.
345 *
346 * The HTT target FW will suspend its host->target message processing as long
347 * as 0 < (in-band sync counter - out-of-band sync counter) & 0xff < 128.
348 */
349 struct htt_oob_sync_req {
350 u8 sync_count;
351 __le16 rsvd0;
352 } __packed;
353
354 struct htt_aggr_conf {
355 u8 max_num_ampdu_subframes;
356 /* amsdu_subframes is limited by 0x1F mask */
357 u8 max_num_amsdu_subframes;
358 } __packed;
359
360 struct htt_aggr_conf_v2 {
361 u8 max_num_ampdu_subframes;
362 /* amsdu_subframes is limited by 0x1F mask */
363 u8 max_num_amsdu_subframes;
364 u8 reserved;
365 } __packed;
366
367 #define HTT_MGMT_FRM_HDR_DOWNLOAD_LEN 32
368 struct htt_mgmt_tx_desc_qca99x0 {
369 __le32 rate;
370 } __packed;
371
372 struct htt_mgmt_tx_desc {
373 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
374 __le32 msdu_paddr;
375 __le32 desc_id;
376 __le32 len;
377 __le32 vdev_id;
378 u8 hdr[HTT_MGMT_FRM_HDR_DOWNLOAD_LEN];
379 union {
380 struct htt_mgmt_tx_desc_qca99x0 qca99x0;
381 } __packed;
382 } __packed;
383
384 enum htt_mgmt_tx_status {
385 HTT_MGMT_TX_STATUS_OK = 0,
386 HTT_MGMT_TX_STATUS_RETRY = 1,
387 HTT_MGMT_TX_STATUS_DROP = 2
388 };
389
390 /*=== target -> host messages ===============================================*/
391
392 enum htt_main_t2h_msg_type {
393 HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF = 0x0,
394 HTT_MAIN_T2H_MSG_TYPE_RX_IND = 0x1,
395 HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH = 0x2,
396 HTT_MAIN_T2H_MSG_TYPE_PEER_MAP = 0x3,
397 HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
398 HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA = 0x5,
399 HTT_MAIN_T2H_MSG_TYPE_RX_DELBA = 0x6,
400 HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
401 HTT_MAIN_T2H_MSG_TYPE_PKTLOG = 0x8,
402 HTT_MAIN_T2H_MSG_TYPE_STATS_CONF = 0x9,
403 HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
404 HTT_MAIN_T2H_MSG_TYPE_SEC_IND = 0xb,
405 HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
406 HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
407 HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
408 HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND = 0x10,
409 HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
410 HTT_MAIN_T2H_MSG_TYPE_TEST,
411 /* keep this last */
412 HTT_MAIN_T2H_NUM_MSGS
413 };
414
415 enum htt_10x_t2h_msg_type {
416 HTT_10X_T2H_MSG_TYPE_VERSION_CONF = 0x0,
417 HTT_10X_T2H_MSG_TYPE_RX_IND = 0x1,
418 HTT_10X_T2H_MSG_TYPE_RX_FLUSH = 0x2,
419 HTT_10X_T2H_MSG_TYPE_PEER_MAP = 0x3,
420 HTT_10X_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
421 HTT_10X_T2H_MSG_TYPE_RX_ADDBA = 0x5,
422 HTT_10X_T2H_MSG_TYPE_RX_DELBA = 0x6,
423 HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
424 HTT_10X_T2H_MSG_TYPE_PKTLOG = 0x8,
425 HTT_10X_T2H_MSG_TYPE_STATS_CONF = 0x9,
426 HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
427 HTT_10X_T2H_MSG_TYPE_SEC_IND = 0xb,
428 HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
429 HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
430 HTT_10X_T2H_MSG_TYPE_TEST = 0xe,
431 HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
432 HTT_10X_T2H_MSG_TYPE_AGGR_CONF = 0x11,
433 HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x12,
434 HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0x13,
435 /* keep this last */
436 HTT_10X_T2H_NUM_MSGS
437 };
438
439 enum htt_tlv_t2h_msg_type {
440 HTT_TLV_T2H_MSG_TYPE_VERSION_CONF = 0x0,
441 HTT_TLV_T2H_MSG_TYPE_RX_IND = 0x1,
442 HTT_TLV_T2H_MSG_TYPE_RX_FLUSH = 0x2,
443 HTT_TLV_T2H_MSG_TYPE_PEER_MAP = 0x3,
444 HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
445 HTT_TLV_T2H_MSG_TYPE_RX_ADDBA = 0x5,
446 HTT_TLV_T2H_MSG_TYPE_RX_DELBA = 0x6,
447 HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
448 HTT_TLV_T2H_MSG_TYPE_PKTLOG = 0x8,
449 HTT_TLV_T2H_MSG_TYPE_STATS_CONF = 0x9,
450 HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
451 HTT_TLV_T2H_MSG_TYPE_SEC_IND = 0xb,
452 HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc, /* deprecated */
453 HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
454 HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
455 HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0xf,
456 HTT_TLV_T2H_MSG_TYPE_RX_PN_IND = 0x10,
457 HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x11,
458 HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND = 0x12,
459 /* 0x13 reservd */
460 HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE = 0x14,
461 HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE = 0x15,
462 HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR = 0x16,
463 HTT_TLV_T2H_MSG_TYPE_TEST,
464 /* keep this last */
465 HTT_TLV_T2H_NUM_MSGS
466 };
467
468 enum htt_10_4_t2h_msg_type {
469 HTT_10_4_T2H_MSG_TYPE_VERSION_CONF = 0x0,
470 HTT_10_4_T2H_MSG_TYPE_RX_IND = 0x1,
471 HTT_10_4_T2H_MSG_TYPE_RX_FLUSH = 0x2,
472 HTT_10_4_T2H_MSG_TYPE_PEER_MAP = 0x3,
473 HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP = 0x4,
474 HTT_10_4_T2H_MSG_TYPE_RX_ADDBA = 0x5,
475 HTT_10_4_T2H_MSG_TYPE_RX_DELBA = 0x6,
476 HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND = 0x7,
477 HTT_10_4_T2H_MSG_TYPE_PKTLOG = 0x8,
478 HTT_10_4_T2H_MSG_TYPE_STATS_CONF = 0x9,
479 HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND = 0xa,
480 HTT_10_4_T2H_MSG_TYPE_SEC_IND = 0xb,
481 HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND = 0xc,
482 HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND = 0xd,
483 HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND = 0xe,
484 HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE = 0xf,
485 HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND = 0x10,
486 HTT_10_4_T2H_MSG_TYPE_RX_PN_IND = 0x11,
487 HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND = 0x12,
488 HTT_10_4_T2H_MSG_TYPE_TEST = 0x13,
489 HTT_10_4_T2H_MSG_TYPE_EN_STATS = 0x14,
490 HTT_10_4_T2H_MSG_TYPE_AGGR_CONF = 0x15,
491 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND = 0x16,
492 HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM = 0x17,
493 HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD = 0x18,
494 /* 0x19 to 0x2f are reserved */
495 HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND = 0x30,
496 HTT_10_4_T2H_MSG_TYPE_PEER_STATS = 0x31,
497 /* keep this last */
498 HTT_10_4_T2H_NUM_MSGS
499 };
500
501 enum htt_t2h_msg_type {
502 HTT_T2H_MSG_TYPE_VERSION_CONF,
503 HTT_T2H_MSG_TYPE_RX_IND,
504 HTT_T2H_MSG_TYPE_RX_FLUSH,
505 HTT_T2H_MSG_TYPE_PEER_MAP,
506 HTT_T2H_MSG_TYPE_PEER_UNMAP,
507 HTT_T2H_MSG_TYPE_RX_ADDBA,
508 HTT_T2H_MSG_TYPE_RX_DELBA,
509 HTT_T2H_MSG_TYPE_TX_COMPL_IND,
510 HTT_T2H_MSG_TYPE_PKTLOG,
511 HTT_T2H_MSG_TYPE_STATS_CONF,
512 HTT_T2H_MSG_TYPE_RX_FRAG_IND,
513 HTT_T2H_MSG_TYPE_SEC_IND,
514 HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
515 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
516 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
517 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
518 HTT_T2H_MSG_TYPE_RX_PN_IND,
519 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
520 HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
521 HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
522 HTT_T2H_MSG_TYPE_CHAN_CHANGE,
523 HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
524 HTT_T2H_MSG_TYPE_AGGR_CONF,
525 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
526 HTT_T2H_MSG_TYPE_TEST,
527 HTT_T2H_MSG_TYPE_EN_STATS,
528 HTT_T2H_MSG_TYPE_TX_FETCH_IND,
529 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
530 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
531 HTT_T2H_MSG_TYPE_PEER_STATS,
532 /* keep this last */
533 HTT_T2H_NUM_MSGS
534 };
535
536 /*
537 * htt_resp_hdr - header for target-to-host messages
538 *
539 * msg_type: see htt_t2h_msg_type
540 */
541 struct htt_resp_hdr {
542 u8 msg_type;
543 } __packed;
544
545 #define HTT_RESP_HDR_MSG_TYPE_OFFSET 0
546 #define HTT_RESP_HDR_MSG_TYPE_MASK 0xff
547 #define HTT_RESP_HDR_MSG_TYPE_LSB 0
548
549 /* htt_ver_resp - response sent for htt_ver_req */
550 struct htt_ver_resp {
551 u8 minor;
552 u8 major;
553 u8 rsvd0;
554 } __packed;
555
556 #define HTT_MGMT_TX_CMPL_FLAG_ACK_RSSI BIT(0)
557
558 #define HTT_MGMT_TX_CMPL_INFO_ACK_RSSI_MASK GENMASK(7, 0)
559
560 struct htt_mgmt_tx_completion {
561 u8 rsvd0;
562 u8 rsvd1;
563 u8 flags;
564 __le32 desc_id;
565 __le32 status;
566 __le32 ppdu_id;
567 __le32 info;
568 } __packed;
569
570 #define HTT_RX_INDICATION_INFO0_EXT_TID_MASK (0x1F)
571 #define HTT_RX_INDICATION_INFO0_EXT_TID_LSB (0)
572 #define HTT_RX_INDICATION_INFO0_FLUSH_VALID (1 << 5)
573 #define HTT_RX_INDICATION_INFO0_RELEASE_VALID (1 << 6)
574 #define HTT_RX_INDICATION_INFO0_PPDU_DURATION BIT(7)
575
576 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_MASK 0x0000003F
577 #define HTT_RX_INDICATION_INFO1_FLUSH_START_SEQNO_LSB 0
578 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_MASK 0x00000FC0
579 #define HTT_RX_INDICATION_INFO1_FLUSH_END_SEQNO_LSB 6
580 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_MASK 0x0003F000
581 #define HTT_RX_INDICATION_INFO1_RELEASE_START_SEQNO_LSB 12
582 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_MASK 0x00FC0000
583 #define HTT_RX_INDICATION_INFO1_RELEASE_END_SEQNO_LSB 18
584 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_MASK 0xFF000000
585 #define HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES_LSB 24
586
587 #define HTT_TX_CMPL_FLAG_DATA_RSSI BIT(0)
588 #define HTT_TX_CMPL_FLAG_PPID_PRESENT BIT(1)
589 #define HTT_TX_CMPL_FLAG_PA_PRESENT BIT(2)
590 #define HTT_TX_CMPL_FLAG_PPDU_DURATION_PRESENT BIT(3)
591
592 #define HTT_TX_DATA_RSSI_ENABLE_WCN3990 BIT(3)
593 #define HTT_TX_DATA_APPEND_RETRIES BIT(0)
594 #define HTT_TX_DATA_APPEND_TIMESTAMP BIT(1)
595
596 struct htt_rx_indication_hdr {
597 u8 info0; /* %HTT_RX_INDICATION_INFO0_ */
598 __le16 peer_id;
599 __le32 info1; /* %HTT_RX_INDICATION_INFO1_ */
600 } __packed;
601
602 #define HTT_RX_INDICATION_INFO0_PHY_ERR_VALID (1 << 0)
603 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_MASK (0x1E)
604 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_LSB (1)
605 #define HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK (1 << 5)
606 #define HTT_RX_INDICATION_INFO0_END_VALID (1 << 6)
607 #define HTT_RX_INDICATION_INFO0_START_VALID (1 << 7)
608
609 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_MASK 0x00FFFFFF
610 #define HTT_RX_INDICATION_INFO1_VHT_SIG_A1_LSB 0
611 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_MASK 0xFF000000
612 #define HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE_LSB 24
613
614 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_MASK 0x00FFFFFF
615 #define HTT_RX_INDICATION_INFO2_VHT_SIG_A1_LSB 0
616 #define HTT_RX_INDICATION_INFO2_SERVICE_MASK 0xFF000000
617 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB 24
618
619 enum htt_rx_legacy_rate {
620 HTT_RX_OFDM_48 = 0,
621 HTT_RX_OFDM_24 = 1,
622 HTT_RX_OFDM_12,
623 HTT_RX_OFDM_6,
624 HTT_RX_OFDM_54,
625 HTT_RX_OFDM_36,
626 HTT_RX_OFDM_18,
627 HTT_RX_OFDM_9,
628
629 /* long preamble */
630 HTT_RX_CCK_11_LP = 0,
631 HTT_RX_CCK_5_5_LP = 1,
632 HTT_RX_CCK_2_LP,
633 HTT_RX_CCK_1_LP,
634 /* short preamble */
635 HTT_RX_CCK_11_SP,
636 HTT_RX_CCK_5_5_SP,
637 HTT_RX_CCK_2_SP
638 };
639
640 enum htt_rx_legacy_rate_type {
641 HTT_RX_LEGACY_RATE_OFDM = 0,
642 HTT_RX_LEGACY_RATE_CCK
643 };
644
645 enum htt_rx_preamble_type {
646 HTT_RX_LEGACY = 0x4,
647 HTT_RX_HT = 0x8,
648 HTT_RX_HT_WITH_TXBF = 0x9,
649 HTT_RX_VHT = 0xC,
650 HTT_RX_VHT_WITH_TXBF = 0xD,
651 };
652
653 /*
654 * Fields: phy_err_valid, phy_err_code, tsf,
655 * usec_timestamp, sub_usec_timestamp
656 * ..are valid only if end_valid == 1.
657 *
658 * Fields: rssi_chains, legacy_rate_type,
659 * legacy_rate_cck, preamble_type, service,
660 * vht_sig_*
661 * ..are valid only if start_valid == 1;
662 */
663 struct htt_rx_indication_ppdu {
664 u8 combined_rssi;
665 u8 sub_usec_timestamp;
666 u8 phy_err_code;
667 u8 info0; /* HTT_RX_INDICATION_INFO0_ */
668 struct {
669 u8 pri20_db;
670 u8 ext20_db;
671 u8 ext40_db;
672 u8 ext80_db;
673 } __packed rssi_chains[4];
674 __le32 tsf;
675 __le32 usec_timestamp;
676 __le32 info1; /* HTT_RX_INDICATION_INFO1_ */
677 __le32 info2; /* HTT_RX_INDICATION_INFO2_ */
678 } __packed;
679
680 enum htt_rx_mpdu_status {
681 HTT_RX_IND_MPDU_STATUS_UNKNOWN = 0x0,
682 HTT_RX_IND_MPDU_STATUS_OK,
683 HTT_RX_IND_MPDU_STATUS_ERR_FCS,
684 HTT_RX_IND_MPDU_STATUS_ERR_DUP,
685 HTT_RX_IND_MPDU_STATUS_ERR_REPLAY,
686 HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER,
687 /* only accept EAPOL frames */
688 HTT_RX_IND_MPDU_STATUS_UNAUTH_PEER,
689 HTT_RX_IND_MPDU_STATUS_OUT_OF_SYNC,
690 /* Non-data in promiscuous mode */
691 HTT_RX_IND_MPDU_STATUS_MGMT_CTRL,
692 HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR,
693 HTT_RX_IND_MPDU_STATUS_DECRYPT_ERR,
694 HTT_RX_IND_MPDU_STATUS_MPDU_LENGTH_ERR,
695 HTT_RX_IND_MPDU_STATUS_ENCRYPT_REQUIRED_ERR,
696 HTT_RX_IND_MPDU_STATUS_PRIVACY_ERR,
697
698 /*
699 * MISC: discard for unspecified reasons.
700 * Leave this enum value last.
701 */
702 HTT_RX_IND_MPDU_STATUS_ERR_MISC = 0xFF
703 };
704
705 struct htt_rx_indication_mpdu_range {
706 u8 mpdu_count;
707 u8 mpdu_range_status; /* %htt_rx_mpdu_status */
708 u8 pad0;
709 u8 pad1;
710 } __packed;
711
712 struct htt_rx_indication_prefix {
713 __le16 fw_rx_desc_bytes;
714 u8 pad0;
715 u8 pad1;
716 };
717
718 struct htt_rx_indication {
719 struct htt_rx_indication_hdr hdr;
720 struct htt_rx_indication_ppdu ppdu;
721 struct htt_rx_indication_prefix prefix;
722
723 /*
724 * the following fields are both dynamically sized, so
725 * take care addressing them
726 */
727
728 /* the size of this is %fw_rx_desc_bytes */
729 struct fw_rx_desc_base fw_desc;
730
731 /*
732 * %mpdu_ranges starts after &%prefix + roundup(%fw_rx_desc_bytes, 4)
733 * and has %num_mpdu_ranges elements.
734 */
735 struct htt_rx_indication_mpdu_range mpdu_ranges[];
736 } __packed;
737
738 /* High latency version of the RX indication */
739 struct htt_rx_indication_hl {
740 struct htt_rx_indication_hdr hdr;
741 struct htt_rx_indication_ppdu ppdu;
742 struct htt_rx_indication_prefix prefix;
743 struct fw_rx_desc_hl fw_desc;
744 struct htt_rx_indication_mpdu_range mpdu_ranges[];
745 } __packed;
746
747 struct htt_hl_rx_desc {
748 __le32 info;
749 __le32 pn_31_0;
750 union {
751 struct {
752 __le16 pn_47_32;
753 __le16 pn_63_48;
754 } pn16;
755 __le32 pn_63_32;
756 } u0;
757 __le32 pn_95_64;
758 __le32 pn_127_96;
759 } __packed;
760
761 static inline struct htt_rx_indication_mpdu_range *
762 htt_rx_ind_get_mpdu_ranges(struct htt_rx_indication *rx_ind)
763 {
764 void *ptr = rx_ind;
765
766 ptr += sizeof(rx_ind->hdr)
767 + sizeof(rx_ind->ppdu)
768 + sizeof(rx_ind->prefix)
769 + roundup(__le16_to_cpu(rx_ind->prefix.fw_rx_desc_bytes), 4);
770 return ptr;
771 }
772
773 static inline struct htt_rx_indication_mpdu_range *
774 htt_rx_ind_get_mpdu_ranges_hl(struct htt_rx_indication_hl *rx_ind)
775 {
776 void *ptr = rx_ind;
777
778 ptr += sizeof(rx_ind->hdr)
779 + sizeof(rx_ind->ppdu)
780 + sizeof(rx_ind->prefix)
781 + sizeof(rx_ind->fw_desc);
782 return ptr;
783 }
784
785 enum htt_rx_flush_mpdu_status {
786 HTT_RX_FLUSH_MPDU_DISCARD = 0,
787 HTT_RX_FLUSH_MPDU_REORDER = 1,
788 };
789
790 /*
791 * htt_rx_flush - discard or reorder given range of mpdus
792 *
793 * Note: host must check if all sequence numbers between
794 * [seq_num_start, seq_num_end-1] are valid.
795 */
796 struct htt_rx_flush {
797 __le16 peer_id;
798 u8 tid;
799 u8 rsvd0;
800 u8 mpdu_status; /* %htt_rx_flush_mpdu_status */
801 u8 seq_num_start; /* it is 6 LSBs of 802.11 seq no */
802 u8 seq_num_end; /* it is 6 LSBs of 802.11 seq no */
803 };
804
805 struct htt_rx_peer_map {
806 u8 vdev_id;
807 __le16 peer_id;
808 u8 addr[6];
809 u8 rsvd0;
810 u8 rsvd1;
811 } __packed;
812
813 struct htt_rx_peer_unmap {
814 u8 rsvd0;
815 __le16 peer_id;
816 } __packed;
817
818 enum htt_txrx_sec_cast_type {
819 HTT_TXRX_SEC_MCAST = 0,
820 HTT_TXRX_SEC_UCAST
821 };
822
823 enum htt_rx_pn_check_type {
824 HTT_RX_NON_PN_CHECK = 0,
825 HTT_RX_PN_CHECK
826 };
827
828 enum htt_rx_tkip_demic_type {
829 HTT_RX_NON_TKIP_MIC = 0,
830 HTT_RX_TKIP_MIC
831 };
832
833 enum htt_security_types {
834 HTT_SECURITY_NONE,
835 HTT_SECURITY_WEP128,
836 HTT_SECURITY_WEP104,
837 HTT_SECURITY_WEP40,
838 HTT_SECURITY_TKIP,
839 HTT_SECURITY_TKIP_NOMIC,
840 HTT_SECURITY_AES_CCMP,
841 HTT_SECURITY_WAPI,
842
843 HTT_NUM_SECURITY_TYPES /* keep this last! */
844 };
845
846 #define ATH10K_HTT_TXRX_PEER_SECURITY_MAX 2
847 #define ATH10K_TXRX_NUM_EXT_TIDS 19
848
849 enum htt_security_flags {
850 #define HTT_SECURITY_TYPE_MASK 0x7F
851 #define HTT_SECURITY_TYPE_LSB 0
852 HTT_SECURITY_IS_UNICAST = 1 << 7
853 };
854
855 struct htt_security_indication {
856 union {
857 /* dont use bitfields; undefined behaviour */
858 u8 flags; /* %htt_security_flags */
859 struct {
860 u8 security_type:7, /* %htt_security_types */
861 is_unicast:1;
862 } __packed;
863 } __packed;
864 __le16 peer_id;
865 u8 michael_key[8];
866 u8 wapi_rsc[16];
867 } __packed;
868
869 #define HTT_RX_BA_INFO0_TID_MASK 0x000F
870 #define HTT_RX_BA_INFO0_TID_LSB 0
871 #define HTT_RX_BA_INFO0_PEER_ID_MASK 0xFFF0
872 #define HTT_RX_BA_INFO0_PEER_ID_LSB 4
873
874 struct htt_rx_addba {
875 u8 window_size;
876 __le16 info0; /* %HTT_RX_BA_INFO0_ */
877 } __packed;
878
879 struct htt_rx_delba {
880 u8 rsvd0;
881 __le16 info0; /* %HTT_RX_BA_INFO0_ */
882 } __packed;
883
884 enum htt_data_tx_status {
885 HTT_DATA_TX_STATUS_OK = 0,
886 HTT_DATA_TX_STATUS_DISCARD = 1,
887 HTT_DATA_TX_STATUS_NO_ACK = 2,
888 HTT_DATA_TX_STATUS_POSTPONE = 3, /* HL only */
889 HTT_DATA_TX_STATUS_DOWNLOAD_FAIL = 128
890 };
891
892 enum htt_data_tx_flags {
893 #define HTT_DATA_TX_STATUS_MASK 0x07
894 #define HTT_DATA_TX_STATUS_LSB 0
895 #define HTT_DATA_TX_TID_MASK 0x78
896 #define HTT_DATA_TX_TID_LSB 3
897 HTT_DATA_TX_TID_INVALID = 1 << 7
898 };
899
900 #define HTT_TX_COMPL_INV_MSDU_ID 0xFFFF
901
902 struct htt_append_retries {
903 __le16 msdu_id;
904 u8 tx_retries;
905 u8 flag;
906 } __packed;
907
908 struct htt_data_tx_completion_ext {
909 struct htt_append_retries a_retries;
910 __le32 t_stamp;
911 __le16 msdus_rssi[];
912 } __packed;
913
914 /**
915 * @brief target -> host TX completion indication message definition
916 *
917 * @details
918 * The following diagram shows the format of the TX completion indication sent
919 * from the target to the host
920 *
921 * |31 28|27|26|25|24|23 16| 15 |14 11|10 8|7 0|
922 * |-------------------------------------------------------------|
923 * header: |rsvd |A2|TP|A1|A0| num | t_i| tid |status| msg_type |
924 * |-------------------------------------------------------------|
925 * payload: | MSDU1 ID | MSDU0 ID |
926 * |-------------------------------------------------------------|
927 * : MSDU3 ID : MSDU2 ID :
928 * |-------------------------------------------------------------|
929 * | struct htt_tx_compl_ind_append_retries |
930 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
931 * | struct htt_tx_compl_ind_append_tx_tstamp |
932 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
933 * | MSDU1 ACK RSSI | MSDU0 ACK RSSI |
934 * |-------------------------------------------------------------|
935 * : MSDU3 ACK RSSI : MSDU2 ACK RSSI :
936 * |- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -|
937 * -msg_type
938 * Bits 7:0
939 * Purpose: identifies this as HTT TX completion indication
940 * -status
941 * Bits 10:8
942 * Purpose: the TX completion status of payload fragmentations descriptors
943 * Value: could be HTT_TX_COMPL_IND_STAT_OK or HTT_TX_COMPL_IND_STAT_DISCARD
944 * -tid
945 * Bits 14:11
946 * Purpose: the tid associated with those fragmentation descriptors. It is
947 * valid or not, depending on the tid_invalid bit.
948 * Value: 0 to 15
949 * -tid_invalid
950 * Bits 15:15
951 * Purpose: this bit indicates whether the tid field is valid or not
952 * Value: 0 indicates valid, 1 indicates invalid
953 * -num
954 * Bits 23:16
955 * Purpose: the number of payload in this indication
956 * Value: 1 to 255
957 * -A0 = append
958 * Bits 24:24
959 * Purpose: append the struct htt_tx_compl_ind_append_retries which contains
960 * the number of tx retries for one MSDU at the end of this message
961 * Value: 0 indicates no appending, 1 indicates appending
962 * -A1 = append1
963 * Bits 25:25
964 * Purpose: Append the struct htt_tx_compl_ind_append_tx_tstamp which
965 * contains the timestamp info for each TX msdu id in payload.
966 * Value: 0 indicates no appending, 1 indicates appending
967 * -TP = MSDU tx power presence
968 * Bits 26:26
969 * Purpose: Indicate whether the TX_COMPL_IND includes a tx power report
970 * for each MSDU referenced by the TX_COMPL_IND message.
971 * The order of the per-MSDU tx power reports matches the order
972 * of the MSDU IDs.
973 * Value: 0 indicates not appending, 1 indicates appending
974 * -A2 = append2
975 * Bits 27:27
976 * Purpose: Indicate whether data ACK RSSI is appended for each MSDU in
977 * TX_COMP_IND message. The order of the per-MSDU ACK RSSI report
978 * matches the order of the MSDU IDs.
979 * The ACK RSSI values are valid when status is COMPLETE_OK (and
980 * this append2 bit is set).
981 * Value: 0 indicates not appending, 1 indicates appending
982 */
983
984 struct htt_data_tx_completion {
985 union {
986 u8 flags;
987 struct {
988 u8 status:3,
989 tid:4,
990 tid_invalid:1;
991 } __packed;
992 } __packed;
993 u8 num_msdus;
994 u8 flags2; /* HTT_TX_CMPL_FLAG_DATA_RSSI */
995 __le16 msdus[]; /* variable length based on %num_msdus */
996 } __packed;
997
998 #define HTT_TX_PPDU_DUR_INFO0_PEER_ID_MASK GENMASK(15, 0)
999 #define HTT_TX_PPDU_DUR_INFO0_TID_MASK GENMASK(20, 16)
1000
1001 struct htt_data_tx_ppdu_dur {
1002 __le32 info0; /* HTT_TX_PPDU_DUR_INFO0_ */
1003 __le32 tx_duration; /* in usecs */
1004 } __packed;
1005
1006 #define HTT_TX_COMPL_PPDU_DUR_INFO0_NUM_ENTRIES_MASK GENMASK(7, 0)
1007
1008 struct htt_data_tx_compl_ppdu_dur {
1009 __le32 info0; /* HTT_TX_COMPL_PPDU_DUR_INFO0_ */
1010 struct htt_data_tx_ppdu_dur ppdu_dur[];
1011 } __packed;
1012
1013 struct htt_tx_compl_ind_base {
1014 u32 hdr;
1015 u16 payload[1/*or more*/];
1016 } __packed;
1017
1018 struct htt_rc_tx_done_params {
1019 u32 rate_code;
1020 u32 rate_code_flags;
1021 u32 flags;
1022 u32 num_enqued; /* 1 for non-AMPDU */
1023 u32 num_retries;
1024 u32 num_failed; /* for AMPDU */
1025 u32 ack_rssi;
1026 u32 time_stamp;
1027 u32 is_probe;
1028 };
1029
1030 struct htt_rc_update {
1031 u8 vdev_id;
1032 __le16 peer_id;
1033 u8 addr[6];
1034 u8 num_elems;
1035 u8 rsvd0;
1036 struct htt_rc_tx_done_params params[]; /* variable length %num_elems */
1037 } __packed;
1038
1039 /* see htt_rx_indication for similar fields and descriptions */
1040 struct htt_rx_fragment_indication {
1041 union {
1042 u8 info0; /* %HTT_RX_FRAG_IND_INFO0_ */
1043 struct {
1044 u8 ext_tid:5,
1045 flush_valid:1;
1046 } __packed;
1047 } __packed;
1048 __le16 peer_id;
1049 __le32 info1; /* %HTT_RX_FRAG_IND_INFO1_ */
1050 __le16 fw_rx_desc_bytes;
1051 __le16 rsvd0;
1052
1053 u8 fw_msdu_rx_desc[];
1054 } __packed;
1055
1056 #define ATH10K_IEEE80211_EXTIV BIT(5)
1057 #define ATH10K_IEEE80211_TKIP_MICLEN 8 /* trailing MIC */
1058
1059 #define HTT_RX_FRAG_IND_INFO0_HEADER_LEN 16
1060
1061 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_MASK 0x1F
1062 #define HTT_RX_FRAG_IND_INFO0_EXT_TID_LSB 0
1063 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_MASK 0x20
1064 #define HTT_RX_FRAG_IND_INFO0_FLUSH_VALID_LSB 5
1065
1066 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_MASK 0x0000003F
1067 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_START_LSB 0
1068 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_MASK 0x00000FC0
1069 #define HTT_RX_FRAG_IND_INFO1_FLUSH_SEQ_NUM_END_LSB 6
1070
1071 struct htt_rx_pn_ind {
1072 __le16 peer_id;
1073 u8 tid;
1074 u8 seqno_start;
1075 u8 seqno_end;
1076 u8 pn_ie_count;
1077 u8 reserved;
1078 u8 pn_ies[];
1079 } __packed;
1080
1081 struct htt_rx_offload_msdu {
1082 __le16 msdu_len;
1083 __le16 peer_id;
1084 u8 vdev_id;
1085 u8 tid;
1086 u8 fw_desc;
1087 u8 payload[];
1088 } __packed;
1089
1090 struct htt_rx_offload_ind {
1091 u8 reserved;
1092 __le16 msdu_count;
1093 } __packed;
1094
1095 struct htt_rx_in_ord_msdu_desc {
1096 __le32 msdu_paddr;
1097 __le16 msdu_len;
1098 u8 fw_desc;
1099 u8 reserved;
1100 } __packed;
1101
1102 struct htt_rx_in_ord_msdu_desc_ext {
1103 __le64 msdu_paddr;
1104 __le16 msdu_len;
1105 u8 fw_desc;
1106 u8 reserved;
1107 } __packed;
1108
1109 struct htt_rx_in_ord_ind {
1110 u8 info;
1111 __le16 peer_id;
1112 u8 vdev_id;
1113 u8 reserved;
1114 __le16 msdu_count;
1115 union {
1116 struct htt_rx_in_ord_msdu_desc msdu_descs32[0];
1117 struct htt_rx_in_ord_msdu_desc_ext msdu_descs64[0];
1118 } __packed;
1119 } __packed;
1120
1121 #define HTT_RX_IN_ORD_IND_INFO_TID_MASK 0x0000001f
1122 #define HTT_RX_IN_ORD_IND_INFO_TID_LSB 0
1123 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_MASK 0x00000020
1124 #define HTT_RX_IN_ORD_IND_INFO_OFFLOAD_LSB 5
1125 #define HTT_RX_IN_ORD_IND_INFO_FRAG_MASK 0x00000040
1126 #define HTT_RX_IN_ORD_IND_INFO_FRAG_LSB 6
1127
1128 /*
1129 * target -> host test message definition
1130 *
1131 * The following field definitions describe the format of the test
1132 * message sent from the target to the host.
1133 * The message consists of a 4-octet header, followed by a variable
1134 * number of 32-bit integer values, followed by a variable number
1135 * of 8-bit character values.
1136 *
1137 * |31 16|15 8|7 0|
1138 * |-----------------------------------------------------------|
1139 * | num chars | num ints | msg type |
1140 * |-----------------------------------------------------------|
1141 * | int 0 |
1142 * |-----------------------------------------------------------|
1143 * | int 1 |
1144 * |-----------------------------------------------------------|
1145 * | ... |
1146 * |-----------------------------------------------------------|
1147 * | char 3 | char 2 | char 1 | char 0 |
1148 * |-----------------------------------------------------------|
1149 * | | | ... | char 4 |
1150 * |-----------------------------------------------------------|
1151 * - MSG_TYPE
1152 * Bits 7:0
1153 * Purpose: identifies this as a test message
1154 * Value: HTT_MSG_TYPE_TEST
1155 * - NUM_INTS
1156 * Bits 15:8
1157 * Purpose: indicate how many 32-bit integers follow the message header
1158 * - NUM_CHARS
1159 * Bits 31:16
1160 * Purpose: indicate how many 8-bit characters follow the series of integers
1161 */
1162 struct htt_rx_test {
1163 u8 num_ints;
1164 __le16 num_chars;
1165
1166 /* payload consists of 2 lists:
1167 * a) num_ints * sizeof(__le32)
1168 * b) num_chars * sizeof(u8) aligned to 4bytes
1169 */
1170 u8 payload[];
1171 } __packed;
1172
1173 static inline __le32 *htt_rx_test_get_ints(struct htt_rx_test *rx_test)
1174 {
1175 return (__le32 *)rx_test->payload;
1176 }
1177
1178 static inline u8 *htt_rx_test_get_chars(struct htt_rx_test *rx_test)
1179 {
1180 return rx_test->payload + (rx_test->num_ints * sizeof(__le32));
1181 }
1182
1183 /*
1184 * target -> host packet log message
1185 *
1186 * The following field definitions describe the format of the packet log
1187 * message sent from the target to the host.
1188 * The message consists of a 4-octet header,followed by a variable number
1189 * of 32-bit character values.
1190 *
1191 * |31 24|23 16|15 8|7 0|
1192 * |-----------------------------------------------------------|
1193 * | | | | msg type |
1194 * |-----------------------------------------------------------|
1195 * | payload |
1196 * |-----------------------------------------------------------|
1197 * - MSG_TYPE
1198 * Bits 7:0
1199 * Purpose: identifies this as a test message
1200 * Value: HTT_MSG_TYPE_PACKETLOG
1201 */
1202 struct htt_pktlog_msg {
1203 u8 pad[3];
1204 u8 payload[];
1205 } __packed;
1206
1207 struct htt_dbg_stats_rx_reorder_stats {
1208 /* Non QoS MPDUs received */
1209 __le32 deliver_non_qos;
1210
1211 /* MPDUs received in-order */
1212 __le32 deliver_in_order;
1213
1214 /* Flush due to reorder timer expired */
1215 __le32 deliver_flush_timeout;
1216
1217 /* Flush due to move out of window */
1218 __le32 deliver_flush_oow;
1219
1220 /* Flush due to DELBA */
1221 __le32 deliver_flush_delba;
1222
1223 /* MPDUs dropped due to FCS error */
1224 __le32 fcs_error;
1225
1226 /* MPDUs dropped due to monitor mode non-data packet */
1227 __le32 mgmt_ctrl;
1228
1229 /* MPDUs dropped due to invalid peer */
1230 __le32 invalid_peer;
1231
1232 /* MPDUs dropped due to duplication (non aggregation) */
1233 __le32 dup_non_aggr;
1234
1235 /* MPDUs dropped due to processed before */
1236 __le32 dup_past;
1237
1238 /* MPDUs dropped due to duplicate in reorder queue */
1239 __le32 dup_in_reorder;
1240
1241 /* Reorder timeout happened */
1242 __le32 reorder_timeout;
1243
1244 /* invalid bar ssn */
1245 __le32 invalid_bar_ssn;
1246
1247 /* reorder reset due to bar ssn */
1248 __le32 ssn_reset;
1249 };
1250
1251 struct htt_dbg_stats_wal_tx_stats {
1252 /* Num HTT cookies queued to dispatch list */
1253 __le32 comp_queued;
1254
1255 /* Num HTT cookies dispatched */
1256 __le32 comp_delivered;
1257
1258 /* Num MSDU queued to WAL */
1259 __le32 msdu_enqued;
1260
1261 /* Num MPDU queue to WAL */
1262 __le32 mpdu_enqued;
1263
1264 /* Num MSDUs dropped by WMM limit */
1265 __le32 wmm_drop;
1266
1267 /* Num Local frames queued */
1268 __le32 local_enqued;
1269
1270 /* Num Local frames done */
1271 __le32 local_freed;
1272
1273 /* Num queued to HW */
1274 __le32 hw_queued;
1275
1276 /* Num PPDU reaped from HW */
1277 __le32 hw_reaped;
1278
1279 /* Num underruns */
1280 __le32 underrun;
1281
1282 /* Num PPDUs cleaned up in TX abort */
1283 __le32 tx_abort;
1284
1285 /* Num MPDUs requed by SW */
1286 __le32 mpdus_requed;
1287
1288 /* excessive retries */
1289 __le32 tx_ko;
1290
1291 /* data hw rate code */
1292 __le32 data_rc;
1293
1294 /* Scheduler self triggers */
1295 __le32 self_triggers;
1296
1297 /* frames dropped due to excessive sw retries */
1298 __le32 sw_retry_failure;
1299
1300 /* illegal rate phy errors */
1301 __le32 illgl_rate_phy_err;
1302
1303 /* wal pdev continuous xretry */
1304 __le32 pdev_cont_xretry;
1305
1306 /* wal pdev continuous xretry */
1307 __le32 pdev_tx_timeout;
1308
1309 /* wal pdev resets */
1310 __le32 pdev_resets;
1311
1312 __le32 phy_underrun;
1313
1314 /* MPDU is more than txop limit */
1315 __le32 txop_ovf;
1316 } __packed;
1317
1318 struct htt_dbg_stats_wal_rx_stats {
1319 /* Cnts any change in ring routing mid-ppdu */
1320 __le32 mid_ppdu_route_change;
1321
1322 /* Total number of statuses processed */
1323 __le32 status_rcvd;
1324
1325 /* Extra frags on rings 0-3 */
1326 __le32 r0_frags;
1327 __le32 r1_frags;
1328 __le32 r2_frags;
1329 __le32 r3_frags;
1330
1331 /* MSDUs / MPDUs delivered to HTT */
1332 __le32 htt_msdus;
1333 __le32 htt_mpdus;
1334
1335 /* MSDUs / MPDUs delivered to local stack */
1336 __le32 loc_msdus;
1337 __le32 loc_mpdus;
1338
1339 /* AMSDUs that have more MSDUs than the status ring size */
1340 __le32 oversize_amsdu;
1341
1342 /* Number of PHY errors */
1343 __le32 phy_errs;
1344
1345 /* Number of PHY errors drops */
1346 __le32 phy_err_drop;
1347
1348 /* Number of mpdu errors - FCS, MIC, ENC etc. */
1349 __le32 mpdu_errs;
1350 } __packed;
1351
1352 struct htt_dbg_stats_wal_peer_stats {
1353 __le32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */
1354 } __packed;
1355
1356 struct htt_dbg_stats_wal_pdev_txrx {
1357 struct htt_dbg_stats_wal_tx_stats tx_stats;
1358 struct htt_dbg_stats_wal_rx_stats rx_stats;
1359 struct htt_dbg_stats_wal_peer_stats peer_stats;
1360 } __packed;
1361
1362 struct htt_dbg_stats_rx_rate_info {
1363 __le32 mcs[10];
1364 __le32 sgi[10];
1365 __le32 nss[4];
1366 __le32 stbc[10];
1367 __le32 bw[3];
1368 __le32 pream[6];
1369 __le32 ldpc;
1370 __le32 txbf;
1371 };
1372
1373 /*
1374 * htt_dbg_stats_status -
1375 * present - The requested stats have been delivered in full.
1376 * This indicates that either the stats information was contained
1377 * in its entirety within this message, or else this message
1378 * completes the delivery of the requested stats info that was
1379 * partially delivered through earlier STATS_CONF messages.
1380 * partial - The requested stats have been delivered in part.
1381 * One or more subsequent STATS_CONF messages with the same
1382 * cookie value will be sent to deliver the remainder of the
1383 * information.
1384 * error - The requested stats could not be delivered, for example due
1385 * to a shortage of memory to construct a message holding the
1386 * requested stats.
1387 * invalid - The requested stat type is either not recognized, or the
1388 * target is configured to not gather the stats type in question.
1389 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1390 * series_done - This special value indicates that no further stats info
1391 * elements are present within a series of stats info elems
1392 * (within a stats upload confirmation message).
1393 */
1394 enum htt_dbg_stats_status {
1395 HTT_DBG_STATS_STATUS_PRESENT = 0,
1396 HTT_DBG_STATS_STATUS_PARTIAL = 1,
1397 HTT_DBG_STATS_STATUS_ERROR = 2,
1398 HTT_DBG_STATS_STATUS_INVALID = 3,
1399 HTT_DBG_STATS_STATUS_SERIES_DONE = 7
1400 };
1401
1402 /*
1403 * target -> host statistics upload
1404 *
1405 * The following field definitions describe the format of the HTT target
1406 * to host stats upload confirmation message.
1407 * The message contains a cookie echoed from the HTT host->target stats
1408 * upload request, which identifies which request the confirmation is
1409 * for, and a series of tag-length-value stats information elements.
1410 * The tag-length header for each stats info element also includes a
1411 * status field, to indicate whether the request for the stat type in
1412 * question was fully met, partially met, unable to be met, or invalid
1413 * (if the stat type in question is disabled in the target).
1414 * A special value of all 1's in this status field is used to indicate
1415 * the end of the series of stats info elements.
1416 *
1417 *
1418 * |31 16|15 8|7 5|4 0|
1419 * |------------------------------------------------------------|
1420 * | reserved | msg type |
1421 * |------------------------------------------------------------|
1422 * | cookie LSBs |
1423 * |------------------------------------------------------------|
1424 * | cookie MSBs |
1425 * |------------------------------------------------------------|
1426 * | stats entry length | reserved | S |stat type|
1427 * |------------------------------------------------------------|
1428 * | |
1429 * | type-specific stats info |
1430 * | |
1431 * |------------------------------------------------------------|
1432 * | stats entry length | reserved | S |stat type|
1433 * |------------------------------------------------------------|
1434 * | |
1435 * | type-specific stats info |
1436 * | |
1437 * |------------------------------------------------------------|
1438 * | n/a | reserved | 111 | n/a |
1439 * |------------------------------------------------------------|
1440 * Header fields:
1441 * - MSG_TYPE
1442 * Bits 7:0
1443 * Purpose: identifies this is a statistics upload confirmation message
1444 * Value: 0x9
1445 * - COOKIE_LSBS
1446 * Bits 31:0
1447 * Purpose: Provide a mechanism to match a target->host stats confirmation
1448 * message with its preceding host->target stats request message.
1449 * Value: LSBs of the opaque cookie specified by the host-side requestor
1450 * - COOKIE_MSBS
1451 * Bits 31:0
1452 * Purpose: Provide a mechanism to match a target->host stats confirmation
1453 * message with its preceding host->target stats request message.
1454 * Value: MSBs of the opaque cookie specified by the host-side requestor
1455 *
1456 * Stats Information Element tag-length header fields:
1457 * - STAT_TYPE
1458 * Bits 4:0
1459 * Purpose: identifies the type of statistics info held in the
1460 * following information element
1461 * Value: htt_dbg_stats_type
1462 * - STATUS
1463 * Bits 7:5
1464 * Purpose: indicate whether the requested stats are present
1465 * Value: htt_dbg_stats_status, including a special value (0x7) to mark
1466 * the completion of the stats entry series
1467 * - LENGTH
1468 * Bits 31:16
1469 * Purpose: indicate the stats information size
1470 * Value: This field specifies the number of bytes of stats information
1471 * that follows the element tag-length header.
1472 * It is expected but not required that this length is a multiple of
1473 * 4 bytes. Even if the length is not an integer multiple of 4, the
1474 * subsequent stats entry header will begin on a 4-byte aligned
1475 * boundary.
1476 */
1477
1478 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_MASK 0x1F
1479 #define HTT_STATS_CONF_ITEM_INFO_STAT_TYPE_LSB 0
1480 #define HTT_STATS_CONF_ITEM_INFO_STATUS_MASK 0xE0
1481 #define HTT_STATS_CONF_ITEM_INFO_STATUS_LSB 5
1482
1483 struct htt_stats_conf_item {
1484 union {
1485 u8 info;
1486 struct {
1487 u8 stat_type:5; /* %HTT_DBG_STATS_ */
1488 u8 status:3; /* %HTT_DBG_STATS_STATUS_ */
1489 } __packed;
1490 } __packed;
1491 u8 pad;
1492 __le16 length;
1493 u8 payload[]; /* roundup(length, 4) long */
1494 } __packed;
1495
1496 struct htt_stats_conf {
1497 u8 pad[3];
1498 __le32 cookie_lsb;
1499 __le32 cookie_msb;
1500
1501 /* each item has variable length! */
1502 struct htt_stats_conf_item items[];
1503 } __packed;
1504
1505 static inline struct htt_stats_conf_item *htt_stats_conf_next_item(
1506 const struct htt_stats_conf_item *item)
1507 {
1508 return (void *)item + sizeof(*item) + roundup(item->length, 4);
1509 }
1510
1511 /*
1512 * host -> target FRAG DESCRIPTOR/MSDU_EXT DESC bank
1513 *
1514 * The following field definitions describe the format of the HTT host
1515 * to target frag_desc/msdu_ext bank configuration message.
1516 * The message contains the based address and the min and max id of the
1517 * MSDU_EXT/FRAG_DESC that will be used by the HTT to map MSDU DESC and
1518 * MSDU_EXT/FRAG_DESC.
1519 * HTT will use id in HTT descriptor instead sending the frag_desc_ptr.
1520 * For QCA988X HW the firmware will use fragment_desc_ptr but in WIFI2.0
1521 * the hardware does the mapping/translation.
1522 *
1523 * Total banks that can be configured is configured to 16.
1524 *
1525 * This should be called before any TX has be initiated by the HTT
1526 *
1527 * |31 16|15 8|7 5|4 0|
1528 * |------------------------------------------------------------|
1529 * | DESC_SIZE | NUM_BANKS | RES |SWP|pdev| msg type |
1530 * |------------------------------------------------------------|
1531 * | BANK0_BASE_ADDRESS |
1532 * |------------------------------------------------------------|
1533 * | ... |
1534 * |------------------------------------------------------------|
1535 * | BANK15_BASE_ADDRESS |
1536 * |------------------------------------------------------------|
1537 * | BANK0_MAX_ID | BANK0_MIN_ID |
1538 * |------------------------------------------------------------|
1539 * | ... |
1540 * |------------------------------------------------------------|
1541 * | BANK15_MAX_ID | BANK15_MIN_ID |
1542 * |------------------------------------------------------------|
1543 * Header fields:
1544 * - MSG_TYPE
1545 * Bits 7:0
1546 * Value: 0x6
1547 * - BANKx_BASE_ADDRESS
1548 * Bits 31:0
1549 * Purpose: Provide a mechanism to specify the base address of the MSDU_EXT
1550 * bank physical/bus address.
1551 * - BANKx_MIN_ID
1552 * Bits 15:0
1553 * Purpose: Provide a mechanism to specify the min index that needs to
1554 * mapped.
1555 * - BANKx_MAX_ID
1556 * Bits 31:16
1557 * Purpose: Provide a mechanism to specify the max index that needs to
1558 *
1559 */
1560 struct htt_frag_desc_bank_id {
1561 __le16 bank_min_id;
1562 __le16 bank_max_id;
1563 } __packed;
1564
1565 /* real is 16 but it wouldn't fit in the max htt message size
1566 * so we use a conservatively safe value for now
1567 */
1568 #define HTT_FRAG_DESC_BANK_MAX 4
1569
1570 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_MASK 0x03
1571 #define HTT_FRAG_DESC_BANK_CFG_INFO_PDEV_ID_LSB 0
1572 #define HTT_FRAG_DESC_BANK_CFG_INFO_SWAP BIT(2)
1573 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_VALID BIT(3)
1574 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_MASK BIT(4)
1575 #define HTT_FRAG_DESC_BANK_CFG_INFO_Q_STATE_DEPTH_TYPE_LSB 4
1576
1577 enum htt_q_depth_type {
1578 HTT_Q_DEPTH_TYPE_BYTES = 0,
1579 HTT_Q_DEPTH_TYPE_MSDUS = 1,
1580 };
1581
1582 #define HTT_TX_Q_STATE_NUM_PEERS (TARGET_10_4_NUM_QCACHE_PEERS_MAX + \
1583 TARGET_10_4_NUM_VDEVS)
1584 #define HTT_TX_Q_STATE_NUM_TIDS 8
1585 #define HTT_TX_Q_STATE_ENTRY_SIZE 1
1586 #define HTT_TX_Q_STATE_ENTRY_MULTIPLIER 0
1587
1588 /**
1589 * htt_q_state_conf - part of htt_frag_desc_bank_cfg for host q state config
1590 *
1591 * Defines host q state format and behavior. See htt_q_state.
1592 *
1593 * @record_size: Defines the size of each host q entry in bytes. In practice
1594 * however firmware (at least 10.4.3-00191) ignores this host
1595 * configuration value and uses hardcoded value of 1.
1596 * @record_multiplier: This is valid only when q depth type is MSDUs. It
1597 * defines the exponent for the power of 2 multiplication.
1598 */
1599 struct htt_q_state_conf {
1600 __le32 paddr;
1601 __le16 num_peers;
1602 __le16 num_tids;
1603 u8 record_size;
1604 u8 record_multiplier;
1605 u8 pad[2];
1606 } __packed;
1607
1608 struct htt_frag_desc_bank_cfg32 {
1609 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1610 u8 num_banks;
1611 u8 desc_size;
1612 __le32 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1613 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1614 struct htt_q_state_conf q_state;
1615 } __packed;
1616
1617 struct htt_frag_desc_bank_cfg64 {
1618 u8 info; /* HTT_FRAG_DESC_BANK_CFG_INFO_ */
1619 u8 num_banks;
1620 u8 desc_size;
1621 __le64 bank_base_addrs[HTT_FRAG_DESC_BANK_MAX];
1622 struct htt_frag_desc_bank_id bank_id[HTT_FRAG_DESC_BANK_MAX];
1623 struct htt_q_state_conf q_state;
1624 } __packed;
1625
1626 #define HTT_TX_Q_STATE_ENTRY_COEFFICIENT 128
1627 #define HTT_TX_Q_STATE_ENTRY_FACTOR_MASK 0x3f
1628 #define HTT_TX_Q_STATE_ENTRY_FACTOR_LSB 0
1629 #define HTT_TX_Q_STATE_ENTRY_EXP_MASK 0xc0
1630 #define HTT_TX_Q_STATE_ENTRY_EXP_LSB 6
1631
1632 /**
1633 * htt_q_state - shared between host and firmware via DMA
1634 *
1635 * This structure is used for the host to expose it's software queue state to
1636 * firmware so that its rate control can schedule fetch requests for optimized
1637 * performance. This is most notably used for MU-MIMO aggregation when multiple
1638 * MU clients are connected.
1639 *
1640 * @count: Each element defines the host queue depth. When q depth type was
1641 * configured as HTT_Q_DEPTH_TYPE_BYTES then each entry is defined as:
1642 * FACTOR * 128 * 8^EXP (see HTT_TX_Q_STATE_ENTRY_FACTOR_MASK and
1643 * HTT_TX_Q_STATE_ENTRY_EXP_MASK). When q depth type was configured as
1644 * HTT_Q_DEPTH_TYPE_MSDUS the number of packets is scaled by 2 **
1645 * record_multiplier (see htt_q_state_conf).
1646 * @map: Used by firmware to quickly check which host queues are not empty. It
1647 * is a bitmap simply saying.
1648 * @seq: Used by firmware to quickly check if the host queues were updated
1649 * since it last checked.
1650 *
1651 * FIXME: Is the q_state map[] size calculation really correct?
1652 */
1653 struct htt_q_state {
1654 u8 count[HTT_TX_Q_STATE_NUM_TIDS][HTT_TX_Q_STATE_NUM_PEERS];
1655 u32 map[HTT_TX_Q_STATE_NUM_TIDS][(HTT_TX_Q_STATE_NUM_PEERS + 31) / 32];
1656 __le32 seq;
1657 } __packed;
1658
1659 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_MASK 0x0fff
1660 #define HTT_TX_FETCH_RECORD_INFO_PEER_ID_LSB 0
1661 #define HTT_TX_FETCH_RECORD_INFO_TID_MASK 0xf000
1662 #define HTT_TX_FETCH_RECORD_INFO_TID_LSB 12
1663
1664 struct htt_tx_fetch_record {
1665 __le16 info; /* HTT_TX_FETCH_IND_RECORD_INFO_ */
1666 __le16 num_msdus;
1667 __le32 num_bytes;
1668 } __packed;
1669
1670 struct htt_tx_fetch_ind {
1671 u8 pad0;
1672 __le16 fetch_seq_num;
1673 __le32 token;
1674 __le16 num_resp_ids;
1675 __le16 num_records;
1676 __le32 resp_ids[0]; /* ath10k_htt_get_tx_fetch_ind_resp_ids() */
1677 struct htt_tx_fetch_record records[];
1678 } __packed;
1679
1680 static inline void *
1681 ath10k_htt_get_tx_fetch_ind_resp_ids(struct htt_tx_fetch_ind *ind)
1682 {
1683 return (void *)&ind->records[le16_to_cpu(ind->num_records)];
1684 }
1685
1686 struct htt_tx_fetch_resp {
1687 u8 pad0;
1688 __le16 resp_id;
1689 __le16 fetch_seq_num;
1690 __le16 num_records;
1691 __le32 token;
1692 struct htt_tx_fetch_record records[];
1693 } __packed;
1694
1695 struct htt_tx_fetch_confirm {
1696 u8 pad0;
1697 __le16 num_resp_ids;
1698 __le32 resp_ids[];
1699 } __packed;
1700
1701 enum htt_tx_mode_switch_mode {
1702 HTT_TX_MODE_SWITCH_PUSH = 0,
1703 HTT_TX_MODE_SWITCH_PUSH_PULL = 1,
1704 };
1705
1706 #define HTT_TX_MODE_SWITCH_IND_INFO0_ENABLE BIT(0)
1707 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_MASK 0xfffe
1708 #define HTT_TX_MODE_SWITCH_IND_INFO0_NUM_RECORDS_LSB 1
1709
1710 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_MASK 0x0003
1711 #define HTT_TX_MODE_SWITCH_IND_INFO1_MODE_LSB 0
1712 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_MASK 0xfffc
1713 #define HTT_TX_MODE_SWITCH_IND_INFO1_THRESHOLD_LSB 2
1714
1715 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_MASK 0x0fff
1716 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_PEER_ID_LSB 0
1717 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_MASK 0xf000
1718 #define HTT_TX_MODE_SWITCH_RECORD_INFO0_TID_LSB 12
1719
1720 struct htt_tx_mode_switch_record {
1721 __le16 info0; /* HTT_TX_MODE_SWITCH_RECORD_INFO0_ */
1722 __le16 num_max_msdus;
1723 } __packed;
1724
1725 struct htt_tx_mode_switch_ind {
1726 u8 pad0;
1727 __le16 info0; /* HTT_TX_MODE_SWITCH_IND_INFO0_ */
1728 __le16 info1; /* HTT_TX_MODE_SWITCH_IND_INFO1_ */
1729 u8 pad1[2];
1730 struct htt_tx_mode_switch_record records[];
1731 } __packed;
1732
1733 struct htt_channel_change {
1734 u8 pad[3];
1735 __le32 freq;
1736 __le32 center_freq1;
1737 __le32 center_freq2;
1738 __le32 phymode;
1739 } __packed;
1740
1741 struct htt_per_peer_tx_stats_ind {
1742 __le32 succ_bytes;
1743 __le32 retry_bytes;
1744 __le32 failed_bytes;
1745 u8 ratecode;
1746 u8 flags;
1747 __le16 peer_id;
1748 __le16 succ_pkts;
1749 __le16 retry_pkts;
1750 __le16 failed_pkts;
1751 __le16 tx_duration;
1752 __le32 reserved1;
1753 __le32 reserved2;
1754 } __packed;
1755
1756 struct htt_peer_tx_stats {
1757 u8 num_ppdu;
1758 u8 ppdu_len;
1759 u8 version;
1760 u8 payload[];
1761 } __packed;
1762
1763 #define ATH10K_10_2_TX_STATS_OFFSET 136
1764 #define PEER_STATS_FOR_NO_OF_PPDUS 4
1765
1766 struct ath10k_10_2_peer_tx_stats {
1767 u8 ratecode[PEER_STATS_FOR_NO_OF_PPDUS];
1768 u8 success_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1769 __le16 success_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1770 u8 retry_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1771 __le16 retry_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1772 u8 failed_pkts[PEER_STATS_FOR_NO_OF_PPDUS];
1773 __le16 failed_bytes[PEER_STATS_FOR_NO_OF_PPDUS];
1774 u8 flags[PEER_STATS_FOR_NO_OF_PPDUS];
1775 __le32 tx_duration;
1776 u8 tx_ppdu_cnt;
1777 u8 peer_id;
1778 } __packed;
1779
1780 union htt_rx_pn_t {
1781 /* WEP: 24-bit PN */
1782 u32 pn24;
1783
1784 /* TKIP or CCMP: 48-bit PN */
1785 u64 pn48;
1786
1787 /* WAPI: 128-bit PN */
1788 u64 pn128[2];
1789 };
1790
1791 struct htt_cmd {
1792 struct htt_cmd_hdr hdr;
1793 union {
1794 struct htt_ver_req ver_req;
1795 struct htt_mgmt_tx_desc mgmt_tx;
1796 struct htt_data_tx_desc data_tx;
1797 struct htt_rx_ring_setup_32 rx_setup_32;
1798 struct htt_rx_ring_setup_64 rx_setup_64;
1799 struct htt_stats_req stats_req;
1800 struct htt_oob_sync_req oob_sync_req;
1801 struct htt_aggr_conf aggr_conf;
1802 struct htt_aggr_conf_v2 aggr_conf_v2;
1803 struct htt_frag_desc_bank_cfg32 frag_desc_bank_cfg32;
1804 struct htt_frag_desc_bank_cfg64 frag_desc_bank_cfg64;
1805 struct htt_tx_fetch_resp tx_fetch_resp;
1806 };
1807 } __packed;
1808
1809 struct htt_resp {
1810 struct htt_resp_hdr hdr;
1811 union {
1812 struct htt_ver_resp ver_resp;
1813 struct htt_mgmt_tx_completion mgmt_tx_completion;
1814 struct htt_data_tx_completion data_tx_completion;
1815 struct htt_rx_indication rx_ind;
1816 struct htt_rx_indication_hl rx_ind_hl;
1817 struct htt_rx_fragment_indication rx_frag_ind;
1818 struct htt_rx_peer_map peer_map;
1819 struct htt_rx_peer_unmap peer_unmap;
1820 struct htt_rx_flush rx_flush;
1821 struct htt_rx_addba rx_addba;
1822 struct htt_rx_delba rx_delba;
1823 struct htt_security_indication security_indication;
1824 struct htt_rc_update rc_update;
1825 struct htt_rx_test rx_test;
1826 struct htt_pktlog_msg pktlog_msg;
1827 struct htt_stats_conf stats_conf;
1828 struct htt_rx_pn_ind rx_pn_ind;
1829 struct htt_rx_offload_ind rx_offload_ind;
1830 struct htt_rx_in_ord_ind rx_in_ord_ind;
1831 struct htt_tx_fetch_ind tx_fetch_ind;
1832 struct htt_tx_fetch_confirm tx_fetch_confirm;
1833 struct htt_tx_mode_switch_ind tx_mode_switch_ind;
1834 struct htt_channel_change chan_change;
1835 struct htt_peer_tx_stats peer_tx_stats;
1836 };
1837 } __packed;
1838
1839 /*** host side structures follow ***/
1840
1841 struct htt_tx_done {
1842 u16 msdu_id;
1843 u16 status;
1844 u8 ack_rssi;
1845 };
1846
1847 enum htt_tx_compl_state {
1848 HTT_TX_COMPL_STATE_NONE,
1849 HTT_TX_COMPL_STATE_ACK,
1850 HTT_TX_COMPL_STATE_NOACK,
1851 HTT_TX_COMPL_STATE_DISCARD,
1852 };
1853
1854 struct htt_peer_map_event {
1855 u8 vdev_id;
1856 u16 peer_id;
1857 u8 addr[ETH_ALEN];
1858 };
1859
1860 struct htt_peer_unmap_event {
1861 u16 peer_id;
1862 };
1863
1864 struct ath10k_htt_txbuf_32 {
1865 struct htt_data_tx_desc_frag frags[2];
1866 struct ath10k_htc_hdr htc_hdr;
1867 struct htt_cmd_hdr cmd_hdr;
1868 struct htt_data_tx_desc cmd_tx;
1869 } __packed __aligned(4);
1870
1871 struct ath10k_htt_txbuf_64 {
1872 struct htt_data_tx_desc_frag frags[2];
1873 struct ath10k_htc_hdr htc_hdr;
1874 struct htt_cmd_hdr cmd_hdr;
1875 struct htt_data_tx_desc_64 cmd_tx;
1876 } __packed __aligned(4);
1877
1878 struct ath10k_htt {
1879 struct ath10k *ar;
1880 enum ath10k_htc_ep_id eid;
1881
1882 struct sk_buff_head rx_indication_head;
1883
1884 u8 target_version_major;
1885 u8 target_version_minor;
1886 struct completion target_version_received;
1887 u8 max_num_amsdu;
1888 u8 max_num_ampdu;
1889
1890 const enum htt_t2h_msg_type *t2h_msg_types;
1891 u32 t2h_msg_types_max;
1892
1893 struct {
1894 /*
1895 * Ring of network buffer objects - This ring is
1896 * used exclusively by the host SW. This ring
1897 * mirrors the dev_addrs_ring that is shared
1898 * between the host SW and the MAC HW. The host SW
1899 * uses this netbufs ring to locate the network
1900 * buffer objects whose data buffers the HW has
1901 * filled.
1902 */
1903 struct sk_buff **netbufs_ring;
1904
1905 /* This is used only with firmware supporting IN_ORD_IND.
1906 *
1907 * With Full Rx Reorder the HTT Rx Ring is more of a temporary
1908 * buffer ring from which buffer addresses are copied by the
1909 * firmware to MAC Rx ring. Firmware then delivers IN_ORD_IND
1910 * pointing to specific (re-ordered) buffers.
1911 *
1912 * FIXME: With kernel generic hashing functions there's a lot
1913 * of hash collisions for sk_buffs.
1914 */
1915 bool in_ord_rx;
1916 DECLARE_HASHTABLE(skb_table, 4);
1917
1918 /*
1919 * Ring of buffer addresses -
1920 * This ring holds the "physical" device address of the
1921 * rx buffers the host SW provides for the MAC HW to
1922 * fill.
1923 */
1924 union {
1925 __le64 *paddrs_ring_64;
1926 __le32 *paddrs_ring_32;
1927 };
1928
1929 /*
1930 * Base address of ring, as a "physical" device address
1931 * rather than a CPU address.
1932 */
1933 dma_addr_t base_paddr;
1934
1935 /* how many elems in the ring (power of 2) */
1936 int size;
1937
1938 /* size - 1 */
1939 unsigned int size_mask;
1940
1941 /* how many rx buffers to keep in the ring */
1942 int fill_level;
1943
1944 /* how many rx buffers (full+empty) are in the ring */
1945 int fill_cnt;
1946
1947 /*
1948 * alloc_idx - where HTT SW has deposited empty buffers
1949 * This is allocated in consistent mem, so that the FW can
1950 * read this variable, and program the HW's FW_IDX reg with
1951 * the value of this shadow register.
1952 */
1953 struct {
1954 __le32 *vaddr;
1955 dma_addr_t paddr;
1956 } alloc_idx;
1957
1958 /* where HTT SW has processed bufs filled by rx MAC DMA */
1959 struct {
1960 unsigned int msdu_payld;
1961 } sw_rd_idx;
1962
1963 /*
1964 * refill_retry_timer - timer triggered when the ring is
1965 * not refilled to the level expected
1966 */
1967 struct timer_list refill_retry_timer;
1968
1969 /* Protects access to all rx ring buffer state variables */
1970 spinlock_t lock;
1971 } rx_ring;
1972
1973 unsigned int prefetch_len;
1974
1975 /* Protects access to pending_tx, num_pending_tx */
1976 spinlock_t tx_lock;
1977 int max_num_pending_tx;
1978 int num_pending_tx;
1979 int num_pending_mgmt_tx;
1980 struct idr pending_tx;
1981 wait_queue_head_t empty_tx_wq;
1982
1983 /* FIFO for storing tx done status {ack, no-ack, discard} and msdu id */
1984 DECLARE_KFIFO_PTR(txdone_fifo, struct htt_tx_done);
1985
1986 /* set if host-fw communication goes haywire
1987 * used to avoid further failures
1988 */
1989 bool rx_confused;
1990 atomic_t num_mpdus_ready;
1991
1992 /* This is used to group tx/rx completions separately and process them
1993 * in batches to reduce cache stalls
1994 */
1995 struct sk_buff_head rx_msdus_q;
1996 struct sk_buff_head rx_in_ord_compl_q;
1997 struct sk_buff_head tx_fetch_ind_q;
1998
1999 /* rx_status template */
2000 struct ieee80211_rx_status rx_status;
2001
2002 struct {
2003 dma_addr_t paddr;
2004 union {
2005 struct htt_msdu_ext_desc *vaddr_desc_32;
2006 struct htt_msdu_ext_desc_64 *vaddr_desc_64;
2007 };
2008 size_t size;
2009 } frag_desc;
2010
2011 struct {
2012 dma_addr_t paddr;
2013 union {
2014 struct ath10k_htt_txbuf_32 *vaddr_txbuff_32;
2015 struct ath10k_htt_txbuf_64 *vaddr_txbuff_64;
2016 };
2017 size_t size;
2018 } txbuf;
2019
2020 struct {
2021 bool enabled;
2022 struct htt_q_state *vaddr;
2023 dma_addr_t paddr;
2024 u16 num_push_allowed;
2025 u16 num_peers;
2026 u16 num_tids;
2027 enum htt_tx_mode_switch_mode mode;
2028 enum htt_q_depth_type type;
2029 } tx_q_state;
2030
2031 bool tx_mem_allocated;
2032 const struct ath10k_htt_tx_ops *tx_ops;
2033 const struct ath10k_htt_rx_ops *rx_ops;
2034 bool disable_tx_comp;
2035 bool bundle_tx;
2036 struct sk_buff_head tx_req_head;
2037 struct sk_buff_head tx_complete_head;
2038 };
2039
2040 struct ath10k_htt_tx_ops {
2041 int (*htt_send_rx_ring_cfg)(struct ath10k_htt *htt);
2042 int (*htt_send_frag_desc_bank_cfg)(struct ath10k_htt *htt);
2043 int (*htt_alloc_frag_desc)(struct ath10k_htt *htt);
2044 void (*htt_free_frag_desc)(struct ath10k_htt *htt);
2045 int (*htt_tx)(struct ath10k_htt *htt, enum ath10k_hw_txrx_mode txmode,
2046 struct sk_buff *msdu);
2047 int (*htt_alloc_txbuff)(struct ath10k_htt *htt);
2048 void (*htt_free_txbuff)(struct ath10k_htt *htt);
2049 int (*htt_h2t_aggr_cfg_msg)(struct ath10k_htt *htt,
2050 u8 max_subfrms_ampdu,
2051 u8 max_subfrms_amsdu);
2052 void (*htt_flush_tx)(struct ath10k_htt *htt);
2053 };
2054
2055 static inline int ath10k_htt_send_rx_ring_cfg(struct ath10k_htt *htt)
2056 {
2057 if (!htt->tx_ops->htt_send_rx_ring_cfg)
2058 return -EOPNOTSUPP;
2059
2060 return htt->tx_ops->htt_send_rx_ring_cfg(htt);
2061 }
2062
2063 static inline int ath10k_htt_send_frag_desc_bank_cfg(struct ath10k_htt *htt)
2064 {
2065 if (!htt->tx_ops->htt_send_frag_desc_bank_cfg)
2066 return -EOPNOTSUPP;
2067
2068 return htt->tx_ops->htt_send_frag_desc_bank_cfg(htt);
2069 }
2070
2071 static inline int ath10k_htt_alloc_frag_desc(struct ath10k_htt *htt)
2072 {
2073 if (!htt->tx_ops->htt_alloc_frag_desc)
2074 return -EOPNOTSUPP;
2075
2076 return htt->tx_ops->htt_alloc_frag_desc(htt);
2077 }
2078
2079 static inline void ath10k_htt_free_frag_desc(struct ath10k_htt *htt)
2080 {
2081 if (htt->tx_ops->htt_free_frag_desc)
2082 htt->tx_ops->htt_free_frag_desc(htt);
2083 }
2084
2085 static inline int ath10k_htt_tx(struct ath10k_htt *htt,
2086 enum ath10k_hw_txrx_mode txmode,
2087 struct sk_buff *msdu)
2088 {
2089 return htt->tx_ops->htt_tx(htt, txmode, msdu);
2090 }
2091
2092 static inline void ath10k_htt_flush_tx(struct ath10k_htt *htt)
2093 {
2094 if (htt->tx_ops->htt_flush_tx)
2095 htt->tx_ops->htt_flush_tx(htt);
2096 }
2097
2098 static inline int ath10k_htt_alloc_txbuff(struct ath10k_htt *htt)
2099 {
2100 if (!htt->tx_ops->htt_alloc_txbuff)
2101 return -EOPNOTSUPP;
2102
2103 return htt->tx_ops->htt_alloc_txbuff(htt);
2104 }
2105
2106 static inline void ath10k_htt_free_txbuff(struct ath10k_htt *htt)
2107 {
2108 if (htt->tx_ops->htt_free_txbuff)
2109 htt->tx_ops->htt_free_txbuff(htt);
2110 }
2111
2112 static inline int ath10k_htt_h2t_aggr_cfg_msg(struct ath10k_htt *htt,
2113 u8 max_subfrms_ampdu,
2114 u8 max_subfrms_amsdu)
2115
2116 {
2117 if (!htt->tx_ops->htt_h2t_aggr_cfg_msg)
2118 return -EOPNOTSUPP;
2119
2120 return htt->tx_ops->htt_h2t_aggr_cfg_msg(htt,
2121 max_subfrms_ampdu,
2122 max_subfrms_amsdu);
2123 }
2124
2125 struct ath10k_htt_rx_ops {
2126 size_t (*htt_get_rx_ring_size)(struct ath10k_htt *htt);
2127 void (*htt_config_paddrs_ring)(struct ath10k_htt *htt, void *vaddr);
2128 void (*htt_set_paddrs_ring)(struct ath10k_htt *htt, dma_addr_t paddr,
2129 int idx);
2130 void* (*htt_get_vaddr_ring)(struct ath10k_htt *htt);
2131 void (*htt_reset_paddrs_ring)(struct ath10k_htt *htt, int idx);
2132 bool (*htt_rx_proc_rx_frag_ind)(struct ath10k_htt *htt,
2133 struct htt_rx_fragment_indication *rx,
2134 struct sk_buff *skb);
2135 };
2136
2137 static inline size_t ath10k_htt_get_rx_ring_size(struct ath10k_htt *htt)
2138 {
2139 if (!htt->rx_ops->htt_get_rx_ring_size)
2140 return 0;
2141
2142 return htt->rx_ops->htt_get_rx_ring_size(htt);
2143 }
2144
2145 static inline void ath10k_htt_config_paddrs_ring(struct ath10k_htt *htt,
2146 void *vaddr)
2147 {
2148 if (htt->rx_ops->htt_config_paddrs_ring)
2149 htt->rx_ops->htt_config_paddrs_ring(htt, vaddr);
2150 }
2151
2152 static inline void ath10k_htt_set_paddrs_ring(struct ath10k_htt *htt,
2153 dma_addr_t paddr,
2154 int idx)
2155 {
2156 if (htt->rx_ops->htt_set_paddrs_ring)
2157 htt->rx_ops->htt_set_paddrs_ring(htt, paddr, idx);
2158 }
2159
2160 static inline void *ath10k_htt_get_vaddr_ring(struct ath10k_htt *htt)
2161 {
2162 if (!htt->rx_ops->htt_get_vaddr_ring)
2163 return NULL;
2164
2165 return htt->rx_ops->htt_get_vaddr_ring(htt);
2166 }
2167
2168 static inline void ath10k_htt_reset_paddrs_ring(struct ath10k_htt *htt, int idx)
2169 {
2170 if (htt->rx_ops->htt_reset_paddrs_ring)
2171 htt->rx_ops->htt_reset_paddrs_ring(htt, idx);
2172 }
2173
2174 static inline bool ath10k_htt_rx_proc_rx_frag_ind(struct ath10k_htt *htt,
2175 struct htt_rx_fragment_indication *rx,
2176 struct sk_buff *skb)
2177 {
2178 if (!htt->rx_ops->htt_rx_proc_rx_frag_ind)
2179 return true;
2180
2181 return htt->rx_ops->htt_rx_proc_rx_frag_ind(htt, rx, skb);
2182 }
2183
2184 #define RX_HTT_HDR_STATUS_LEN 64
2185
2186 /* This structure layout is programmed via rx ring setup
2187 * so that FW knows how to transfer the rx descriptor to the host.
2188 * Buffers like this are placed on the rx ring.
2189 */
2190 struct htt_rx_desc {
2191 union {
2192 /* This field is filled on the host using the msdu buffer
2193 * from htt_rx_indication
2194 */
2195 struct fw_rx_desc_base fw_desc;
2196 u32 pad;
2197 } __packed;
2198 struct {
2199 struct rx_attention attention;
2200 struct rx_frag_info frag_info;
2201 struct rx_mpdu_start mpdu_start;
2202 struct rx_msdu_start msdu_start;
2203 struct rx_msdu_end msdu_end;
2204 struct rx_mpdu_end mpdu_end;
2205 struct rx_ppdu_start ppdu_start;
2206 struct rx_ppdu_end ppdu_end;
2207 } __packed;
2208 u8 rx_hdr_status[RX_HTT_HDR_STATUS_LEN];
2209 u8 msdu_payload[];
2210 };
2211
2212 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_MASK 0x00000fff
2213 #define HTT_RX_DESC_HL_INFO_SEQ_NUM_LSB 0
2214 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_MASK 0x00001000
2215 #define HTT_RX_DESC_HL_INFO_ENCRYPTED_LSB 12
2216 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_MASK 0x00002000
2217 #define HTT_RX_DESC_HL_INFO_CHAN_INFO_PRESENT_LSB 13
2218 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_MASK 0x00010000
2219 #define HTT_RX_DESC_HL_INFO_MCAST_BCAST_LSB 16
2220 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_MASK 0x01fe0000
2221 #define HTT_RX_DESC_HL_INFO_KEY_ID_OCT_LSB 17
2222
2223 struct htt_rx_desc_base_hl {
2224 __le32 info; /* HTT_RX_DESC_HL_INFO_ */
2225 };
2226
2227 struct htt_rx_chan_info {
2228 __le16 primary_chan_center_freq_mhz;
2229 __le16 contig_chan1_center_freq_mhz;
2230 __le16 contig_chan2_center_freq_mhz;
2231 u8 phy_mode;
2232 u8 reserved;
2233 } __packed;
2234
2235 #define HTT_RX_DESC_ALIGN 8
2236
2237 #define HTT_MAC_ADDR_LEN 6
2238
2239 /*
2240 * FIX THIS
2241 * Should be: sizeof(struct htt_host_rx_desc) + max rx MSDU size,
2242 * rounded up to a cache line size.
2243 */
2244 #define HTT_RX_BUF_SIZE 1920
2245 #define HTT_RX_MSDU_SIZE (HTT_RX_BUF_SIZE - (int)sizeof(struct htt_rx_desc))
2246
2247 /* Refill a bunch of RX buffers for each refill round so that FW/HW can handle
2248 * aggregated traffic more nicely.
2249 */
2250 #define ATH10K_HTT_MAX_NUM_REFILL 100
2251
2252 /*
2253 * DMA_MAP expects the buffer to be an integral number of cache lines.
2254 * Rather than checking the actual cache line size, this code makes a
2255 * conservative estimate of what the cache line size could be.
2256 */
2257 #define HTT_LOG2_MAX_CACHE_LINE_SIZE 7 /* 2^7 = 128 */
2258 #define HTT_MAX_CACHE_LINE_SIZE_MASK ((1 << HTT_LOG2_MAX_CACHE_LINE_SIZE) - 1)
2259
2260 /* These values are default in most firmware revisions and apparently are a
2261 * sweet spot performance wise.
2262 */
2263 #define ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT 3
2264 #define ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT 64
2265
2266 int ath10k_htt_connect(struct ath10k_htt *htt);
2267 int ath10k_htt_init(struct ath10k *ar);
2268 int ath10k_htt_setup(struct ath10k_htt *htt);
2269
2270 int ath10k_htt_tx_start(struct ath10k_htt *htt);
2271 void ath10k_htt_tx_stop(struct ath10k_htt *htt);
2272 void ath10k_htt_tx_destroy(struct ath10k_htt *htt);
2273 void ath10k_htt_tx_free(struct ath10k_htt *htt);
2274
2275 int ath10k_htt_rx_alloc(struct ath10k_htt *htt);
2276 int ath10k_htt_rx_ring_refill(struct ath10k *ar);
2277 void ath10k_htt_rx_free(struct ath10k_htt *htt);
2278
2279 void ath10k_htt_htc_tx_complete(struct ath10k *ar, struct sk_buff *skb);
2280 void ath10k_htt_htc_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
2281 bool ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb);
2282 int ath10k_htt_h2t_ver_req_msg(struct ath10k_htt *htt);
2283 int ath10k_htt_h2t_stats_req(struct ath10k_htt *htt, u32 mask, u32 reset_mask,
2284 u64 cookie);
2285 void ath10k_htt_hif_tx_complete(struct ath10k *ar, struct sk_buff *skb);
2286 int ath10k_htt_tx_fetch_resp(struct ath10k *ar,
2287 __le32 token,
2288 __le16 fetch_seq_num,
2289 struct htt_tx_fetch_record *records,
2290 size_t num_records);
2291 void ath10k_htt_op_ep_tx_credits(struct ath10k *ar);
2292
2293 void ath10k_htt_tx_txq_update(struct ieee80211_hw *hw,
2294 struct ieee80211_txq *txq);
2295 void ath10k_htt_tx_txq_recalc(struct ieee80211_hw *hw,
2296 struct ieee80211_txq *txq);
2297 void ath10k_htt_tx_txq_sync(struct ath10k *ar);
2298 void ath10k_htt_tx_dec_pending(struct ath10k_htt *htt);
2299 int ath10k_htt_tx_inc_pending(struct ath10k_htt *htt);
2300 void ath10k_htt_tx_mgmt_dec_pending(struct ath10k_htt *htt);
2301 int ath10k_htt_tx_mgmt_inc_pending(struct ath10k_htt *htt, bool is_mgmt,
2302 bool is_presp);
2303
2304 int ath10k_htt_tx_alloc_msdu_id(struct ath10k_htt *htt, struct sk_buff *skb);
2305 void ath10k_htt_tx_free_msdu_id(struct ath10k_htt *htt, u16 msdu_id);
2306 int ath10k_htt_mgmt_tx(struct ath10k_htt *htt, struct sk_buff *msdu);
2307 void ath10k_htt_rx_pktlog_completion_handler(struct ath10k *ar,
2308 struct sk_buff *skb);
2309 int ath10k_htt_txrx_compl_task(struct ath10k *ar, int budget);
2310 int ath10k_htt_rx_hl_indication(struct ath10k *ar, int budget);
2311 void ath10k_htt_set_tx_ops(struct ath10k_htt *htt);
2312 void ath10k_htt_set_rx_ops(struct ath10k_htt *htt);
2313 #endif
Linux with added FPC-III support