drivers/net/wireless/intel/iwlwifi/fw/api/rx.h

   1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
   2 /*
   3  * Copyright (C) 2012-2014, 2018-2020 Intel Corporation
   4  * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
   5  * Copyright (C) 2015-2017 Intel Deutschland GmbH
   6  */
   7 #ifndef __iwl_fw_api_rx_h__
   8 #define __iwl_fw_api_rx_h__
   9
  10 /* API for pre-9000 hardware */
  11
  12 #define IWL_RX_INFO_PHY_CNT 8
  13 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
  14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
  15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
  16 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
  17 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
  18 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8
  19 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16
  20
  21 enum iwl_mac_context_info {
  22         MAC_CONTEXT_INFO_NONE,
  23         MAC_CONTEXT_INFO_GSCAN,
  24 };
  25
  26 /**
  27  * struct iwl_rx_phy_info - phy info
  28  * (REPLY_RX_PHY_CMD = 0xc0)
  29  * @non_cfg_phy_cnt: non configurable DSP phy data byte count
  30  * @cfg_phy_cnt: configurable DSP phy data byte count
  31  * @stat_id: configurable DSP phy data set ID
  32  * @reserved1: reserved
  33  * @system_timestamp: GP2  at on air rise
  34  * @timestamp: TSF at on air rise
  35  * @beacon_time_stamp: beacon at on-air rise
  36  * @phy_flags: general phy flags: band, modulation, ...
  37  * @channel: channel number
  38  * @non_cfg_phy: for various implementations of non_cfg_phy
  39  * @rate_n_flags: RATE_MCS_*
  40  * @byte_count: frame's byte-count
  41  * @frame_time: frame's time on the air, based on byte count and frame rate
  42  *      calculation
  43  * @mac_active_msk: what MACs were active when the frame was received
  44  * @mac_context_info: additional info on the context in which the frame was
  45  *      received as defined in &enum iwl_mac_context_info
  46  *
  47  * Before each Rx, the device sends this data. It contains PHY information
  48  * about the reception of the packet.
  49  */
  50 struct iwl_rx_phy_info {
  51         u8 non_cfg_phy_cnt;
  52         u8 cfg_phy_cnt;
  53         u8 stat_id;
  54         u8 reserved1;
  55         __le32 system_timestamp;
  56         __le64 timestamp;
  57         __le32 beacon_time_stamp;
  58         __le16 phy_flags;
  59         __le16 channel;
  60         __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
  61         __le32 rate_n_flags;
  62         __le32 byte_count;
  63         u8 mac_active_msk;
  64         u8 mac_context_info;
  65         __le16 frame_time;
  66 } __packed;
  67
  68 /*
  69  * TCP offload Rx assist info
  70  *
  71  * bits 0:3 - reserved
  72  * bits 4:7 - MIC CRC length
  73  * bits 8:12 - MAC header length
  74  * bit 13 - Padding indication
  75  * bit 14 - A-AMSDU indication
  76  * bit 15 - Offload enabled
  77  */
  78 enum iwl_csum_rx_assist_info {
  79         CSUM_RXA_RESERVED_MASK  = 0x000f,
  80         CSUM_RXA_MICSIZE_MASK   = 0x00f0,
  81         CSUM_RXA_HEADERLEN_MASK = 0x1f00,
  82         CSUM_RXA_PADD           = BIT(13),
  83         CSUM_RXA_AMSDU          = BIT(14),
  84         CSUM_RXA_ENA            = BIT(15)
  85 };
  86
  87 /**
  88  * struct iwl_rx_mpdu_res_start - phy info
  89  * @byte_count: byte count of the frame
  90  * @assist: see &enum iwl_csum_rx_assist_info
  91  */
  92 struct iwl_rx_mpdu_res_start {
  93         __le16 byte_count;
  94         __le16 assist;
  95 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
  96
  97 /**
  98  * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
  99  * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
 100  * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK
 101  * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
 102  * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive
 103  * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
 104  * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position
 105  * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
 106  * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
 107  * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
 108  * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
 109  */
 110 enum iwl_rx_phy_flags {
 111         RX_RES_PHY_FLAGS_BAND_24        = BIT(0),
 112         RX_RES_PHY_FLAGS_MOD_CCK        = BIT(1),
 113         RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
 114         RX_RES_PHY_FLAGS_NARROW_BAND    = BIT(3),
 115         RX_RES_PHY_FLAGS_ANTENNA        = (0x7 << 4),
 116         RX_RES_PHY_FLAGS_ANTENNA_POS    = 4,
 117         RX_RES_PHY_FLAGS_AGG            = BIT(7),
 118         RX_RES_PHY_FLAGS_OFDM_HT        = BIT(8),
 119         RX_RES_PHY_FLAGS_OFDM_GF        = BIT(9),
 120         RX_RES_PHY_FLAGS_OFDM_VHT       = BIT(10),
 121 };
 122
 123 /**
 124  * enum iwl_mvm_rx_status - written by fw for each Rx packet
 125  * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
 126  * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
 127  * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found
 128  * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid
 129  * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable
 130  * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
 131  * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
 132  *      in the driver.
 133  * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
 134  * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR:  valid for alg = CCM_CMAC or
 135  *      alg = CCM only. Checks replay attack for 11w frames. Relevant only if
 136  *      %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
 137  * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
 138  * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
 139  * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
 140  * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
 141  * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension
 142  *      algorithm
 143  * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
 144  * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
 145  * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
 146  * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
 147  * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP)
 148  * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done
 149  * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
 150  * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
 151  * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
 152  * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask
 153  * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift
 154  */
 155 enum iwl_mvm_rx_status {
 156         RX_MPDU_RES_STATUS_CRC_OK                       = BIT(0),
 157         RX_MPDU_RES_STATUS_OVERRUN_OK                   = BIT(1),
 158         RX_MPDU_RES_STATUS_SRC_STA_FOUND                = BIT(2),
 159         RX_MPDU_RES_STATUS_KEY_VALID                    = BIT(3),
 160         RX_MPDU_RES_STATUS_KEY_PARAM_OK                 = BIT(4),
 161         RX_MPDU_RES_STATUS_ICV_OK                       = BIT(5),
 162         RX_MPDU_RES_STATUS_MIC_OK                       = BIT(6),
 163         RX_MPDU_RES_STATUS_TTAK_OK                      = BIT(7),
 164         RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR         = BIT(7),
 165         RX_MPDU_RES_STATUS_SEC_NO_ENC                   = (0 << 8),
 166         RX_MPDU_RES_STATUS_SEC_WEP_ENC                  = (1 << 8),
 167         RX_MPDU_RES_STATUS_SEC_CCM_ENC                  = (2 << 8),
 168         RX_MPDU_RES_STATUS_SEC_TKIP_ENC                 = (3 << 8),
 169         RX_MPDU_RES_STATUS_SEC_EXT_ENC                  = (4 << 8),
 170         RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC             = (6 << 8),
 171         RX_MPDU_RES_STATUS_SEC_ENC_ERR                  = (7 << 8),
 172         RX_MPDU_RES_STATUS_SEC_ENC_MSK                  = (7 << 8),
 173         RX_MPDU_RES_STATUS_DEC_DONE                     = BIT(11),
 174         RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP               = BIT(13),
 175         RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT               = BIT(14),
 176         RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME             = BIT(15),
 177         RX_MPDU_RES_STATUS_CSUM_DONE                    = BIT(16),
 178         RX_MPDU_RES_STATUS_CSUM_OK                      = BIT(17),
 179         RX_MDPU_RES_STATUS_STA_ID_SHIFT                 = 24,
 180         RX_MPDU_RES_STATUS_STA_ID_MSK                   = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
 181 };
 182
 183 /* 9000 series API */
 184 enum iwl_rx_mpdu_mac_flags1 {
 185         IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK         = 0x03,
 186         IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK      = 0xf0,
 187         /* shift should be 4, but the length is measured in 2-byte
 188          * words, so shifting only by 3 gives a byte result
 189          */
 190         IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT     = 3,
 191 };
 192
 193 enum iwl_rx_mpdu_mac_flags2 {
 194         /* in 2-byte words */
 195         IWL_RX_MPDU_MFLG2_HDR_LEN_MASK          = 0x1f,
 196         IWL_RX_MPDU_MFLG2_PAD                   = 0x20,
 197         IWL_RX_MPDU_MFLG2_AMSDU                 = 0x40,
 198 };
 199
 200 enum iwl_rx_mpdu_amsdu_info {
 201         IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK     = 0x7f,
 202         IWL_RX_MPDU_AMSDU_LAST_SUBFRAME         = 0x80,
 203 };
 204
 205 #define RX_MPDU_BAND_POS 6
 206 #define RX_MPDU_BAND_MASK 0xC0
 207 #define BAND_IN_RX_STATUS(_val) \
 208         (((_val) & RX_MPDU_BAND_MASK) >> RX_MPDU_BAND_POS)
 209
 210 enum iwl_rx_l3_proto_values {
 211         IWL_RX_L3_TYPE_NONE,
 212         IWL_RX_L3_TYPE_IPV4,
 213         IWL_RX_L3_TYPE_IPV4_FRAG,
 214         IWL_RX_L3_TYPE_IPV6_FRAG,
 215         IWL_RX_L3_TYPE_IPV6,
 216         IWL_RX_L3_TYPE_IPV6_IN_IPV4,
 217         IWL_RX_L3_TYPE_ARP,
 218         IWL_RX_L3_TYPE_EAPOL,
 219 };
 220
 221 #define IWL_RX_L3_PROTO_POS 4
 222
 223 enum iwl_rx_l3l4_flags {
 224         IWL_RX_L3L4_IP_HDR_CSUM_OK              = BIT(0),
 225         IWL_RX_L3L4_TCP_UDP_CSUM_OK             = BIT(1),
 226         IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH         = BIT(2),
 227         IWL_RX_L3L4_TCP_ACK                     = BIT(3),
 228         IWL_RX_L3L4_L3_PROTO_MASK               = 0xf << IWL_RX_L3_PROTO_POS,
 229         IWL_RX_L3L4_L4_PROTO_MASK               = 0xf << 8,
 230         IWL_RX_L3L4_RSS_HASH_MASK               = 0xf << 12,
 231 };
 232
 233 enum iwl_rx_mpdu_status {
 234         IWL_RX_MPDU_STATUS_CRC_OK               = BIT(0),
 235         IWL_RX_MPDU_STATUS_OVERRUN_OK           = BIT(1),
 236         IWL_RX_MPDU_STATUS_SRC_STA_FOUND        = BIT(2),
 237         IWL_RX_MPDU_STATUS_KEY_VALID            = BIT(3),
 238         IWL_RX_MPDU_STATUS_KEY_PARAM_OK         = BIT(4),
 239         IWL_RX_MPDU_STATUS_ICV_OK               = BIT(5),
 240         IWL_RX_MPDU_STATUS_MIC_OK               = BIT(6),
 241         IWL_RX_MPDU_RES_STATUS_TTAK_OK          = BIT(7),
 242         IWL_RX_MPDU_STATUS_SEC_MASK             = 0x7 << 8,
 243         IWL_RX_MPDU_STATUS_SEC_UNKNOWN          = IWL_RX_MPDU_STATUS_SEC_MASK,
 244         IWL_RX_MPDU_STATUS_SEC_NONE             = 0x0 << 8,
 245         IWL_RX_MPDU_STATUS_SEC_WEP              = 0x1 << 8,
 246         IWL_RX_MPDU_STATUS_SEC_CCM              = 0x2 << 8,
 247         IWL_RX_MPDU_STATUS_SEC_TKIP             = 0x3 << 8,
 248         IWL_RX_MPDU_STATUS_SEC_EXT_ENC          = 0x4 << 8,
 249         IWL_RX_MPDU_STATUS_SEC_GCM              = 0x5 << 8,
 250         IWL_RX_MPDU_STATUS_DECRYPTED            = BIT(11),
 251         IWL_RX_MPDU_STATUS_WEP_MATCH            = BIT(12),
 252         IWL_RX_MPDU_STATUS_EXT_IV_MATCH         = BIT(13),
 253         IWL_RX_MPDU_STATUS_KEY_ID_MATCH         = BIT(14),
 254         IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME     = BIT(15),
 255
 256         IWL_RX_MPDU_STATUS_KEY                  = 0x3f0000,
 257         IWL_RX_MPDU_STATUS_DUPLICATE            = BIT(22),
 258
 259         IWL_RX_MPDU_STATUS_STA_ID               = 0x1f000000,
 260 };
 261
 262 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
 263
 264 enum iwl_rx_mpdu_reorder_data {
 265         IWL_RX_MPDU_REORDER_NSSN_MASK           = 0x00000fff,
 266         IWL_RX_MPDU_REORDER_SN_MASK             = 0x00fff000,
 267         IWL_RX_MPDU_REORDER_SN_SHIFT            = 12,
 268         IWL_RX_MPDU_REORDER_BAID_MASK           = 0x7f000000,
 269         IWL_RX_MPDU_REORDER_BAID_SHIFT          = 24,
 270         IWL_RX_MPDU_REORDER_BA_OLD_SN           = 0x80000000,
 271 };
 272
 273 enum iwl_rx_mpdu_phy_info {
 274         IWL_RX_MPDU_PHY_AMPDU           = BIT(5),
 275         IWL_RX_MPDU_PHY_AMPDU_TOGGLE    = BIT(6),
 276         IWL_RX_MPDU_PHY_SHORT_PREAMBLE  = BIT(7),
 277         /* short preamble is only for CCK, for non-CCK overridden by this */
 278         IWL_RX_MPDU_PHY_NCCK_ADDTL_NTFY = BIT(7),
 279         IWL_RX_MPDU_PHY_TSF_OVERLOAD    = BIT(8),
 280 };
 281
 282 enum iwl_rx_mpdu_mac_info {
 283         IWL_RX_MPDU_PHY_MAC_INDEX_MASK          = 0x0f,
 284         IWL_RX_MPDU_PHY_PHY_INDEX_MASK          = 0xf0,
 285 };
 286
 287 /* TSF overload low dword */
 288 enum iwl_rx_phy_data0 {
 289         /* info type: HE any */
 290         IWL_RX_PHY_DATA0_HE_BEAM_CHNG                           = 0x00000001,
 291         IWL_RX_PHY_DATA0_HE_UPLINK                              = 0x00000002,
 292         IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK                      = 0x000000fc,
 293         IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK                  = 0x00000f00,
 294         /* 1 bit reserved */
 295         IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK                       = 0x000fe000,
 296         IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM                        = 0x00100000,
 297         IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK                    = 0x00600000,
 298         IWL_RX_PHY_DATA0_HE_PE_DISAMBIG                         = 0x00800000,
 299         IWL_RX_PHY_DATA0_HE_DOPPLER                             = 0x01000000,
 300         /* 6 bits reserved */
 301         IWL_RX_PHY_DATA0_HE_DELIM_EOF                           = 0x80000000,
 302 };
 303
 304 enum iwl_rx_phy_info_type {
 305         IWL_RX_PHY_INFO_TYPE_NONE                               = 0,
 306         IWL_RX_PHY_INFO_TYPE_CCK                                = 1,
 307         IWL_RX_PHY_INFO_TYPE_OFDM_LGCY                          = 2,
 308         IWL_RX_PHY_INFO_TYPE_HT                                 = 3,
 309         IWL_RX_PHY_INFO_TYPE_VHT_SU                             = 4,
 310         IWL_RX_PHY_INFO_TYPE_VHT_MU                             = 5,
 311         IWL_RX_PHY_INFO_TYPE_HE_SU                              = 6,
 312         IWL_RX_PHY_INFO_TYPE_HE_MU                              = 7,
 313         IWL_RX_PHY_INFO_TYPE_HE_TB                              = 8,
 314         IWL_RX_PHY_INFO_TYPE_HE_MU_EXT                          = 9,
 315         IWL_RX_PHY_INFO_TYPE_HE_TB_EXT                          = 10,
 316 };
 317
 318 /* TSF overload high dword */
 319 enum iwl_rx_phy_data1 {
 320         /*
 321          * check this first - if TSF overload is set,
 322          * see &enum iwl_rx_phy_info_type
 323          */
 324         IWL_RX_PHY_DATA1_INFO_TYPE_MASK                         = 0xf0000000,
 325
 326         /* info type: HT/VHT/HE any */
 327         IWL_RX_PHY_DATA1_LSIG_LEN_MASK                          = 0x0fff0000,
 328
 329         /* info type: HE MU/MU-EXT */
 330         IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION                 = 0x00000001,
 331         IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK        = 0x0000001e,
 332
 333         /* info type: HE any */
 334         IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK                        = 0x000000e0,
 335         IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80                      = 0x00000100,
 336         /* trigger encoded */
 337         IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK                       = 0x0000fe00,
 338
 339         /* info type: HE TB/TX-EXT */
 340         IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE                       = 0x00000001,
 341         IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK                      = 0x0000000e,
 342 };
 343
 344 /* goes into Metadata DW 7 */
 345 enum iwl_rx_phy_data2 {
 346         /* info type: HE MU-EXT */
 347         /* the a1/a2/... is what the PHY/firmware calls the values */
 348         IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0              = 0x000000ff, /* a1 */
 349         IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2              = 0x0000ff00, /* a2 */
 350         IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0              = 0x00ff0000, /* b1 */
 351         IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2              = 0xff000000, /* b2 */
 352
 353         /* info type: HE TB-EXT */
 354         IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1          = 0x0000000f,
 355         IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2          = 0x000000f0,
 356         IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3          = 0x00000f00,
 357         IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4          = 0x0000f000,
 358 };
 359
 360 /* goes into Metadata DW 8 */
 361 enum iwl_rx_phy_data3 {
 362         /* info type: HE MU-EXT */
 363         IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1              = 0x000000ff, /* c1 */
 364         IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3              = 0x0000ff00, /* c2 */
 365         IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1              = 0x00ff0000, /* d1 */
 366         IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3              = 0xff000000, /* d2 */
 367 };
 368
 369 /* goes into Metadata DW 4 high 16 bits */
 370 enum iwl_rx_phy_data4 {
 371         /* info type: HE MU-EXT */
 372         IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU                   = 0x0001,
 373         IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU                   = 0x0002,
 374         IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK                   = 0x0004,
 375         IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK                   = 0x0008,
 376         IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK                = 0x00f0,
 377         IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM                     = 0x0100,
 378         IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK      = 0x0600,
 379 };
 380
 381 /**
 382  * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor
 383  */
 384 struct iwl_rx_mpdu_desc_v1 {
 385         /* DW7 - carries rss_hash only when rpa_en == 1 */
 386         union {
 387                 /**
 388                  * @rss_hash: RSS hash value
 389                  */
 390                 __le32 rss_hash;
 391
 392                 /**
 393                  * @phy_data2: depends on info type (see @phy_data1)
 394                  */
 395                 __le32 phy_data2;
 396         };
 397
 398         /* DW8 - carries filter_match only when rpa_en == 1 */
 399         union {
 400                 /**
 401                  * @filter_match: filter match value
 402                  */
 403                 __le32 filter_match;
 404
 405                 /**
 406                  * @phy_data3: depends on info type (see @phy_data1)
 407                  */
 408                 __le32 phy_data3;
 409         };
 410
 411         /* DW9 */
 412         /**
 413          * @rate_n_flags: RX rate/flags encoding
 414          */
 415         __le32 rate_n_flags;
 416         /* DW10 */
 417         /**
 418          * @energy_a: energy chain A
 419          */
 420         u8 energy_a;
 421         /**
 422          * @energy_b: energy chain B
 423          */
 424         u8 energy_b;
 425         /**
 426          * @channel: channel number
 427          */
 428         u8 channel;
 429         /**
 430          * @mac_context: MAC context mask
 431          */
 432         u8 mac_context;
 433         /* DW11 */
 434         /**
 435          * @gp2_on_air_rise: GP2 timer value on air rise (INA)
 436          */
 437         __le32 gp2_on_air_rise;
 438         /* DW12 & DW13 */
 439         union {
 440                 /**
 441                  * @tsf_on_air_rise:
 442                  * TSF value on air rise (INA), only valid if
 443                  * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
 444                  */
 445                 __le64 tsf_on_air_rise;
 446
 447                 struct {
 448                         /**
 449                          * @phy_data0: depends on info_type, see @phy_data1
 450                          */
 451                         __le32 phy_data0;
 452                         /**
 453                          * @phy_data1: valid only if
 454                          * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set,
 455                          * see &enum iwl_rx_phy_data1.
 456                          */
 457                         __le32 phy_data1;
 458                 };
 459         };
 460 } __packed;
 461
 462 /**
 463  * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor
 464  */
 465 struct iwl_rx_mpdu_desc_v3 {
 466         /* DW7 - carries filter_match only when rpa_en == 1 */
 467         union {
 468                 /**
 469                  * @filter_match: filter match value
 470                  */
 471                 __le32 filter_match;
 472
 473                 /**
 474                  * @phy_data3: depends on info type (see @phy_data1)
 475                  */
 476                 __le32 phy_data3;
 477         };
 478
 479         /* DW8 - carries rss_hash only when rpa_en == 1 */
 480         union {
 481                 /**
 482                  * @rss_hash: RSS hash value
 483                  */
 484                 __le32 rss_hash;
 485
 486                 /**
 487                  * @phy_data2: depends on info type (see @phy_data1)
 488                  */
 489                 __le32 phy_data2;
 490         };
 491         /* DW9 */
 492         /**
 493          * @partial_hash: 31:0 ip/tcp header hash
 494          *      w/o some fields (such as IP SRC addr)
 495          */
 496         __le32 partial_hash;
 497         /* DW10 */
 498         /**
 499          * @raw_xsum: raw xsum value
 500          */
 501         __be16 raw_xsum;
 502         /**
 503          * @reserved_xsum: reserved high bits in the raw checksum
 504          */
 505         __le16 reserved_xsum;
 506         /* DW11 */
 507         /**
 508          * @rate_n_flags: RX rate/flags encoding
 509          */
 510         __le32 rate_n_flags;
 511         /* DW12 */
 512         /**
 513          * @energy_a: energy chain A
 514          */
 515         u8 energy_a;
 516         /**
 517          * @energy_b: energy chain B
 518          */
 519         u8 energy_b;
 520         /**
 521          * @channel: channel number
 522          */
 523         u8 channel;
 524         /**
 525          * @mac_context: MAC context mask
 526          */
 527         u8 mac_context;
 528         /* DW13 */
 529         /**
 530          * @gp2_on_air_rise: GP2 timer value on air rise (INA)
 531          */
 532         __le32 gp2_on_air_rise;
 533         /* DW14 & DW15 */
 534         union {
 535                 /**
 536                  * @tsf_on_air_rise:
 537                  * TSF value on air rise (INA), only valid if
 538                  * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
 539                  */
 540                 __le64 tsf_on_air_rise;
 541
 542                 struct {
 543                         /**
 544                          * @phy_data0: depends on info_type, see @phy_data1
 545                          */
 546                         __le32 phy_data0;
 547                         /**
 548                          * @phy_data1: valid only if
 549                          * %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set,
 550                          * see &enum iwl_rx_phy_data1.
 551                          */
 552                         __le32 phy_data1;
 553                 };
 554         };
 555         /* DW16 & DW17 */
 556         /**
 557          * @reserved: reserved
 558          */
 559         __le32 reserved[2];
 560 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */
 561
 562 /**
 563  * struct iwl_rx_mpdu_desc - RX MPDU descriptor
 564  */
 565 struct iwl_rx_mpdu_desc {
 566         /* DW2 */
 567         /**
 568          * @mpdu_len: MPDU length
 569          */
 570         __le16 mpdu_len;
 571         /**
 572          * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1
 573          */
 574         u8 mac_flags1;
 575         /**
 576          * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2
 577          */
 578         u8 mac_flags2;
 579         /* DW3 */
 580         /**
 581          * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info
 582          */
 583         u8 amsdu_info;
 584         /**
 585          * @phy_info: &enum iwl_rx_mpdu_phy_info
 586          */
 587         __le16 phy_info;
 588         /**
 589          * @mac_phy_idx: MAC/PHY index
 590          */
 591         u8 mac_phy_idx;
 592         /* DW4 - carries csum data only when rpa_en == 1 */
 593         /**
 594          * @raw_csum: raw checksum (alledgedly unreliable)
 595          */
 596         __le16 raw_csum;
 597
 598         union {
 599                 /**
 600                  * @l3l4_flags: &enum iwl_rx_l3l4_flags
 601                  */
 602                 __le16 l3l4_flags;
 603
 604                 /**
 605                  * @phy_data4: depends on info type, see phy_data1
 606                  */
 607                 __le16 phy_data4;
 608         };
 609         /* DW5 */
 610         /**
 611          * @status: &enum iwl_rx_mpdu_status
 612          */
 613         __le32 status;
 614
 615         /* DW6 */
 616         /**
 617          * @reorder_data: &enum iwl_rx_mpdu_reorder_data
 618          */
 619         __le32 reorder_data;
 620
 621         union {
 622                 struct iwl_rx_mpdu_desc_v1 v1;
 623                 struct iwl_rx_mpdu_desc_v3 v3;
 624         };
 625 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */
 626
 627 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1)
 628
 629 #define RX_NO_DATA_CHAIN_A_POS          0
 630 #define RX_NO_DATA_CHAIN_A_MSK          (0xff << RX_NO_DATA_CHAIN_A_POS)
 631 #define RX_NO_DATA_CHAIN_B_POS          8
 632 #define RX_NO_DATA_CHAIN_B_MSK          (0xff << RX_NO_DATA_CHAIN_B_POS)
 633 #define RX_NO_DATA_CHANNEL_POS          16
 634 #define RX_NO_DATA_CHANNEL_MSK          (0xff << RX_NO_DATA_CHANNEL_POS)
 635
 636 #define RX_NO_DATA_INFO_TYPE_POS        0
 637 #define RX_NO_DATA_INFO_TYPE_MSK        (0xff << RX_NO_DATA_INFO_TYPE_POS)
 638 #define RX_NO_DATA_INFO_TYPE_NONE       0
 639 #define RX_NO_DATA_INFO_TYPE_RX_ERR     1
 640 #define RX_NO_DATA_INFO_TYPE_NDP        2
 641 #define RX_NO_DATA_INFO_TYPE_MU_UNMATCHED       3
 642 #define RX_NO_DATA_INFO_TYPE_HE_TB_UNMATCHED    4
 643
 644 #define RX_NO_DATA_INFO_ERR_POS         8
 645 #define RX_NO_DATA_INFO_ERR_MSK         (0xff << RX_NO_DATA_INFO_ERR_POS)
 646 #define RX_NO_DATA_INFO_ERR_NONE        0
 647 #define RX_NO_DATA_INFO_ERR_BAD_PLCP    1
 648 #define RX_NO_DATA_INFO_ERR_UNSUPPORTED_RATE    2
 649 #define RX_NO_DATA_INFO_ERR_NO_DELIM            3
 650 #define RX_NO_DATA_INFO_ERR_BAD_MAC_HDR 4
 651
 652 #define RX_NO_DATA_FRAME_TIME_POS       0
 653 #define RX_NO_DATA_FRAME_TIME_MSK       (0xfffff << RX_NO_DATA_FRAME_TIME_POS)
 654
 655 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK  0x03800000
 656 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000
 657
 658 /**
 659  * struct iwl_rx_no_data - RX no data descriptor
 660  * @info: 7:0 frame type, 15:8 RX error type
 661  * @rssi: 7:0 energy chain-A,
 662  *      15:8 chain-B, measured at FINA time (FINA_ENERGY), 16:23 channel
 663  * @on_air_rise_time: GP2 during on air rise
 664  * @fr_time: frame time
 665  * @rate: rate/mcs of frame
 666  * @phy_info: &enum iwl_rx_phy_data0 and &enum iwl_rx_phy_info_type
 667  * @rx_vec: DW-12:9 raw RX vectors from DSP according to modulation type.
 668  *      for VHT: OFDM_RX_VECTOR_SIGA1_OUT, OFDM_RX_VECTOR_SIGA2_OUT
 669  *      for HE: OFDM_RX_VECTOR_HE_SIGA1_OUT, OFDM_RX_VECTOR_HE_SIGA2_OUT
 670  */
 671 struct iwl_rx_no_data {
 672         __le32 info;
 673         __le32 rssi;
 674         __le32 on_air_rise_time;
 675         __le32 fr_time;
 676         __le32 rate;
 677         __le32 phy_info[2];
 678         __le32 rx_vec[2];
 679 } __packed; /* RX_NO_DATA_NTFY_API_S_VER_1 */
 680
 681 struct iwl_frame_release {
 682         u8 baid;
 683         u8 reserved;
 684         __le16 nssn;
 685 };
 686
 687 /**
 688  * enum iwl_bar_frame_release_sta_tid - STA/TID information for BAR release
 689  * @IWL_BAR_FRAME_RELEASE_TID_MASK: TID mask
 690  * @IWL_BAR_FRAME_RELEASE_STA_MASK: STA mask
 691  */
 692 enum iwl_bar_frame_release_sta_tid {
 693         IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f,
 694         IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0,
 695 };
 696
 697 /**
 698  * enum iwl_bar_frame_release_ba_info - BA information for BAR release
 699  * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask
 700  * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver)
 701  * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask
 702  */
 703 enum iwl_bar_frame_release_ba_info {
 704         IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff,
 705         IWL_BAR_FRAME_RELEASE_SN_MASK   = 0x00fff000,
 706         IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000,
 707 };
 708
 709 /**
 710  * struct iwl_bar_frame_release - frame release from BAR info
 711  * @sta_tid: STA & TID information, see &enum iwl_bar_frame_release_sta_tid.
 712  * @ba_info: BA information, see &enum iwl_bar_frame_release_ba_info.
 713  */
 714 struct iwl_bar_frame_release {
 715         __le32 sta_tid;
 716         __le32 ba_info;
 717 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */
 718
 719 enum iwl_rss_hash_func_en {
 720         IWL_RSS_HASH_TYPE_IPV4_TCP,
 721         IWL_RSS_HASH_TYPE_IPV4_UDP,
 722         IWL_RSS_HASH_TYPE_IPV4_PAYLOAD,
 723         IWL_RSS_HASH_TYPE_IPV6_TCP,
 724         IWL_RSS_HASH_TYPE_IPV6_UDP,
 725         IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
 726 };
 727
 728 #define IWL_RSS_HASH_KEY_CNT 10
 729 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128
 730 #define IWL_RSS_ENABLE 1
 731
 732 /**
 733  * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration
 734  *
 735  * @flags: 1 - enable, 0 - disable
 736  * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en
 737  * @reserved: reserved
 738  * @secret_key: 320 bit input of random key configuration from driver
 739  * @indirection_table: indirection table
 740  */
 741 struct iwl_rss_config_cmd {
 742         __le32 flags;
 743         u8 hash_mask;
 744         u8 reserved[3];
 745         __le32 secret_key[IWL_RSS_HASH_KEY_CNT];
 746         u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE];
 747 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */
 748
 749 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
 750 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
 751
 752 /**
 753  * struct iwl_rxq_sync_cmd - RXQ notification trigger
 754  *
 755  * @flags: flags of the notification. bit 0:3 are the sender queue
 756  * @rxq_mask: rx queues to send the notification on
 757  * @count: number of bytes in payload, should be DWORD aligned
 758  * @payload: data to send to rx queues
 759  */
 760 struct iwl_rxq_sync_cmd {
 761         __le32 flags;
 762         __le32 rxq_mask;
 763         __le32 count;
 764         u8 payload[];
 765 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
 766
 767 /**
 768  * struct iwl_rxq_sync_notification - Notification triggered by RXQ
 769  * sync command
 770  *
 771  * @count: number of bytes in payload
 772  * @payload: data to send to rx queues
 773  */
 774 struct iwl_rxq_sync_notification {
 775         __le32 count;
 776         u8 payload[];
 777 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
 778
 779 /**
 780  * enum iwl_mvm_rxq_notif_type - Internal message identifier
 781  *
 782  * @IWL_MVM_RXQ_EMPTY: empty sync notification
 783  * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA
 784  * @IWL_MVM_RXQ_NSSN_SYNC: notify all the RSS queues with the new NSSN
 785  */
 786 enum iwl_mvm_rxq_notif_type {
 787         IWL_MVM_RXQ_EMPTY,
 788         IWL_MVM_RXQ_NOTIF_DEL_BA,
 789         IWL_MVM_RXQ_NSSN_SYNC,
 790 };
 791
 792 /**
 793  * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent
 794  * in &iwl_rxq_sync_cmd. Should be DWORD aligned.
 795  * FW is agnostic to the payload, so there are no endianity requirements.
 796  *
 797  * @type: value from &iwl_mvm_rxq_notif_type
 798  * @sync: ctrl path is waiting for all notifications to be received
 799  * @cookie: internal cookie to identify old notifications
 800  * @data: payload
 801  */
 802 struct iwl_mvm_internal_rxq_notif {
 803         u16 type;
 804         u16 sync;
 805         u32 cookie;
 806         u8 data[];
 807 } __packed;
 808
 809 /**
 810  * enum iwl_mvm_pm_event - type of station PM event
 811  * @IWL_MVM_PM_EVENT_AWAKE: station woke up
 812  * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep
 813  * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger
 814  * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll
 815  */
 816 enum iwl_mvm_pm_event {
 817         IWL_MVM_PM_EVENT_AWAKE,
 818         IWL_MVM_PM_EVENT_ASLEEP,
 819         IWL_MVM_PM_EVENT_UAPSD,
 820         IWL_MVM_PM_EVENT_PS_POLL,
 821 }; /* PEER_PM_NTFY_API_E_VER_1 */
 822
 823 /**
 824  * struct iwl_mvm_pm_state_notification - station PM state notification
 825  * @sta_id: station ID of the station changing state
 826  * @type: the new powersave state, see &enum iwl_mvm_pm_event
 827  */
 828 struct iwl_mvm_pm_state_notification {
 829         u8 sta_id;
 830         u8 type;
 831         /* private: */
 832         __le16 reserved;
 833 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */
 834
 835 #define BA_WINDOW_STREAMS_MAX           16
 836 #define BA_WINDOW_STATUS_TID_MSK        0x000F
 837 #define BA_WINDOW_STATUS_STA_ID_POS     4
 838 #define BA_WINDOW_STATUS_STA_ID_MSK     0x01F0
 839 #define BA_WINDOW_STATUS_VALID_MSK      BIT(9)
 840
 841 /**
 842  * struct iwl_ba_window_status_notif - reordering window's status notification
 843  * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63]
 844  * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid
 845  * @start_seq_num: the start sequence number of the bitmap
 846  * @mpdu_rx_count: the number of received MPDUs since entering D0i3
 847  */
 848 struct iwl_ba_window_status_notif {
 849         __le64 bitmap[BA_WINDOW_STREAMS_MAX];
 850         __le16 ra_tid[BA_WINDOW_STREAMS_MAX];
 851         __le32 start_seq_num[BA_WINDOW_STREAMS_MAX];
 852         __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX];
 853 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */
 854
 855 /**
 856  * struct iwl_rfh_queue_config - RX queue configuration
 857  * @q_num: Q num
 858  * @enable: enable queue
 859  * @reserved: alignment
 860  * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
 861  * @fr_bd_cb: DMA address of freeRB table
 862  * @ur_bd_cb: DMA address of used RB table
 863  * @fr_bd_wid: Initial index of the free table
 864  */
 865 struct iwl_rfh_queue_data {
 866         u8 q_num;
 867         u8 enable;
 868         __le16 reserved;
 869         __le64 urbd_stts_wrptr;
 870         __le64 fr_bd_cb;
 871         __le64 ur_bd_cb;
 872         __le32 fr_bd_wid;
 873 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */
 874
 875 /**
 876  * struct iwl_rfh_queue_config - RX queue configuration
 877  * @num_queues: number of queues configured
 878  * @reserved: alignment
 879  * @data: DMA addresses per-queue
 880  */
 881 struct iwl_rfh_queue_config {
 882         u8 num_queues;
 883         u8 reserved[3];
 884         struct iwl_rfh_queue_data data[];
 885 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */
 886
 887 #endif /* __iwl_fw_api_rx_h__ */