drivers/net/wireless/intersil/prism54/isl_38xx.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  *  Copyright (C) 2002 Intersil Americas Inc.
   4  */
   5
   6 #ifndef _ISL_38XX_H
   7 #define _ISL_38XX_H
   8
   9 #include <asm/io.h>
  10 #include <asm/byteorder.h>
  11
  12 #define ISL38XX_CB_RX_QSIZE                     8
  13 #define ISL38XX_CB_TX_QSIZE                     32
  14
  15 /* ISL38XX Access Point Specific definitions */
  16 #define ISL38XX_MAX_WDS_LINKS                   8
  17
  18 /* ISL38xx Client Specific definitions */
  19 #define ISL38XX_PSM_ACTIVE_STATE                0
  20 #define ISL38XX_PSM_POWERSAVE_STATE             1
  21
  22 /* ISL38XX Host Interface Definitions */
  23 #define ISL38XX_PCI_MEM_SIZE                    0x02000
  24 #define ISL38XX_MEMORY_WINDOW_SIZE              0x01000
  25 #define ISL38XX_DEV_FIRMWARE_ADDRES             0x20000
  26 #define ISL38XX_WRITEIO_DELAY                   10      /* in us */
  27 #define ISL38XX_RESET_DELAY                     50      /* in ms */
  28 #define ISL38XX_WAIT_CYCLE                      10      /* in 10ms */
  29 #define ISL38XX_MAX_WAIT_CYCLES                 10
  30
  31 /* PCI Memory Area */
  32 #define ISL38XX_HARDWARE_REG                    0x0000
  33 #define ISL38XX_CARDBUS_CIS                     0x0800
  34 #define ISL38XX_DIRECT_MEM_WIN                  0x1000
  35
  36 /* Hardware registers */
  37 #define ISL38XX_DEV_INT_REG                     0x0000
  38 #define ISL38XX_INT_IDENT_REG                   0x0010
  39 #define ISL38XX_INT_ACK_REG                     0x0014
  40 #define ISL38XX_INT_EN_REG                      0x0018
  41 #define ISL38XX_GEN_PURP_COM_REG_1              0x0020
  42 #define ISL38XX_GEN_PURP_COM_REG_2              0x0024
  43 #define ISL38XX_CTRL_BLK_BASE_REG               ISL38XX_GEN_PURP_COM_REG_1
  44 #define ISL38XX_DIR_MEM_BASE_REG                0x0030
  45 #define ISL38XX_CTRL_STAT_REG                   0x0078
  46
  47 /* High end mobos queue up pci writes, the following
  48  * is used to "read" from after a write to force flush */
  49 #define ISL38XX_PCI_POSTING_FLUSH               ISL38XX_INT_EN_REG
  50
  51 /**
  52  * isl38xx_w32_flush - PCI iomem write helper
  53  * @base: (host) memory base address of the device
  54  * @val: 32bit value (host order) to write
  55  * @offset: byte offset into @base to write value to
  56  *
  57  *  This helper takes care of writing a 32bit datum to the
  58  *  specified offset into the device's pci memory space, and making sure
  59  *  the pci memory buffers get flushed by performing one harmless read
  60  *  from the %ISL38XX_PCI_POSTING_FLUSH offset.
  61  */
  62 static inline void
  63 isl38xx_w32_flush(void __iomem *base, u32 val, unsigned long offset)
  64 {
  65         writel(val, base + offset);
  66         (void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
  67 }
  68
  69 /* Device Interrupt register bits */
  70 #define ISL38XX_DEV_INT_RESET                   0x0001
  71 #define ISL38XX_DEV_INT_UPDATE                  0x0002
  72 #define ISL38XX_DEV_INT_WAKEUP                  0x0008
  73 #define ISL38XX_DEV_INT_SLEEP                   0x0010
  74
  75 /* Interrupt Identification/Acknowledge/Enable register bits */
  76 #define ISL38XX_INT_IDENT_UPDATE                0x0002
  77 #define ISL38XX_INT_IDENT_INIT                  0x0004
  78 #define ISL38XX_INT_IDENT_WAKEUP                0x0008
  79 #define ISL38XX_INT_IDENT_SLEEP                 0x0010
  80 #define ISL38XX_INT_SOURCES                     0x001E
  81
  82 /* Control/Status register bits */
  83 /* Looks like there are other meaningful bits
  84     0x20004400 seen in normal operation,
  85     0x200044db at 'timeout waiting for mgmt response'
  86 */
  87 #define ISL38XX_CTRL_STAT_SLEEPMODE             0x00000200
  88 #define ISL38XX_CTRL_STAT_CLKRUN                0x00800000
  89 #define ISL38XX_CTRL_STAT_RESET                 0x10000000
  90 #define ISL38XX_CTRL_STAT_RAMBOOT               0x20000000
  91 #define ISL38XX_CTRL_STAT_STARTHALTED           0x40000000
  92 #define ISL38XX_CTRL_STAT_HOST_OVERRIDE         0x80000000
  93
  94 /* Control Block definitions */
  95 #define ISL38XX_CB_RX_DATA_LQ                   0
  96 #define ISL38XX_CB_TX_DATA_LQ                   1
  97 #define ISL38XX_CB_RX_DATA_HQ                   2
  98 #define ISL38XX_CB_TX_DATA_HQ                   3
  99 #define ISL38XX_CB_RX_MGMTQ                     4
 100 #define ISL38XX_CB_TX_MGMTQ                     5
 101 #define ISL38XX_CB_QCOUNT                       6
 102 #define ISL38XX_CB_MGMT_QSIZE                   4
 103 #define ISL38XX_MIN_QTHRESHOLD                  4       /* fragments */
 104
 105 /* Memory Manager definitions */
 106 #define MGMT_FRAME_SIZE                         1500    /* >= size struct obj_bsslist */
 107 #define MGMT_TX_FRAME_COUNT                     24      /* max 4 + spare 4 + 8 init */
 108 #define MGMT_RX_FRAME_COUNT                     24      /* 4*4 + spare 8 */
 109 #define MGMT_FRAME_COUNT                        (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
 110 #define CONTROL_BLOCK_SIZE                      1024    /* should be enough */
 111 #define PSM_FRAME_SIZE                          1536
 112 #define PSM_MINIMAL_STATION_COUNT               64
 113 #define PSM_FRAME_COUNT                         PSM_MINIMAL_STATION_COUNT
 114 #define PSM_BUFFER_SIZE                         PSM_FRAME_SIZE * PSM_FRAME_COUNT
 115 #define MAX_TRAP_RX_QUEUE                       4
 116 #define HOST_MEM_BLOCK                          CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
 117
 118 /* Fragment package definitions */
 119 #define FRAGMENT_FLAG_MF                        0x0001
 120 #define MAX_FRAGMENT_SIZE                       1536
 121
 122 /* In monitor mode frames have a header. I don't know exactly how big those
 123  * frame can be but I've never seen any frame bigger than 1584... :
 124  */
 125 #define MAX_FRAGMENT_SIZE_RX                    1600
 126
 127 typedef struct {
 128         __le32 address;         /* physical address on host */
 129         __le16 size;            /* packet size */
 130         __le16 flags;           /* set of bit-wise flags */
 131 } isl38xx_fragment;
 132
 133 struct isl38xx_cb {
 134         __le32 driver_curr_frag[ISL38XX_CB_QCOUNT];
 135         __le32 device_curr_frag[ISL38XX_CB_QCOUNT];
 136         isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
 137         isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
 138         isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
 139         isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
 140         isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
 141         isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
 142 };
 143
 144 typedef struct isl38xx_cb isl38xx_control_block;
 145
 146 /* determine number of entries currently in queue */
 147 int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
 148
 149 void isl38xx_disable_interrupts(void __iomem *);
 150 void isl38xx_enable_common_interrupts(void __iomem *);
 151
 152 void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
 153                                   void __iomem *);
 154 void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void __iomem *);
 155 void isl38xx_trigger_device(int, void __iomem *);
 156 void isl38xx_interface_reset(void __iomem *, dma_addr_t);
 157
 158 #endif                          /* _ISL_38XX_H */