?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
WIP FPC-III support
[linux/fpc-iii.git] / sound / soc / codecs / wm8996.c
blobd303ef7571e9d38532828818f6aed5b58bbd6a04
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * wm8996.c - WM8996 audio codec interface
4 *
5 * Copyright 2011-2 Wolfson Microelectronics PLC.
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/completion.h>
13 #include <linux/delay.h>
14 #include <linux/pm.h>
15 #include <linux/gcd.h>
16 #include <linux/gpio/driver.h>
17 #include <linux/gpio.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/slab.h>
22 #include <linux/workqueue.h>
23 #include <sound/core.h>
24 #include <sound/jack.h>
25 #include <sound/pcm.h>
26 #include <sound/pcm_params.h>
27 #include <sound/soc.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30 #include <trace/events/asoc.h>
31
32 #include <sound/wm8996.h>
33 #include "wm8996.h"
34
35 #define WM8996_AIFS 2
36
37 #define HPOUT1L 1
38 #define HPOUT1R 2
39 #define HPOUT2L 4
40 #define HPOUT2R 8
41
42 #define WM8996_NUM_SUPPLIES 3
43 static const char *wm8996_supply_names[WM8996_NUM_SUPPLIES] = {
44 "DBVDD",
45 "AVDD1",
46 "AVDD2",
47 };
48
49 struct wm8996_priv {
50 struct device *dev;
51 struct regmap *regmap;
52 struct snd_soc_component *component;
53
54 int ldo1ena;
55
56 int sysclk;
57 int sysclk_src;
58
59 int fll_src;
60 int fll_fref;
61 int fll_fout;
62
63 struct completion fll_lock;
64
65 u16 dcs_pending;
66 struct completion dcs_done;
67
68 u16 hpout_ena;
69 u16 hpout_pending;
70
71 struct regulator_bulk_data supplies[WM8996_NUM_SUPPLIES];
72 struct notifier_block disable_nb[WM8996_NUM_SUPPLIES];
73 int bg_ena;
74
75 struct wm8996_pdata pdata;
76
77 int rx_rate[WM8996_AIFS];
78 int bclk_rate[WM8996_AIFS];
79
80 /* Platform dependant ReTune mobile configuration */
81 int num_retune_mobile_texts;
82 const char **retune_mobile_texts;
83 int retune_mobile_cfg[2];
84 struct soc_enum retune_mobile_enum;
85
86 struct snd_soc_jack *jack;
87 bool detecting;
88 bool jack_mic;
89 int jack_flips;
90 wm8996_polarity_fn polarity_cb;
91
92 #ifdef CONFIG_GPIOLIB
93 struct gpio_chip gpio_chip;
94 #endif
95 };
96
97 /* We can't use the same notifier block for more than one supply and
98 * there's no way I can see to get from a callback to the caller
99 * except container_of().
100 */
101 #define WM8996_REGULATOR_EVENT(n) \
102 static int wm8996_regulator_event_##n(struct notifier_block *nb, \
103 unsigned long event, void *data) \
104 { \
105 struct wm8996_priv *wm8996 = container_of(nb, struct wm8996_priv, \
106 disable_nb[n]); \
107 if (event & REGULATOR_EVENT_DISABLE) { \
108 regcache_mark_dirty(wm8996->regmap); \
109 } \
110 return 0; \
111 }
112
113 WM8996_REGULATOR_EVENT(0)
114 WM8996_REGULATOR_EVENT(1)
115 WM8996_REGULATOR_EVENT(2)
116
117 static const struct reg_default wm8996_reg[] = {
118 { WM8996_POWER_MANAGEMENT_1, 0x0 },
119 { WM8996_POWER_MANAGEMENT_2, 0x0 },
120 { WM8996_POWER_MANAGEMENT_3, 0x0 },
121 { WM8996_POWER_MANAGEMENT_4, 0x0 },
122 { WM8996_POWER_MANAGEMENT_5, 0x0 },
123 { WM8996_POWER_MANAGEMENT_6, 0x0 },
124 { WM8996_POWER_MANAGEMENT_7, 0x10 },
125 { WM8996_POWER_MANAGEMENT_8, 0x0 },
126 { WM8996_LEFT_LINE_INPUT_VOLUME, 0x0 },
127 { WM8996_RIGHT_LINE_INPUT_VOLUME, 0x0 },
128 { WM8996_LINE_INPUT_CONTROL, 0x0 },
129 { WM8996_DAC1_HPOUT1_VOLUME, 0x88 },
130 { WM8996_DAC2_HPOUT2_VOLUME, 0x88 },
131 { WM8996_DAC1_LEFT_VOLUME, 0x2c0 },
132 { WM8996_DAC1_RIGHT_VOLUME, 0x2c0 },
133 { WM8996_DAC2_LEFT_VOLUME, 0x2c0 },
134 { WM8996_DAC2_RIGHT_VOLUME, 0x2c0 },
135 { WM8996_OUTPUT1_LEFT_VOLUME, 0x80 },
136 { WM8996_OUTPUT1_RIGHT_VOLUME, 0x80 },
137 { WM8996_OUTPUT2_LEFT_VOLUME, 0x80 },
138 { WM8996_OUTPUT2_RIGHT_VOLUME, 0x80 },
139 { WM8996_MICBIAS_1, 0x39 },
140 { WM8996_MICBIAS_2, 0x39 },
141 { WM8996_LDO_1, 0x3 },
142 { WM8996_LDO_2, 0x13 },
143 { WM8996_ACCESSORY_DETECT_MODE_1, 0x4 },
144 { WM8996_ACCESSORY_DETECT_MODE_2, 0x0 },
145 { WM8996_HEADPHONE_DETECT_1, 0x20 },
146 { WM8996_HEADPHONE_DETECT_2, 0x0 },
147 { WM8996_MIC_DETECT_1, 0x7600 },
148 { WM8996_MIC_DETECT_2, 0xbf },
149 { WM8996_CHARGE_PUMP_1, 0x1f25 },
150 { WM8996_CHARGE_PUMP_2, 0xab19 },
151 { WM8996_DC_SERVO_1, 0x0 },
152 { WM8996_DC_SERVO_3, 0x0 },
153 { WM8996_DC_SERVO_5, 0x2a2a },
154 { WM8996_DC_SERVO_6, 0x0 },
155 { WM8996_DC_SERVO_7, 0x0 },
156 { WM8996_ANALOGUE_HP_1, 0x0 },
157 { WM8996_ANALOGUE_HP_2, 0x0 },
158 { WM8996_CONTROL_INTERFACE_1, 0x8004 },
159 { WM8996_WRITE_SEQUENCER_CTRL_1, 0x0 },
160 { WM8996_WRITE_SEQUENCER_CTRL_2, 0x0 },
161 { WM8996_AIF_CLOCKING_1, 0x0 },
162 { WM8996_AIF_CLOCKING_2, 0x0 },
163 { WM8996_CLOCKING_1, 0x10 },
164 { WM8996_CLOCKING_2, 0x0 },
165 { WM8996_AIF_RATE, 0x83 },
166 { WM8996_FLL_CONTROL_1, 0x0 },
167 { WM8996_FLL_CONTROL_2, 0x0 },
168 { WM8996_FLL_CONTROL_3, 0x0 },
169 { WM8996_FLL_CONTROL_4, 0x5dc0 },
170 { WM8996_FLL_CONTROL_5, 0xc84 },
171 { WM8996_FLL_EFS_1, 0x0 },
172 { WM8996_FLL_EFS_2, 0x2 },
173 { WM8996_AIF1_CONTROL, 0x0 },
174 { WM8996_AIF1_BCLK, 0x0 },
175 { WM8996_AIF1_TX_LRCLK_1, 0x80 },
176 { WM8996_AIF1_TX_LRCLK_2, 0x8 },
177 { WM8996_AIF1_RX_LRCLK_1, 0x80 },
178 { WM8996_AIF1_RX_LRCLK_2, 0x0 },
179 { WM8996_AIF1TX_DATA_CONFIGURATION_1, 0x1818 },
180 { WM8996_AIF1TX_DATA_CONFIGURATION_2, 0 },
181 { WM8996_AIF1RX_DATA_CONFIGURATION, 0x1818 },
182 { WM8996_AIF1TX_CHANNEL_0_CONFIGURATION, 0x0 },
183 { WM8996_AIF1TX_CHANNEL_1_CONFIGURATION, 0x0 },
184 { WM8996_AIF1TX_CHANNEL_2_CONFIGURATION, 0x0 },
185 { WM8996_AIF1TX_CHANNEL_3_CONFIGURATION, 0x0 },
186 { WM8996_AIF1TX_CHANNEL_4_CONFIGURATION, 0x0 },
187 { WM8996_AIF1TX_CHANNEL_5_CONFIGURATION, 0x0 },
188 { WM8996_AIF1RX_CHANNEL_0_CONFIGURATION, 0x0 },
189 { WM8996_AIF1RX_CHANNEL_1_CONFIGURATION, 0x0 },
190 { WM8996_AIF1RX_CHANNEL_2_CONFIGURATION, 0x0 },
191 { WM8996_AIF1RX_CHANNEL_3_CONFIGURATION, 0x0 },
192 { WM8996_AIF1RX_CHANNEL_4_CONFIGURATION, 0x0 },
193 { WM8996_AIF1RX_CHANNEL_5_CONFIGURATION, 0x0 },
194 { WM8996_AIF1RX_MONO_CONFIGURATION, 0x0 },
195 { WM8996_AIF1TX_TEST, 0x7 },
196 { WM8996_AIF2_CONTROL, 0x0 },
197 { WM8996_AIF2_BCLK, 0x0 },
198 { WM8996_AIF2_TX_LRCLK_1, 0x80 },
199 { WM8996_AIF2_TX_LRCLK_2, 0x8 },
200 { WM8996_AIF2_RX_LRCLK_1, 0x80 },
201 { WM8996_AIF2_RX_LRCLK_2, 0x0 },
202 { WM8996_AIF2TX_DATA_CONFIGURATION_1, 0x1818 },
203 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x1818 },
204 { WM8996_AIF2RX_DATA_CONFIGURATION, 0x0 },
205 { WM8996_AIF2TX_CHANNEL_0_CONFIGURATION, 0x0 },
206 { WM8996_AIF2TX_CHANNEL_1_CONFIGURATION, 0x0 },
207 { WM8996_AIF2RX_CHANNEL_0_CONFIGURATION, 0x0 },
208 { WM8996_AIF2RX_CHANNEL_1_CONFIGURATION, 0x0 },
209 { WM8996_AIF2RX_MONO_CONFIGURATION, 0x0 },
210 { WM8996_AIF2TX_TEST, 0x1 },
211 { WM8996_DSP1_TX_LEFT_VOLUME, 0xc0 },
212 { WM8996_DSP1_TX_RIGHT_VOLUME, 0xc0 },
213 { WM8996_DSP1_RX_LEFT_VOLUME, 0xc0 },
214 { WM8996_DSP1_RX_RIGHT_VOLUME, 0xc0 },
215 { WM8996_DSP1_TX_FILTERS, 0x2000 },
216 { WM8996_DSP1_RX_FILTERS_1, 0x200 },
217 { WM8996_DSP1_RX_FILTERS_2, 0x10 },
218 { WM8996_DSP1_DRC_1, 0x98 },
219 { WM8996_DSP1_DRC_2, 0x845 },
220 { WM8996_DSP1_RX_EQ_GAINS_1, 0x6318 },
221 { WM8996_DSP1_RX_EQ_GAINS_2, 0x6300 },
222 { WM8996_DSP1_RX_EQ_BAND_1_A, 0xfca },
223 { WM8996_DSP1_RX_EQ_BAND_1_B, 0x400 },
224 { WM8996_DSP1_RX_EQ_BAND_1_PG, 0xd8 },
225 { WM8996_DSP1_RX_EQ_BAND_2_A, 0x1eb5 },
226 { WM8996_DSP1_RX_EQ_BAND_2_B, 0xf145 },
227 { WM8996_DSP1_RX_EQ_BAND_2_C, 0xb75 },
228 { WM8996_DSP1_RX_EQ_BAND_2_PG, 0x1c5 },
229 { WM8996_DSP1_RX_EQ_BAND_3_A, 0x1c58 },
230 { WM8996_DSP1_RX_EQ_BAND_3_B, 0xf373 },
231 { WM8996_DSP1_RX_EQ_BAND_3_C, 0xa54 },
232 { WM8996_DSP1_RX_EQ_BAND_3_PG, 0x558 },
233 { WM8996_DSP1_RX_EQ_BAND_4_A, 0x168e },
234 { WM8996_DSP1_RX_EQ_BAND_4_B, 0xf829 },
235 { WM8996_DSP1_RX_EQ_BAND_4_C, 0x7ad },
236 { WM8996_DSP1_RX_EQ_BAND_4_PG, 0x1103 },
237 { WM8996_DSP1_RX_EQ_BAND_5_A, 0x564 },
238 { WM8996_DSP1_RX_EQ_BAND_5_B, 0x559 },
239 { WM8996_DSP1_RX_EQ_BAND_5_PG, 0x4000 },
240 { WM8996_DSP2_TX_LEFT_VOLUME, 0xc0 },
241 { WM8996_DSP2_TX_RIGHT_VOLUME, 0xc0 },
242 { WM8996_DSP2_RX_LEFT_VOLUME, 0xc0 },
243 { WM8996_DSP2_RX_RIGHT_VOLUME, 0xc0 },
244 { WM8996_DSP2_TX_FILTERS, 0x2000 },
245 { WM8996_DSP2_RX_FILTERS_1, 0x200 },
246 { WM8996_DSP2_RX_FILTERS_2, 0x10 },
247 { WM8996_DSP2_DRC_1, 0x98 },
248 { WM8996_DSP2_DRC_2, 0x845 },
249 { WM8996_DSP2_RX_EQ_GAINS_1, 0x6318 },
250 { WM8996_DSP2_RX_EQ_GAINS_2, 0x6300 },
251 { WM8996_DSP2_RX_EQ_BAND_1_A, 0xfca },
252 { WM8996_DSP2_RX_EQ_BAND_1_B, 0x400 },
253 { WM8996_DSP2_RX_EQ_BAND_1_PG, 0xd8 },
254 { WM8996_DSP2_RX_EQ_BAND_2_A, 0x1eb5 },
255 { WM8996_DSP2_RX_EQ_BAND_2_B, 0xf145 },
256 { WM8996_DSP2_RX_EQ_BAND_2_C, 0xb75 },
257 { WM8996_DSP2_RX_EQ_BAND_2_PG, 0x1c5 },
258 { WM8996_DSP2_RX_EQ_BAND_3_A, 0x1c58 },
259 { WM8996_DSP2_RX_EQ_BAND_3_B, 0xf373 },
260 { WM8996_DSP2_RX_EQ_BAND_3_C, 0xa54 },
261 { WM8996_DSP2_RX_EQ_BAND_3_PG, 0x558 },
262 { WM8996_DSP2_RX_EQ_BAND_4_A, 0x168e },
263 { WM8996_DSP2_RX_EQ_BAND_4_B, 0xf829 },
264 { WM8996_DSP2_RX_EQ_BAND_4_C, 0x7ad },
265 { WM8996_DSP2_RX_EQ_BAND_4_PG, 0x1103 },
266 { WM8996_DSP2_RX_EQ_BAND_5_A, 0x564 },
267 { WM8996_DSP2_RX_EQ_BAND_5_B, 0x559 },
268 { WM8996_DSP2_RX_EQ_BAND_5_PG, 0x4000 },
269 { WM8996_DAC1_MIXER_VOLUMES, 0x0 },
270 { WM8996_DAC1_LEFT_MIXER_ROUTING, 0x0 },
271 { WM8996_DAC1_RIGHT_MIXER_ROUTING, 0x0 },
272 { WM8996_DAC2_MIXER_VOLUMES, 0x0 },
273 { WM8996_DAC2_LEFT_MIXER_ROUTING, 0x0 },
274 { WM8996_DAC2_RIGHT_MIXER_ROUTING, 0x0 },
275 { WM8996_DSP1_TX_LEFT_MIXER_ROUTING, 0x0 },
276 { WM8996_DSP1_TX_RIGHT_MIXER_ROUTING, 0x0 },
277 { WM8996_DSP2_TX_LEFT_MIXER_ROUTING, 0x0 },
278 { WM8996_DSP2_TX_RIGHT_MIXER_ROUTING, 0x0 },
279 { WM8996_DSP_TX_MIXER_SELECT, 0x0 },
280 { WM8996_DAC_SOFTMUTE, 0x0 },
281 { WM8996_OVERSAMPLING, 0xd },
282 { WM8996_SIDETONE, 0x1040 },
283 { WM8996_GPIO_1, 0xa101 },
284 { WM8996_GPIO_2, 0xa101 },
285 { WM8996_GPIO_3, 0xa101 },
286 { WM8996_GPIO_4, 0xa101 },
287 { WM8996_GPIO_5, 0xa101 },
288 { WM8996_PULL_CONTROL_1, 0x0 },
289 { WM8996_PULL_CONTROL_2, 0x140 },
290 { WM8996_INTERRUPT_STATUS_1_MASK, 0x1f },
291 { WM8996_INTERRUPT_STATUS_2_MASK, 0x1ecf },
292 { WM8996_LEFT_PDM_SPEAKER, 0x0 },
293 { WM8996_RIGHT_PDM_SPEAKER, 0x1 },
294 { WM8996_PDM_SPEAKER_MUTE_SEQUENCE, 0x69 },
295 { WM8996_PDM_SPEAKER_VOLUME, 0x66 },
296 };
297
298 static const DECLARE_TLV_DB_SCALE(inpga_tlv, 0, 100, 0);
299 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
300 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
301 static const DECLARE_TLV_DB_SCALE(out_digital_tlv, -1200, 150, 0);
302 static const DECLARE_TLV_DB_SCALE(out_tlv, -900, 75, 0);
303 static const DECLARE_TLV_DB_SCALE(spk_tlv, -900, 150, 0);
304 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
305 static const DECLARE_TLV_DB_SCALE(threedstereo_tlv, -1600, 183, 1);
306
307 static const char *sidetone_hpf_text[] = {
308 "2.9kHz", "1.5kHz", "735Hz", "403Hz", "196Hz", "98Hz", "49Hz"
309 };
310
311 static SOC_ENUM_SINGLE_DECL(sidetone_hpf,
312 WM8996_SIDETONE, 7, sidetone_hpf_text);
313
314 static const char *hpf_mode_text[] = {
315 "HiFi", "Custom", "Voice"
316 };
317
318 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_mode,
319 WM8996_DSP1_TX_FILTERS, 3, hpf_mode_text);
320
321 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_mode,
322 WM8996_DSP2_TX_FILTERS, 3, hpf_mode_text);
323
324 static const char *hpf_cutoff_text[] = {
325 "50Hz", "75Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz"
326 };
327
328 static SOC_ENUM_SINGLE_DECL(dsp1tx_hpf_cutoff,
329 WM8996_DSP1_TX_FILTERS, 0, hpf_cutoff_text);
330
331 static SOC_ENUM_SINGLE_DECL(dsp2tx_hpf_cutoff,
332 WM8996_DSP2_TX_FILTERS, 0, hpf_cutoff_text);
333
334 static void wm8996_set_retune_mobile(struct snd_soc_component *component, int block)
335 {
336 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
337 struct wm8996_pdata *pdata = &wm8996->pdata;
338 int base, best, best_val, save, i, cfg, iface;
339
340 if (!wm8996->num_retune_mobile_texts)
341 return;
342
343 switch (block) {
344 case 0:
345 base = WM8996_DSP1_RX_EQ_GAINS_1;
346 if (snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_8) &
347 WM8996_DSP1RX_SRC)
348 iface = 1;
349 else
350 iface = 0;
351 break;
352 case 1:
353 base = WM8996_DSP1_RX_EQ_GAINS_2;
354 if (snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_8) &
355 WM8996_DSP2RX_SRC)
356 iface = 1;
357 else
358 iface = 0;
359 break;
360 default:
361 return;
362 }
363
364 /* Find the version of the currently selected configuration
365 * with the nearest sample rate. */
366 cfg = wm8996->retune_mobile_cfg[block];
367 best = 0;
368 best_val = INT_MAX;
369 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
370 if (strcmp(pdata->retune_mobile_cfgs[i].name,
371 wm8996->retune_mobile_texts[cfg]) == 0 &&
372 abs(pdata->retune_mobile_cfgs[i].rate
373 - wm8996->rx_rate[iface]) < best_val) {
374 best = i;
375 best_val = abs(pdata->retune_mobile_cfgs[i].rate
376 - wm8996->rx_rate[iface]);
377 }
378 }
379
380 dev_dbg(component->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
381 block,
382 pdata->retune_mobile_cfgs[best].name,
383 pdata->retune_mobile_cfgs[best].rate,
384 wm8996->rx_rate[iface]);
385
386 /* The EQ will be disabled while reconfiguring it, remember the
387 * current configuration.
388 */
389 save = snd_soc_component_read(component, base);
390 save &= WM8996_DSP1RX_EQ_ENA;
391
392 for (i = 0; i < ARRAY_SIZE(pdata->retune_mobile_cfgs[best].regs); i++)
393 snd_soc_component_update_bits(component, base + i, 0xffff,
394 pdata->retune_mobile_cfgs[best].regs[i]);
395
396 snd_soc_component_update_bits(component, base, WM8996_DSP1RX_EQ_ENA, save);
397 }
398
399 /* Icky as hell but saves code duplication */
400 static int wm8996_get_retune_mobile_block(const char *name)
401 {
402 if (strcmp(name, "DSP1 EQ Mode") == 0)
403 return 0;
404 if (strcmp(name, "DSP2 EQ Mode") == 0)
405 return 1;
406 return -EINVAL;
407 }
408
409 static int wm8996_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
410 struct snd_ctl_elem_value *ucontrol)
411 {
412 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
413 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
414 struct wm8996_pdata *pdata = &wm8996->pdata;
415 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
416 int value = ucontrol->value.enumerated.item[0];
417
418 if (block < 0)
419 return block;
420
421 if (value >= pdata->num_retune_mobile_cfgs)
422 return -EINVAL;
423
424 wm8996->retune_mobile_cfg[block] = value;
425
426 wm8996_set_retune_mobile(component, block);
427
428 return 0;
429 }
430
431 static int wm8996_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
432 struct snd_ctl_elem_value *ucontrol)
433 {
434 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
435 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
436 int block = wm8996_get_retune_mobile_block(kcontrol->id.name);
437
438 if (block < 0)
439 return block;
440 ucontrol->value.enumerated.item[0] = wm8996->retune_mobile_cfg[block];
441
442 return 0;
443 }
444
445 static const struct snd_kcontrol_new wm8996_snd_controls[] = {
446 SOC_DOUBLE_R_TLV("Capture Volume", WM8996_LEFT_LINE_INPUT_VOLUME,
447 WM8996_RIGHT_LINE_INPUT_VOLUME, 0, 31, 0, inpga_tlv),
448 SOC_DOUBLE_R("Capture ZC Switch", WM8996_LEFT_LINE_INPUT_VOLUME,
449 WM8996_RIGHT_LINE_INPUT_VOLUME, 5, 1, 0),
450
451 SOC_DOUBLE_TLV("DAC1 Sidetone Volume", WM8996_DAC1_MIXER_VOLUMES,
452 0, 5, 24, 0, sidetone_tlv),
453 SOC_DOUBLE_TLV("DAC2 Sidetone Volume", WM8996_DAC2_MIXER_VOLUMES,
454 0, 5, 24, 0, sidetone_tlv),
455 SOC_SINGLE("Sidetone LPF Switch", WM8996_SIDETONE, 12, 1, 0),
456 SOC_ENUM("Sidetone HPF Cut-off", sidetone_hpf),
457 SOC_SINGLE("Sidetone HPF Switch", WM8996_SIDETONE, 6, 1, 0),
458
459 SOC_DOUBLE_R_TLV("DSP1 Capture Volume", WM8996_DSP1_TX_LEFT_VOLUME,
460 WM8996_DSP1_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
461 SOC_DOUBLE_R_TLV("DSP2 Capture Volume", WM8996_DSP2_TX_LEFT_VOLUME,
462 WM8996_DSP2_TX_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
463
464 SOC_SINGLE("DSP1 Capture Notch Filter Switch", WM8996_DSP1_TX_FILTERS,
465 13, 1, 0),
466 SOC_DOUBLE("DSP1 Capture HPF Switch", WM8996_DSP1_TX_FILTERS, 12, 11, 1, 0),
467 SOC_ENUM("DSP1 Capture HPF Mode", dsp1tx_hpf_mode),
468 SOC_ENUM("DSP1 Capture HPF Cutoff", dsp1tx_hpf_cutoff),
469
470 SOC_SINGLE("DSP2 Capture Notch Filter Switch", WM8996_DSP2_TX_FILTERS,
471 13, 1, 0),
472 SOC_DOUBLE("DSP2 Capture HPF Switch", WM8996_DSP2_TX_FILTERS, 12, 11, 1, 0),
473 SOC_ENUM("DSP2 Capture HPF Mode", dsp2tx_hpf_mode),
474 SOC_ENUM("DSP2 Capture HPF Cutoff", dsp2tx_hpf_cutoff),
475
476 SOC_DOUBLE_R_TLV("DSP1 Playback Volume", WM8996_DSP1_RX_LEFT_VOLUME,
477 WM8996_DSP1_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
478 SOC_SINGLE("DSP1 Playback Switch", WM8996_DSP1_RX_FILTERS_1, 9, 1, 1),
479
480 SOC_DOUBLE_R_TLV("DSP2 Playback Volume", WM8996_DSP2_RX_LEFT_VOLUME,
481 WM8996_DSP2_RX_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
482 SOC_SINGLE("DSP2 Playback Switch", WM8996_DSP2_RX_FILTERS_1, 9, 1, 1),
483
484 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8996_DAC1_LEFT_VOLUME,
485 WM8996_DAC1_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
486 SOC_DOUBLE_R("DAC1 Switch", WM8996_DAC1_LEFT_VOLUME,
487 WM8996_DAC1_RIGHT_VOLUME, 9, 1, 1),
488
489 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8996_DAC2_LEFT_VOLUME,
490 WM8996_DAC2_RIGHT_VOLUME, 1, 112, 0, digital_tlv),
491 SOC_DOUBLE_R("DAC2 Switch", WM8996_DAC2_LEFT_VOLUME,
492 WM8996_DAC2_RIGHT_VOLUME, 9, 1, 1),
493
494 SOC_SINGLE("Speaker High Performance Switch", WM8996_OVERSAMPLING, 3, 1, 0),
495 SOC_SINGLE("DMIC High Performance Switch", WM8996_OVERSAMPLING, 2, 1, 0),
496 SOC_SINGLE("ADC High Performance Switch", WM8996_OVERSAMPLING, 1, 1, 0),
497 SOC_SINGLE("DAC High Performance Switch", WM8996_OVERSAMPLING, 0, 1, 0),
498
499 SOC_SINGLE("DAC Soft Mute Switch", WM8996_DAC_SOFTMUTE, 1, 1, 0),
500 SOC_SINGLE("DAC Slow Soft Mute Switch", WM8996_DAC_SOFTMUTE, 0, 1, 0),
501
502 SOC_SINGLE("DSP1 3D Stereo Switch", WM8996_DSP1_RX_FILTERS_2, 8, 1, 0),
503 SOC_SINGLE("DSP2 3D Stereo Switch", WM8996_DSP2_RX_FILTERS_2, 8, 1, 0),
504
505 SOC_SINGLE_TLV("DSP1 3D Stereo Volume", WM8996_DSP1_RX_FILTERS_2, 10, 15,
506 0, threedstereo_tlv),
507 SOC_SINGLE_TLV("DSP2 3D Stereo Volume", WM8996_DSP2_RX_FILTERS_2, 10, 15,
508 0, threedstereo_tlv),
509
510 SOC_DOUBLE_TLV("Digital Output 1 Volume", WM8996_DAC1_HPOUT1_VOLUME, 0, 4,
511 8, 0, out_digital_tlv),
512 SOC_DOUBLE_TLV("Digital Output 2 Volume", WM8996_DAC2_HPOUT2_VOLUME, 0, 4,
513 8, 0, out_digital_tlv),
514
515 SOC_DOUBLE_R_TLV("Output 1 Volume", WM8996_OUTPUT1_LEFT_VOLUME,
516 WM8996_OUTPUT1_RIGHT_VOLUME, 0, 12, 0, out_tlv),
517 SOC_DOUBLE_R("Output 1 ZC Switch", WM8996_OUTPUT1_LEFT_VOLUME,
518 WM8996_OUTPUT1_RIGHT_VOLUME, 7, 1, 0),
519
520 SOC_DOUBLE_R_TLV("Output 2 Volume", WM8996_OUTPUT2_LEFT_VOLUME,
521 WM8996_OUTPUT2_RIGHT_VOLUME, 0, 12, 0, out_tlv),
522 SOC_DOUBLE_R("Output 2 ZC Switch", WM8996_OUTPUT2_LEFT_VOLUME,
523 WM8996_OUTPUT2_RIGHT_VOLUME, 7, 1, 0),
524
525 SOC_DOUBLE_TLV("Speaker Volume", WM8996_PDM_SPEAKER_VOLUME, 0, 4, 8, 0,
526 spk_tlv),
527 SOC_DOUBLE_R("Speaker Switch", WM8996_LEFT_PDM_SPEAKER,
528 WM8996_RIGHT_PDM_SPEAKER, 3, 1, 1),
529 SOC_DOUBLE_R("Speaker ZC Switch", WM8996_LEFT_PDM_SPEAKER,
530 WM8996_RIGHT_PDM_SPEAKER, 2, 1, 0),
531
532 SOC_SINGLE("DSP1 EQ Switch", WM8996_DSP1_RX_EQ_GAINS_1, 0, 1, 0),
533 SOC_SINGLE("DSP2 EQ Switch", WM8996_DSP2_RX_EQ_GAINS_1, 0, 1, 0),
534
535 SOC_SINGLE("DSP1 DRC TXL Switch", WM8996_DSP1_DRC_1, 0, 1, 0),
536 SOC_SINGLE("DSP1 DRC TXR Switch", WM8996_DSP1_DRC_1, 1, 1, 0),
537 SOC_SINGLE("DSP1 DRC RX Switch", WM8996_DSP1_DRC_1, 2, 1, 0),
538 SND_SOC_BYTES_MASK("DSP1 DRC", WM8996_DSP1_DRC_1, 5,
539 WM8996_DSP1RX_DRC_ENA | WM8996_DSP1TXL_DRC_ENA |
540 WM8996_DSP1TXR_DRC_ENA),
541
542 SOC_SINGLE("DSP2 DRC TXL Switch", WM8996_DSP2_DRC_1, 0, 1, 0),
543 SOC_SINGLE("DSP2 DRC TXR Switch", WM8996_DSP2_DRC_1, 1, 1, 0),
544 SOC_SINGLE("DSP2 DRC RX Switch", WM8996_DSP2_DRC_1, 2, 1, 0),
545 SND_SOC_BYTES_MASK("DSP2 DRC", WM8996_DSP2_DRC_1, 5,
546 WM8996_DSP2RX_DRC_ENA | WM8996_DSP2TXL_DRC_ENA |
547 WM8996_DSP2TXR_DRC_ENA),
548 };
549
550 static const struct snd_kcontrol_new wm8996_eq_controls[] = {
551 SOC_SINGLE_TLV("DSP1 EQ B1 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 11, 31, 0,
552 eq_tlv),
553 SOC_SINGLE_TLV("DSP1 EQ B2 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 6, 31, 0,
554 eq_tlv),
555 SOC_SINGLE_TLV("DSP1 EQ B3 Volume", WM8996_DSP1_RX_EQ_GAINS_1, 1, 31, 0,
556 eq_tlv),
557 SOC_SINGLE_TLV("DSP1 EQ B4 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 11, 31, 0,
558 eq_tlv),
559 SOC_SINGLE_TLV("DSP1 EQ B5 Volume", WM8996_DSP1_RX_EQ_GAINS_2, 6, 31, 0,
560 eq_tlv),
561
562 SOC_SINGLE_TLV("DSP2 EQ B1 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 11, 31, 0,
563 eq_tlv),
564 SOC_SINGLE_TLV("DSP2 EQ B2 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 6, 31, 0,
565 eq_tlv),
566 SOC_SINGLE_TLV("DSP2 EQ B3 Volume", WM8996_DSP2_RX_EQ_GAINS_1, 1, 31, 0,
567 eq_tlv),
568 SOC_SINGLE_TLV("DSP2 EQ B4 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 11, 31, 0,
569 eq_tlv),
570 SOC_SINGLE_TLV("DSP2 EQ B5 Volume", WM8996_DSP2_RX_EQ_GAINS_2, 6, 31, 0,
571 eq_tlv),
572 };
573
574 static void wm8996_bg_enable(struct snd_soc_component *component)
575 {
576 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
577
578 wm8996->bg_ena++;
579 if (wm8996->bg_ena == 1) {
580 snd_soc_component_update_bits(component, WM8996_POWER_MANAGEMENT_1,
581 WM8996_BG_ENA, WM8996_BG_ENA);
582 msleep(2);
583 }
584 }
585
586 static void wm8996_bg_disable(struct snd_soc_component *component)
587 {
588 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
589
590 wm8996->bg_ena--;
591 if (!wm8996->bg_ena)
592 snd_soc_component_update_bits(component, WM8996_POWER_MANAGEMENT_1,
593 WM8996_BG_ENA, 0);
594 }
595
596 static int bg_event(struct snd_soc_dapm_widget *w,
597 struct snd_kcontrol *kcontrol, int event)
598 {
599 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
600 int ret = 0;
601
602 switch (event) {
603 case SND_SOC_DAPM_PRE_PMU:
604 wm8996_bg_enable(component);
605 break;
606 case SND_SOC_DAPM_POST_PMD:
607 wm8996_bg_disable(component);
608 break;
609 default:
610 WARN(1, "Invalid event %d\n", event);
611 ret = -EINVAL;
612 }
613
614 return ret;
615 }
616
617 static int cp_event(struct snd_soc_dapm_widget *w,
618 struct snd_kcontrol *kcontrol, int event)
619 {
620 switch (event) {
621 case SND_SOC_DAPM_POST_PMU:
622 msleep(5);
623 break;
624 default:
625 WARN(1, "Invalid event %d\n", event);
626 }
627
628 return 0;
629 }
630
631 static int rmv_short_event(struct snd_soc_dapm_widget *w,
632 struct snd_kcontrol *kcontrol, int event)
633 {
634 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
635 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
636
637 /* Record which outputs we enabled */
638 switch (event) {
639 case SND_SOC_DAPM_PRE_PMD:
640 wm8996->hpout_pending &= ~w->shift;
641 break;
642 case SND_SOC_DAPM_PRE_PMU:
643 wm8996->hpout_pending |= w->shift;
644 break;
645 default:
646 WARN(1, "Invalid event %d\n", event);
647 return -EINVAL;
648 }
649
650 return 0;
651 }
652
653 static void wait_for_dc_servo(struct snd_soc_component *component, u16 mask)
654 {
655 struct i2c_client *i2c = to_i2c_client(component->dev);
656 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
657 int ret;
658 unsigned long timeout = 200;
659
660 snd_soc_component_write(component, WM8996_DC_SERVO_2, mask);
661
662 /* Use the interrupt if possible */
663 do {
664 if (i2c->irq) {
665 timeout = wait_for_completion_timeout(&wm8996->dcs_done,
666 msecs_to_jiffies(200));
667 if (timeout == 0)
668 dev_err(component->dev, "DC servo timed out\n");
669
670 } else {
671 msleep(1);
672 timeout--;
673 }
674
675 ret = snd_soc_component_read(component, WM8996_DC_SERVO_2);
676 dev_dbg(component->dev, "DC servo state: %x\n", ret);
677 } while (timeout && ret & mask);
678
679 if (timeout == 0)
680 dev_err(component->dev, "DC servo timed out for %x\n", mask);
681 else
682 dev_dbg(component->dev, "DC servo complete for %x\n", mask);
683 }
684
685 static void wm8996_seq_notifier(struct snd_soc_component *component,
686 enum snd_soc_dapm_type event, int subseq)
687 {
688 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
689 u16 val, mask;
690
691 /* Complete any pending DC servo starts */
692 if (wm8996->dcs_pending) {
693 dev_dbg(component->dev, "Starting DC servo for %x\n",
694 wm8996->dcs_pending);
695
696 /* Trigger a startup sequence */
697 wait_for_dc_servo(component, wm8996->dcs_pending
698 << WM8996_DCS_TRIG_STARTUP_0_SHIFT);
699
700 wm8996->dcs_pending = 0;
701 }
702
703 if (wm8996->hpout_pending != wm8996->hpout_ena) {
704 dev_dbg(component->dev, "Applying RMV_SHORTs %x->%x\n",
705 wm8996->hpout_ena, wm8996->hpout_pending);
706
707 val = 0;
708 mask = 0;
709 if (wm8996->hpout_pending & HPOUT1L) {
710 val |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
711 mask |= WM8996_HPOUT1L_RMV_SHORT | WM8996_HPOUT1L_OUTP;
712 } else {
713 mask |= WM8996_HPOUT1L_RMV_SHORT |
714 WM8996_HPOUT1L_OUTP |
715 WM8996_HPOUT1L_DLY;
716 }
717
718 if (wm8996->hpout_pending & HPOUT1R) {
719 val |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
720 mask |= WM8996_HPOUT1R_RMV_SHORT | WM8996_HPOUT1R_OUTP;
721 } else {
722 mask |= WM8996_HPOUT1R_RMV_SHORT |
723 WM8996_HPOUT1R_OUTP |
724 WM8996_HPOUT1R_DLY;
725 }
726
727 snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1, mask, val);
728
729 val = 0;
730 mask = 0;
731 if (wm8996->hpout_pending & HPOUT2L) {
732 val |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
733 mask |= WM8996_HPOUT2L_RMV_SHORT | WM8996_HPOUT2L_OUTP;
734 } else {
735 mask |= WM8996_HPOUT2L_RMV_SHORT |
736 WM8996_HPOUT2L_OUTP |
737 WM8996_HPOUT2L_DLY;
738 }
739
740 if (wm8996->hpout_pending & HPOUT2R) {
741 val |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
742 mask |= WM8996_HPOUT2R_RMV_SHORT | WM8996_HPOUT2R_OUTP;
743 } else {
744 mask |= WM8996_HPOUT2R_RMV_SHORT |
745 WM8996_HPOUT2R_OUTP |
746 WM8996_HPOUT2R_DLY;
747 }
748
749 snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_2, mask, val);
750
751 wm8996->hpout_ena = wm8996->hpout_pending;
752 }
753 }
754
755 static int dcs_start(struct snd_soc_dapm_widget *w,
756 struct snd_kcontrol *kcontrol, int event)
757 {
758 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
759 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
760
761 switch (event) {
762 case SND_SOC_DAPM_POST_PMU:
763 wm8996->dcs_pending |= 1 << w->shift;
764 break;
765 default:
766 WARN(1, "Invalid event %d\n", event);
767 return -EINVAL;
768 }
769
770 return 0;
771 }
772
773 static const char *sidetone_text[] = {
774 "IN1", "IN2",
775 };
776
777 static SOC_ENUM_SINGLE_DECL(left_sidetone_enum,
778 WM8996_SIDETONE, 0, sidetone_text);
779
780 static const struct snd_kcontrol_new left_sidetone =
781 SOC_DAPM_ENUM("Left Sidetone", left_sidetone_enum);
782
783 static SOC_ENUM_SINGLE_DECL(right_sidetone_enum,
784 WM8996_SIDETONE, 1, sidetone_text);
785
786 static const struct snd_kcontrol_new right_sidetone =
787 SOC_DAPM_ENUM("Right Sidetone", right_sidetone_enum);
788
789 static const char *spk_text[] = {
790 "DAC1L", "DAC1R", "DAC2L", "DAC2R"
791 };
792
793 static SOC_ENUM_SINGLE_DECL(spkl_enum,
794 WM8996_LEFT_PDM_SPEAKER, 0, spk_text);
795
796 static const struct snd_kcontrol_new spkl_mux =
797 SOC_DAPM_ENUM("SPKL", spkl_enum);
798
799 static SOC_ENUM_SINGLE_DECL(spkr_enum,
800 WM8996_RIGHT_PDM_SPEAKER, 0, spk_text);
801
802 static const struct snd_kcontrol_new spkr_mux =
803 SOC_DAPM_ENUM("SPKR", spkr_enum);
804
805 static const char *dsp1rx_text[] = {
806 "AIF1", "AIF2"
807 };
808
809 static SOC_ENUM_SINGLE_DECL(dsp1rx_enum,
810 WM8996_POWER_MANAGEMENT_8, 0, dsp1rx_text);
811
812 static const struct snd_kcontrol_new dsp1rx =
813 SOC_DAPM_ENUM("DSP1RX", dsp1rx_enum);
814
815 static const char *dsp2rx_text[] = {
816 "AIF2", "AIF1"
817 };
818
819 static SOC_ENUM_SINGLE_DECL(dsp2rx_enum,
820 WM8996_POWER_MANAGEMENT_8, 4, dsp2rx_text);
821
822 static const struct snd_kcontrol_new dsp2rx =
823 SOC_DAPM_ENUM("DSP2RX", dsp2rx_enum);
824
825 static const char *aif2tx_text[] = {
826 "DSP2", "DSP1", "AIF1"
827 };
828
829 static SOC_ENUM_SINGLE_DECL(aif2tx_enum,
830 WM8996_POWER_MANAGEMENT_8, 6, aif2tx_text);
831
832 static const struct snd_kcontrol_new aif2tx =
833 SOC_DAPM_ENUM("AIF2TX", aif2tx_enum);
834
835 static const char *inmux_text[] = {
836 "ADC", "DMIC1", "DMIC2"
837 };
838
839 static SOC_ENUM_SINGLE_DECL(in1_enum,
840 WM8996_POWER_MANAGEMENT_7, 0, inmux_text);
841
842 static const struct snd_kcontrol_new in1_mux =
843 SOC_DAPM_ENUM("IN1 Mux", in1_enum);
844
845 static SOC_ENUM_SINGLE_DECL(in2_enum,
846 WM8996_POWER_MANAGEMENT_7, 4, inmux_text);
847
848 static const struct snd_kcontrol_new in2_mux =
849 SOC_DAPM_ENUM("IN2 Mux", in2_enum);
850
851 static const struct snd_kcontrol_new dac2r_mix[] = {
852 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
853 5, 1, 0),
854 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING,
855 4, 1, 0),
856 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 1, 1, 0),
857 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_RIGHT_MIXER_ROUTING, 0, 1, 0),
858 };
859
860 static const struct snd_kcontrol_new dac2l_mix[] = {
861 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
862 5, 1, 0),
863 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC2_LEFT_MIXER_ROUTING,
864 4, 1, 0),
865 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 1, 1, 0),
866 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC2_LEFT_MIXER_ROUTING, 0, 1, 0),
867 };
868
869 static const struct snd_kcontrol_new dac1r_mix[] = {
870 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
871 5, 1, 0),
872 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING,
873 4, 1, 0),
874 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 1, 1, 0),
875 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_RIGHT_MIXER_ROUTING, 0, 1, 0),
876 };
877
878 static const struct snd_kcontrol_new dac1l_mix[] = {
879 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
880 5, 1, 0),
881 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8996_DAC1_LEFT_MIXER_ROUTING,
882 4, 1, 0),
883 SOC_DAPM_SINGLE("DSP2 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 1, 1, 0),
884 SOC_DAPM_SINGLE("DSP1 Switch", WM8996_DAC1_LEFT_MIXER_ROUTING, 0, 1, 0),
885 };
886
887 static const struct snd_kcontrol_new dsp1txl[] = {
888 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
889 1, 1, 0),
890 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_LEFT_MIXER_ROUTING,
891 0, 1, 0),
892 };
893
894 static const struct snd_kcontrol_new dsp1txr[] = {
895 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
896 1, 1, 0),
897 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP1_TX_RIGHT_MIXER_ROUTING,
898 0, 1, 0),
899 };
900
901 static const struct snd_kcontrol_new dsp2txl[] = {
902 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
903 1, 1, 0),
904 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_LEFT_MIXER_ROUTING,
905 0, 1, 0),
906 };
907
908 static const struct snd_kcontrol_new dsp2txr[] = {
909 SOC_DAPM_SINGLE("IN1 Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
910 1, 1, 0),
911 SOC_DAPM_SINGLE("DAC Switch", WM8996_DSP2_TX_RIGHT_MIXER_ROUTING,
912 0, 1, 0),
913 };
914
915
916 static const struct snd_soc_dapm_widget wm8996_dapm_widgets[] = {
917 SND_SOC_DAPM_INPUT("IN1LN"),
918 SND_SOC_DAPM_INPUT("IN1LP"),
919 SND_SOC_DAPM_INPUT("IN1RN"),
920 SND_SOC_DAPM_INPUT("IN1RP"),
921
922 SND_SOC_DAPM_INPUT("IN2LN"),
923 SND_SOC_DAPM_INPUT("IN2LP"),
924 SND_SOC_DAPM_INPUT("IN2RN"),
925 SND_SOC_DAPM_INPUT("IN2RP"),
926
927 SND_SOC_DAPM_INPUT("DMIC1DAT"),
928 SND_SOC_DAPM_INPUT("DMIC2DAT"),
929
930 SND_SOC_DAPM_REGULATOR_SUPPLY("CPVDD", 20, 0),
931 SND_SOC_DAPM_SUPPLY_S("SYSCLK", 1, WM8996_AIF_CLOCKING_1, 0, 0, NULL, 0),
932 SND_SOC_DAPM_SUPPLY_S("SYSDSPCLK", 2, WM8996_CLOCKING_1, 1, 0, NULL, 0),
933 SND_SOC_DAPM_SUPPLY_S("AIFCLK", 2, WM8996_CLOCKING_1, 2, 0, NULL, 0),
934 SND_SOC_DAPM_SUPPLY_S("Charge Pump", 2, WM8996_CHARGE_PUMP_1, 15, 0, cp_event,
935 SND_SOC_DAPM_POST_PMU),
936 SND_SOC_DAPM_SUPPLY("Bandgap", SND_SOC_NOPM, 0, 0, bg_event,
937 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
938 SND_SOC_DAPM_SUPPLY("LDO2", WM8996_POWER_MANAGEMENT_2, 1, 0, NULL, 0),
939 SND_SOC_DAPM_SUPPLY("MICB1 Audio", WM8996_MICBIAS_1, 4, 1, NULL, 0),
940 SND_SOC_DAPM_SUPPLY("MICB2 Audio", WM8996_MICBIAS_2, 4, 1, NULL, 0),
941 SND_SOC_DAPM_MICBIAS("MICB2", WM8996_POWER_MANAGEMENT_1, 9, 0),
942 SND_SOC_DAPM_MICBIAS("MICB1", WM8996_POWER_MANAGEMENT_1, 8, 0),
943
944 SND_SOC_DAPM_PGA("IN1L PGA", WM8996_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
945 SND_SOC_DAPM_PGA("IN1R PGA", WM8996_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
946
947 SND_SOC_DAPM_MUX("IN1L Mux", WM8996_POWER_MANAGEMENT_7, 2, 0, &in1_mux),
948 SND_SOC_DAPM_MUX("IN1R Mux", WM8996_POWER_MANAGEMENT_7, 3, 0, &in1_mux),
949 SND_SOC_DAPM_MUX("IN2L Mux", WM8996_POWER_MANAGEMENT_7, 6, 0, &in2_mux),
950 SND_SOC_DAPM_MUX("IN2R Mux", WM8996_POWER_MANAGEMENT_7, 7, 0, &in2_mux),
951
952 SND_SOC_DAPM_SUPPLY("DMIC2", WM8996_POWER_MANAGEMENT_7, 9, 0, NULL, 0),
953 SND_SOC_DAPM_SUPPLY("DMIC1", WM8996_POWER_MANAGEMENT_7, 8, 0, NULL, 0),
954
955 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8996_POWER_MANAGEMENT_3, 5, 0),
956 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8996_POWER_MANAGEMENT_3, 4, 0),
957 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8996_POWER_MANAGEMENT_3, 3, 0),
958 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8996_POWER_MANAGEMENT_3, 2, 0),
959
960 SND_SOC_DAPM_ADC("ADCL", NULL, WM8996_POWER_MANAGEMENT_3, 1, 0),
961 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
962
963 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &left_sidetone),
964 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &right_sidetone),
965
966 SND_SOC_DAPM_AIF_IN("DSP2RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 11, 0),
967 SND_SOC_DAPM_AIF_IN("DSP2RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 10, 0),
968 SND_SOC_DAPM_AIF_IN("DSP1RXL", NULL, 0, WM8996_POWER_MANAGEMENT_3, 9, 0),
969 SND_SOC_DAPM_AIF_IN("DSP1RXR", NULL, 1, WM8996_POWER_MANAGEMENT_3, 8, 0),
970
971 SND_SOC_DAPM_MIXER("DSP2TXL", WM8996_POWER_MANAGEMENT_5, 11, 0,
972 dsp2txl, ARRAY_SIZE(dsp2txl)),
973 SND_SOC_DAPM_MIXER("DSP2TXR", WM8996_POWER_MANAGEMENT_5, 10, 0,
974 dsp2txr, ARRAY_SIZE(dsp2txr)),
975 SND_SOC_DAPM_MIXER("DSP1TXL", WM8996_POWER_MANAGEMENT_5, 9, 0,
976 dsp1txl, ARRAY_SIZE(dsp1txl)),
977 SND_SOC_DAPM_MIXER("DSP1TXR", WM8996_POWER_MANAGEMENT_5, 8, 0,
978 dsp1txr, ARRAY_SIZE(dsp1txr)),
979
980 SND_SOC_DAPM_MIXER("DAC2L Mixer", SND_SOC_NOPM, 0, 0,
981 dac2l_mix, ARRAY_SIZE(dac2l_mix)),
982 SND_SOC_DAPM_MIXER("DAC2R Mixer", SND_SOC_NOPM, 0, 0,
983 dac2r_mix, ARRAY_SIZE(dac2r_mix)),
984 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
985 dac1l_mix, ARRAY_SIZE(dac1l_mix)),
986 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
987 dac1r_mix, ARRAY_SIZE(dac1r_mix)),
988
989 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8996_POWER_MANAGEMENT_5, 3, 0),
990 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8996_POWER_MANAGEMENT_5, 2, 0),
991 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8996_POWER_MANAGEMENT_5, 1, 0),
992 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8996_POWER_MANAGEMENT_5, 0, 0),
993
994 SND_SOC_DAPM_AIF_IN("AIF2RX1", NULL, 0, WM8996_POWER_MANAGEMENT_4, 9, 0),
995 SND_SOC_DAPM_AIF_IN("AIF2RX0", NULL, 1, WM8996_POWER_MANAGEMENT_4, 8, 0),
996
997 SND_SOC_DAPM_AIF_OUT("AIF2TX1", NULL, 0, WM8996_POWER_MANAGEMENT_6, 9, 0),
998 SND_SOC_DAPM_AIF_OUT("AIF2TX0", NULL, 1, WM8996_POWER_MANAGEMENT_6, 8, 0),
999
1000 SND_SOC_DAPM_AIF_IN("AIF1RX5", NULL, 5, WM8996_POWER_MANAGEMENT_4, 5, 0),
1001 SND_SOC_DAPM_AIF_IN("AIF1RX4", NULL, 4, WM8996_POWER_MANAGEMENT_4, 4, 0),
1002 SND_SOC_DAPM_AIF_IN("AIF1RX3", NULL, 3, WM8996_POWER_MANAGEMENT_4, 3, 0),
1003 SND_SOC_DAPM_AIF_IN("AIF1RX2", NULL, 2, WM8996_POWER_MANAGEMENT_4, 2, 0),
1004 SND_SOC_DAPM_AIF_IN("AIF1RX1", NULL, 1, WM8996_POWER_MANAGEMENT_4, 1, 0),
1005 SND_SOC_DAPM_AIF_IN("AIF1RX0", NULL, 0, WM8996_POWER_MANAGEMENT_4, 0, 0),
1006
1007 SND_SOC_DAPM_AIF_OUT("AIF1TX5", NULL, 5, WM8996_POWER_MANAGEMENT_6, 5, 0),
1008 SND_SOC_DAPM_AIF_OUT("AIF1TX4", NULL, 4, WM8996_POWER_MANAGEMENT_6, 4, 0),
1009 SND_SOC_DAPM_AIF_OUT("AIF1TX3", NULL, 3, WM8996_POWER_MANAGEMENT_6, 3, 0),
1010 SND_SOC_DAPM_AIF_OUT("AIF1TX2", NULL, 2, WM8996_POWER_MANAGEMENT_6, 2, 0),
1011 SND_SOC_DAPM_AIF_OUT("AIF1TX1", NULL, 1, WM8996_POWER_MANAGEMENT_6, 1, 0),
1012 SND_SOC_DAPM_AIF_OUT("AIF1TX0", NULL, 0, WM8996_POWER_MANAGEMENT_6, 0, 0),
1013
1014 /* We route as stereo pairs so define some dummy widgets to squash
1015 * things down for now. RXA = 0,1, RXB = 2,3 and so on */
1016 SND_SOC_DAPM_PGA("AIF1RXA", SND_SOC_NOPM, 0, 0, NULL, 0),
1017 SND_SOC_DAPM_PGA("AIF1RXB", SND_SOC_NOPM, 0, 0, NULL, 0),
1018 SND_SOC_DAPM_PGA("AIF1RXC", SND_SOC_NOPM, 0, 0, NULL, 0),
1019 SND_SOC_DAPM_PGA("AIF2RX", SND_SOC_NOPM, 0, 0, NULL, 0),
1020 SND_SOC_DAPM_PGA("DSP2TX", SND_SOC_NOPM, 0, 0, NULL, 0),
1021
1022 SND_SOC_DAPM_MUX("DSP1RX", SND_SOC_NOPM, 0, 0, &dsp1rx),
1023 SND_SOC_DAPM_MUX("DSP2RX", SND_SOC_NOPM, 0, 0, &dsp2rx),
1024 SND_SOC_DAPM_MUX("AIF2TX", SND_SOC_NOPM, 0, 0, &aif2tx),
1025
1026 SND_SOC_DAPM_MUX("SPKL", SND_SOC_NOPM, 0, 0, &spkl_mux),
1027 SND_SOC_DAPM_MUX("SPKR", SND_SOC_NOPM, 0, 0, &spkr_mux),
1028 SND_SOC_DAPM_PGA("SPKL PGA", WM8996_LEFT_PDM_SPEAKER, 4, 0, NULL, 0),
1029 SND_SOC_DAPM_PGA("SPKR PGA", WM8996_RIGHT_PDM_SPEAKER, 4, 0, NULL, 0),
1030
1031 SND_SOC_DAPM_PGA_S("HPOUT2L PGA", 0, WM8996_POWER_MANAGEMENT_1, 7, 0, NULL, 0),
1032 SND_SOC_DAPM_PGA_S("HPOUT2L_DLY", 1, WM8996_ANALOGUE_HP_2, 5, 0, NULL, 0),
1033 SND_SOC_DAPM_PGA_S("HPOUT2L_DCS", 2, WM8996_DC_SERVO_1, 2, 0, dcs_start,
1034 SND_SOC_DAPM_POST_PMU),
1035 SND_SOC_DAPM_PGA_S("HPOUT2L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2L, 0,
1036 rmv_short_event,
1037 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1038
1039 SND_SOC_DAPM_PGA_S("HPOUT2R PGA", 0, WM8996_POWER_MANAGEMENT_1, 6, 0,NULL, 0),
1040 SND_SOC_DAPM_PGA_S("HPOUT2R_DLY", 1, WM8996_ANALOGUE_HP_2, 1, 0, NULL, 0),
1041 SND_SOC_DAPM_PGA_S("HPOUT2R_DCS", 2, WM8996_DC_SERVO_1, 3, 0, dcs_start,
1042 SND_SOC_DAPM_POST_PMU),
1043 SND_SOC_DAPM_PGA_S("HPOUT2R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT2R, 0,
1044 rmv_short_event,
1045 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1046
1047 SND_SOC_DAPM_PGA_S("HPOUT1L PGA", 0, WM8996_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
1048 SND_SOC_DAPM_PGA_S("HPOUT1L_DLY", 1, WM8996_ANALOGUE_HP_1, 5, 0, NULL, 0),
1049 SND_SOC_DAPM_PGA_S("HPOUT1L_DCS", 2, WM8996_DC_SERVO_1, 0, 0, dcs_start,
1050 SND_SOC_DAPM_POST_PMU),
1051 SND_SOC_DAPM_PGA_S("HPOUT1L_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1L, 0,
1052 rmv_short_event,
1053 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1054
1055 SND_SOC_DAPM_PGA_S("HPOUT1R PGA", 0, WM8996_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
1056 SND_SOC_DAPM_PGA_S("HPOUT1R_DLY", 1, WM8996_ANALOGUE_HP_1, 1, 0, NULL, 0),
1057 SND_SOC_DAPM_PGA_S("HPOUT1R_DCS", 2, WM8996_DC_SERVO_1, 1, 0, dcs_start,
1058 SND_SOC_DAPM_POST_PMU),
1059 SND_SOC_DAPM_PGA_S("HPOUT1R_RMV_SHORT", 3, SND_SOC_NOPM, HPOUT1R, 0,
1060 rmv_short_event,
1061 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
1062
1063 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1064 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1065 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1066 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1067 SND_SOC_DAPM_OUTPUT("SPKDAT"),
1068 };
1069
1070 static const struct snd_soc_dapm_route wm8996_dapm_routes[] = {
1071 { "AIFCLK", NULL, "SYSCLK" },
1072 { "SYSDSPCLK", NULL, "SYSCLK" },
1073 { "Charge Pump", NULL, "SYSCLK" },
1074 { "Charge Pump", NULL, "CPVDD" },
1075
1076 { "MICB1", NULL, "LDO2" },
1077 { "MICB1", NULL, "MICB1 Audio" },
1078 { "MICB1", NULL, "Bandgap" },
1079 { "MICB2", NULL, "LDO2" },
1080 { "MICB2", NULL, "MICB2 Audio" },
1081 { "MICB2", NULL, "Bandgap" },
1082
1083 { "AIF1RX0", NULL, "AIF1 Playback" },
1084 { "AIF1RX1", NULL, "AIF1 Playback" },
1085 { "AIF1RX2", NULL, "AIF1 Playback" },
1086 { "AIF1RX3", NULL, "AIF1 Playback" },
1087 { "AIF1RX4", NULL, "AIF1 Playback" },
1088 { "AIF1RX5", NULL, "AIF1 Playback" },
1089
1090 { "AIF2RX0", NULL, "AIF2 Playback" },
1091 { "AIF2RX1", NULL, "AIF2 Playback" },
1092
1093 { "AIF1 Capture", NULL, "AIF1TX0" },
1094 { "AIF1 Capture", NULL, "AIF1TX1" },
1095 { "AIF1 Capture", NULL, "AIF1TX2" },
1096 { "AIF1 Capture", NULL, "AIF1TX3" },
1097 { "AIF1 Capture", NULL, "AIF1TX4" },
1098 { "AIF1 Capture", NULL, "AIF1TX5" },
1099
1100 { "AIF2 Capture", NULL, "AIF2TX0" },
1101 { "AIF2 Capture", NULL, "AIF2TX1" },
1102
1103 { "IN1L PGA", NULL, "IN2LN" },
1104 { "IN1L PGA", NULL, "IN2LP" },
1105 { "IN1L PGA", NULL, "IN1LN" },
1106 { "IN1L PGA", NULL, "IN1LP" },
1107 { "IN1L PGA", NULL, "Bandgap" },
1108
1109 { "IN1R PGA", NULL, "IN2RN" },
1110 { "IN1R PGA", NULL, "IN2RP" },
1111 { "IN1R PGA", NULL, "IN1RN" },
1112 { "IN1R PGA", NULL, "IN1RP" },
1113 { "IN1R PGA", NULL, "Bandgap" },
1114
1115 { "ADCL", NULL, "IN1L PGA" },
1116
1117 { "ADCR", NULL, "IN1R PGA" },
1118
1119 { "DMIC1L", NULL, "DMIC1DAT" },
1120 { "DMIC1R", NULL, "DMIC1DAT" },
1121 { "DMIC2L", NULL, "DMIC2DAT" },
1122 { "DMIC2R", NULL, "DMIC2DAT" },
1123
1124 { "DMIC2L", NULL, "DMIC2" },
1125 { "DMIC2R", NULL, "DMIC2" },
1126 { "DMIC1L", NULL, "DMIC1" },
1127 { "DMIC1R", NULL, "DMIC1" },
1128
1129 { "IN1L Mux", "ADC", "ADCL" },
1130 { "IN1L Mux", "DMIC1", "DMIC1L" },
1131 { "IN1L Mux", "DMIC2", "DMIC2L" },
1132
1133 { "IN1R Mux", "ADC", "ADCR" },
1134 { "IN1R Mux", "DMIC1", "DMIC1R" },
1135 { "IN1R Mux", "DMIC2", "DMIC2R" },
1136
1137 { "IN2L Mux", "ADC", "ADCL" },
1138 { "IN2L Mux", "DMIC1", "DMIC1L" },
1139 { "IN2L Mux", "DMIC2", "DMIC2L" },
1140
1141 { "IN2R Mux", "ADC", "ADCR" },
1142 { "IN2R Mux", "DMIC1", "DMIC1R" },
1143 { "IN2R Mux", "DMIC2", "DMIC2R" },
1144
1145 { "Left Sidetone", "IN1", "IN1L Mux" },
1146 { "Left Sidetone", "IN2", "IN2L Mux" },
1147
1148 { "Right Sidetone", "IN1", "IN1R Mux" },
1149 { "Right Sidetone", "IN2", "IN2R Mux" },
1150
1151 { "DSP1TXL", "IN1 Switch", "IN1L Mux" },
1152 { "DSP1TXR", "IN1 Switch", "IN1R Mux" },
1153
1154 { "DSP2TXL", "IN1 Switch", "IN2L Mux" },
1155 { "DSP2TXR", "IN1 Switch", "IN2R Mux" },
1156
1157 { "AIF1TX0", NULL, "DSP1TXL" },
1158 { "AIF1TX1", NULL, "DSP1TXR" },
1159 { "AIF1TX2", NULL, "DSP2TXL" },
1160 { "AIF1TX3", NULL, "DSP2TXR" },
1161 { "AIF1TX4", NULL, "AIF2RX0" },
1162 { "AIF1TX5", NULL, "AIF2RX1" },
1163
1164 { "AIF1RX0", NULL, "AIFCLK" },
1165 { "AIF1RX1", NULL, "AIFCLK" },
1166 { "AIF1RX2", NULL, "AIFCLK" },
1167 { "AIF1RX3", NULL, "AIFCLK" },
1168 { "AIF1RX4", NULL, "AIFCLK" },
1169 { "AIF1RX5", NULL, "AIFCLK" },
1170
1171 { "AIF2RX0", NULL, "AIFCLK" },
1172 { "AIF2RX1", NULL, "AIFCLK" },
1173
1174 { "AIF1TX0", NULL, "AIFCLK" },
1175 { "AIF1TX1", NULL, "AIFCLK" },
1176 { "AIF1TX2", NULL, "AIFCLK" },
1177 { "AIF1TX3", NULL, "AIFCLK" },
1178 { "AIF1TX4", NULL, "AIFCLK" },
1179 { "AIF1TX5", NULL, "AIFCLK" },
1180
1181 { "AIF2TX0", NULL, "AIFCLK" },
1182 { "AIF2TX1", NULL, "AIFCLK" },
1183
1184 { "DSP1RXL", NULL, "SYSDSPCLK" },
1185 { "DSP1RXR", NULL, "SYSDSPCLK" },
1186 { "DSP2RXL", NULL, "SYSDSPCLK" },
1187 { "DSP2RXR", NULL, "SYSDSPCLK" },
1188 { "DSP1TXL", NULL, "SYSDSPCLK" },
1189 { "DSP1TXR", NULL, "SYSDSPCLK" },
1190 { "DSP2TXL", NULL, "SYSDSPCLK" },
1191 { "DSP2TXR", NULL, "SYSDSPCLK" },
1192
1193 { "AIF1RXA", NULL, "AIF1RX0" },
1194 { "AIF1RXA", NULL, "AIF1RX1" },
1195 { "AIF1RXB", NULL, "AIF1RX2" },
1196 { "AIF1RXB", NULL, "AIF1RX3" },
1197 { "AIF1RXC", NULL, "AIF1RX4" },
1198 { "AIF1RXC", NULL, "AIF1RX5" },
1199
1200 { "AIF2RX", NULL, "AIF2RX0" },
1201 { "AIF2RX", NULL, "AIF2RX1" },
1202
1203 { "AIF2TX", "DSP2", "DSP2TX" },
1204 { "AIF2TX", "DSP1", "DSP1RX" },
1205 { "AIF2TX", "AIF1", "AIF1RXC" },
1206
1207 { "DSP1RXL", NULL, "DSP1RX" },
1208 { "DSP1RXR", NULL, "DSP1RX" },
1209 { "DSP2RXL", NULL, "DSP2RX" },
1210 { "DSP2RXR", NULL, "DSP2RX" },
1211
1212 { "DSP2TX", NULL, "DSP2TXL" },
1213 { "DSP2TX", NULL, "DSP2TXR" },
1214
1215 { "DSP1RX", "AIF1", "AIF1RXA" },
1216 { "DSP1RX", "AIF2", "AIF2RX" },
1217
1218 { "DSP2RX", "AIF1", "AIF1RXB" },
1219 { "DSP2RX", "AIF2", "AIF2RX" },
1220
1221 { "DAC2L Mixer", "DSP2 Switch", "DSP2RXL" },
1222 { "DAC2L Mixer", "DSP1 Switch", "DSP1RXL" },
1223 { "DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1224 { "DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1225
1226 { "DAC2R Mixer", "DSP2 Switch", "DSP2RXR" },
1227 { "DAC2R Mixer", "DSP1 Switch", "DSP1RXR" },
1228 { "DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1229 { "DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1230
1231 { "DAC1L Mixer", "DSP2 Switch", "DSP2RXL" },
1232 { "DAC1L Mixer", "DSP1 Switch", "DSP1RXL" },
1233 { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1234 { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1235
1236 { "DAC1R Mixer", "DSP2 Switch", "DSP2RXR" },
1237 { "DAC1R Mixer", "DSP1 Switch", "DSP1RXR" },
1238 { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1239 { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1240
1241 { "DAC1L", NULL, "DAC1L Mixer" },
1242 { "DAC1R", NULL, "DAC1R Mixer" },
1243 { "DAC2L", NULL, "DAC2L Mixer" },
1244 { "DAC2R", NULL, "DAC2R Mixer" },
1245
1246 { "HPOUT2L PGA", NULL, "Charge Pump" },
1247 { "HPOUT2L PGA", NULL, "Bandgap" },
1248 { "HPOUT2L PGA", NULL, "DAC2L" },
1249 { "HPOUT2L_DLY", NULL, "HPOUT2L PGA" },
1250 { "HPOUT2L_DCS", NULL, "HPOUT2L_DLY" },
1251 { "HPOUT2L_RMV_SHORT", NULL, "HPOUT2L_DCS" },
1252
1253 { "HPOUT2R PGA", NULL, "Charge Pump" },
1254 { "HPOUT2R PGA", NULL, "Bandgap" },
1255 { "HPOUT2R PGA", NULL, "DAC2R" },
1256 { "HPOUT2R_DLY", NULL, "HPOUT2R PGA" },
1257 { "HPOUT2R_DCS", NULL, "HPOUT2R_DLY" },
1258 { "HPOUT2R_RMV_SHORT", NULL, "HPOUT2R_DCS" },
1259
1260 { "HPOUT1L PGA", NULL, "Charge Pump" },
1261 { "HPOUT1L PGA", NULL, "Bandgap" },
1262 { "HPOUT1L PGA", NULL, "DAC1L" },
1263 { "HPOUT1L_DLY", NULL, "HPOUT1L PGA" },
1264 { "HPOUT1L_DCS", NULL, "HPOUT1L_DLY" },
1265 { "HPOUT1L_RMV_SHORT", NULL, "HPOUT1L_DCS" },
1266
1267 { "HPOUT1R PGA", NULL, "Charge Pump" },
1268 { "HPOUT1R PGA", NULL, "Bandgap" },
1269 { "HPOUT1R PGA", NULL, "DAC1R" },
1270 { "HPOUT1R_DLY", NULL, "HPOUT1R PGA" },
1271 { "HPOUT1R_DCS", NULL, "HPOUT1R_DLY" },
1272 { "HPOUT1R_RMV_SHORT", NULL, "HPOUT1R_DCS" },
1273
1274 { "HPOUT2L", NULL, "HPOUT2L_RMV_SHORT" },
1275 { "HPOUT2R", NULL, "HPOUT2R_RMV_SHORT" },
1276 { "HPOUT1L", NULL, "HPOUT1L_RMV_SHORT" },
1277 { "HPOUT1R", NULL, "HPOUT1R_RMV_SHORT" },
1278
1279 { "SPKL", "DAC1L", "DAC1L" },
1280 { "SPKL", "DAC1R", "DAC1R" },
1281 { "SPKL", "DAC2L", "DAC2L" },
1282 { "SPKL", "DAC2R", "DAC2R" },
1283
1284 { "SPKR", "DAC1L", "DAC1L" },
1285 { "SPKR", "DAC1R", "DAC1R" },
1286 { "SPKR", "DAC2L", "DAC2L" },
1287 { "SPKR", "DAC2R", "DAC2R" },
1288
1289 { "SPKL PGA", NULL, "SPKL" },
1290 { "SPKR PGA", NULL, "SPKR" },
1291
1292 { "SPKDAT", NULL, "SPKL PGA" },
1293 { "SPKDAT", NULL, "SPKR PGA" },
1294 };
1295
1296 static bool wm8996_readable_register(struct device *dev, unsigned int reg)
1297 {
1298 /* Due to the sparseness of the register map the compiler
1299 * output from an explicit switch statement ends up being much
1300 * more efficient than a table.
1301 */
1302 switch (reg) {
1303 case WM8996_SOFTWARE_RESET:
1304 case WM8996_POWER_MANAGEMENT_1:
1305 case WM8996_POWER_MANAGEMENT_2:
1306 case WM8996_POWER_MANAGEMENT_3:
1307 case WM8996_POWER_MANAGEMENT_4:
1308 case WM8996_POWER_MANAGEMENT_5:
1309 case WM8996_POWER_MANAGEMENT_6:
1310 case WM8996_POWER_MANAGEMENT_7:
1311 case WM8996_POWER_MANAGEMENT_8:
1312 case WM8996_LEFT_LINE_INPUT_VOLUME:
1313 case WM8996_RIGHT_LINE_INPUT_VOLUME:
1314 case WM8996_LINE_INPUT_CONTROL:
1315 case WM8996_DAC1_HPOUT1_VOLUME:
1316 case WM8996_DAC2_HPOUT2_VOLUME:
1317 case WM8996_DAC1_LEFT_VOLUME:
1318 case WM8996_DAC1_RIGHT_VOLUME:
1319 case WM8996_DAC2_LEFT_VOLUME:
1320 case WM8996_DAC2_RIGHT_VOLUME:
1321 case WM8996_OUTPUT1_LEFT_VOLUME:
1322 case WM8996_OUTPUT1_RIGHT_VOLUME:
1323 case WM8996_OUTPUT2_LEFT_VOLUME:
1324 case WM8996_OUTPUT2_RIGHT_VOLUME:
1325 case WM8996_MICBIAS_1:
1326 case WM8996_MICBIAS_2:
1327 case WM8996_LDO_1:
1328 case WM8996_LDO_2:
1329 case WM8996_ACCESSORY_DETECT_MODE_1:
1330 case WM8996_ACCESSORY_DETECT_MODE_2:
1331 case WM8996_HEADPHONE_DETECT_1:
1332 case WM8996_HEADPHONE_DETECT_2:
1333 case WM8996_MIC_DETECT_1:
1334 case WM8996_MIC_DETECT_2:
1335 case WM8996_MIC_DETECT_3:
1336 case WM8996_CHARGE_PUMP_1:
1337 case WM8996_CHARGE_PUMP_2:
1338 case WM8996_DC_SERVO_1:
1339 case WM8996_DC_SERVO_2:
1340 case WM8996_DC_SERVO_3:
1341 case WM8996_DC_SERVO_5:
1342 case WM8996_DC_SERVO_6:
1343 case WM8996_DC_SERVO_7:
1344 case WM8996_DC_SERVO_READBACK_0:
1345 case WM8996_ANALOGUE_HP_1:
1346 case WM8996_ANALOGUE_HP_2:
1347 case WM8996_CHIP_REVISION:
1348 case WM8996_CONTROL_INTERFACE_1:
1349 case WM8996_WRITE_SEQUENCER_CTRL_1:
1350 case WM8996_WRITE_SEQUENCER_CTRL_2:
1351 case WM8996_AIF_CLOCKING_1:
1352 case WM8996_AIF_CLOCKING_2:
1353 case WM8996_CLOCKING_1:
1354 case WM8996_CLOCKING_2:
1355 case WM8996_AIF_RATE:
1356 case WM8996_FLL_CONTROL_1:
1357 case WM8996_FLL_CONTROL_2:
1358 case WM8996_FLL_CONTROL_3:
1359 case WM8996_FLL_CONTROL_4:
1360 case WM8996_FLL_CONTROL_5:
1361 case WM8996_FLL_CONTROL_6:
1362 case WM8996_FLL_EFS_1:
1363 case WM8996_FLL_EFS_2:
1364 case WM8996_AIF1_CONTROL:
1365 case WM8996_AIF1_BCLK:
1366 case WM8996_AIF1_TX_LRCLK_1:
1367 case WM8996_AIF1_TX_LRCLK_2:
1368 case WM8996_AIF1_RX_LRCLK_1:
1369 case WM8996_AIF1_RX_LRCLK_2:
1370 case WM8996_AIF1TX_DATA_CONFIGURATION_1:
1371 case WM8996_AIF1TX_DATA_CONFIGURATION_2:
1372 case WM8996_AIF1RX_DATA_CONFIGURATION:
1373 case WM8996_AIF1TX_CHANNEL_0_CONFIGURATION:
1374 case WM8996_AIF1TX_CHANNEL_1_CONFIGURATION:
1375 case WM8996_AIF1TX_CHANNEL_2_CONFIGURATION:
1376 case WM8996_AIF1TX_CHANNEL_3_CONFIGURATION:
1377 case WM8996_AIF1TX_CHANNEL_4_CONFIGURATION:
1378 case WM8996_AIF1TX_CHANNEL_5_CONFIGURATION:
1379 case WM8996_AIF1RX_CHANNEL_0_CONFIGURATION:
1380 case WM8996_AIF1RX_CHANNEL_1_CONFIGURATION:
1381 case WM8996_AIF1RX_CHANNEL_2_CONFIGURATION:
1382 case WM8996_AIF1RX_CHANNEL_3_CONFIGURATION:
1383 case WM8996_AIF1RX_CHANNEL_4_CONFIGURATION:
1384 case WM8996_AIF1RX_CHANNEL_5_CONFIGURATION:
1385 case WM8996_AIF1RX_MONO_CONFIGURATION:
1386 case WM8996_AIF1TX_TEST:
1387 case WM8996_AIF2_CONTROL:
1388 case WM8996_AIF2_BCLK:
1389 case WM8996_AIF2_TX_LRCLK_1:
1390 case WM8996_AIF2_TX_LRCLK_2:
1391 case WM8996_AIF2_RX_LRCLK_1:
1392 case WM8996_AIF2_RX_LRCLK_2:
1393 case WM8996_AIF2TX_DATA_CONFIGURATION_1:
1394 case WM8996_AIF2TX_DATA_CONFIGURATION_2:
1395 case WM8996_AIF2RX_DATA_CONFIGURATION:
1396 case WM8996_AIF2TX_CHANNEL_0_CONFIGURATION:
1397 case WM8996_AIF2TX_CHANNEL_1_CONFIGURATION:
1398 case WM8996_AIF2RX_CHANNEL_0_CONFIGURATION:
1399 case WM8996_AIF2RX_CHANNEL_1_CONFIGURATION:
1400 case WM8996_AIF2RX_MONO_CONFIGURATION:
1401 case WM8996_AIF2TX_TEST:
1402 case WM8996_DSP1_TX_LEFT_VOLUME:
1403 case WM8996_DSP1_TX_RIGHT_VOLUME:
1404 case WM8996_DSP1_RX_LEFT_VOLUME:
1405 case WM8996_DSP1_RX_RIGHT_VOLUME:
1406 case WM8996_DSP1_TX_FILTERS:
1407 case WM8996_DSP1_RX_FILTERS_1:
1408 case WM8996_DSP1_RX_FILTERS_2:
1409 case WM8996_DSP1_DRC_1:
1410 case WM8996_DSP1_DRC_2:
1411 case WM8996_DSP1_DRC_3:
1412 case WM8996_DSP1_DRC_4:
1413 case WM8996_DSP1_DRC_5:
1414 case WM8996_DSP1_RX_EQ_GAINS_1:
1415 case WM8996_DSP1_RX_EQ_GAINS_2:
1416 case WM8996_DSP1_RX_EQ_BAND_1_A:
1417 case WM8996_DSP1_RX_EQ_BAND_1_B:
1418 case WM8996_DSP1_RX_EQ_BAND_1_PG:
1419 case WM8996_DSP1_RX_EQ_BAND_2_A:
1420 case WM8996_DSP1_RX_EQ_BAND_2_B:
1421 case WM8996_DSP1_RX_EQ_BAND_2_C:
1422 case WM8996_DSP1_RX_EQ_BAND_2_PG:
1423 case WM8996_DSP1_RX_EQ_BAND_3_A:
1424 case WM8996_DSP1_RX_EQ_BAND_3_B:
1425 case WM8996_DSP1_RX_EQ_BAND_3_C:
1426 case WM8996_DSP1_RX_EQ_BAND_3_PG:
1427 case WM8996_DSP1_RX_EQ_BAND_4_A:
1428 case WM8996_DSP1_RX_EQ_BAND_4_B:
1429 case WM8996_DSP1_RX_EQ_BAND_4_C:
1430 case WM8996_DSP1_RX_EQ_BAND_4_PG:
1431 case WM8996_DSP1_RX_EQ_BAND_5_A:
1432 case WM8996_DSP1_RX_EQ_BAND_5_B:
1433 case WM8996_DSP1_RX_EQ_BAND_5_PG:
1434 case WM8996_DSP2_TX_LEFT_VOLUME:
1435 case WM8996_DSP2_TX_RIGHT_VOLUME:
1436 case WM8996_DSP2_RX_LEFT_VOLUME:
1437 case WM8996_DSP2_RX_RIGHT_VOLUME:
1438 case WM8996_DSP2_TX_FILTERS:
1439 case WM8996_DSP2_RX_FILTERS_1:
1440 case WM8996_DSP2_RX_FILTERS_2:
1441 case WM8996_DSP2_DRC_1:
1442 case WM8996_DSP2_DRC_2:
1443 case WM8996_DSP2_DRC_3:
1444 case WM8996_DSP2_DRC_4:
1445 case WM8996_DSP2_DRC_5:
1446 case WM8996_DSP2_RX_EQ_GAINS_1:
1447 case WM8996_DSP2_RX_EQ_GAINS_2:
1448 case WM8996_DSP2_RX_EQ_BAND_1_A:
1449 case WM8996_DSP2_RX_EQ_BAND_1_B:
1450 case WM8996_DSP2_RX_EQ_BAND_1_PG:
1451 case WM8996_DSP2_RX_EQ_BAND_2_A:
1452 case WM8996_DSP2_RX_EQ_BAND_2_B:
1453 case WM8996_DSP2_RX_EQ_BAND_2_C:
1454 case WM8996_DSP2_RX_EQ_BAND_2_PG:
1455 case WM8996_DSP2_RX_EQ_BAND_3_A:
1456 case WM8996_DSP2_RX_EQ_BAND_3_B:
1457 case WM8996_DSP2_RX_EQ_BAND_3_C:
1458 case WM8996_DSP2_RX_EQ_BAND_3_PG:
1459 case WM8996_DSP2_RX_EQ_BAND_4_A:
1460 case WM8996_DSP2_RX_EQ_BAND_4_B:
1461 case WM8996_DSP2_RX_EQ_BAND_4_C:
1462 case WM8996_DSP2_RX_EQ_BAND_4_PG:
1463 case WM8996_DSP2_RX_EQ_BAND_5_A:
1464 case WM8996_DSP2_RX_EQ_BAND_5_B:
1465 case WM8996_DSP2_RX_EQ_BAND_5_PG:
1466 case WM8996_DAC1_MIXER_VOLUMES:
1467 case WM8996_DAC1_LEFT_MIXER_ROUTING:
1468 case WM8996_DAC1_RIGHT_MIXER_ROUTING:
1469 case WM8996_DAC2_MIXER_VOLUMES:
1470 case WM8996_DAC2_LEFT_MIXER_ROUTING:
1471 case WM8996_DAC2_RIGHT_MIXER_ROUTING:
1472 case WM8996_DSP1_TX_LEFT_MIXER_ROUTING:
1473 case WM8996_DSP1_TX_RIGHT_MIXER_ROUTING:
1474 case WM8996_DSP2_TX_LEFT_MIXER_ROUTING:
1475 case WM8996_DSP2_TX_RIGHT_MIXER_ROUTING:
1476 case WM8996_DSP_TX_MIXER_SELECT:
1477 case WM8996_DAC_SOFTMUTE:
1478 case WM8996_OVERSAMPLING:
1479 case WM8996_SIDETONE:
1480 case WM8996_GPIO_1:
1481 case WM8996_GPIO_2:
1482 case WM8996_GPIO_3:
1483 case WM8996_GPIO_4:
1484 case WM8996_GPIO_5:
1485 case WM8996_PULL_CONTROL_1:
1486 case WM8996_PULL_CONTROL_2:
1487 case WM8996_INTERRUPT_STATUS_1:
1488 case WM8996_INTERRUPT_STATUS_2:
1489 case WM8996_INTERRUPT_RAW_STATUS_2:
1490 case WM8996_INTERRUPT_STATUS_1_MASK:
1491 case WM8996_INTERRUPT_STATUS_2_MASK:
1492 case WM8996_INTERRUPT_CONTROL:
1493 case WM8996_LEFT_PDM_SPEAKER:
1494 case WM8996_RIGHT_PDM_SPEAKER:
1495 case WM8996_PDM_SPEAKER_MUTE_SEQUENCE:
1496 case WM8996_PDM_SPEAKER_VOLUME:
1497 return true;
1498 default:
1499 return false;
1500 }
1501 }
1502
1503 static bool wm8996_volatile_register(struct device *dev, unsigned int reg)
1504 {
1505 switch (reg) {
1506 case WM8996_SOFTWARE_RESET:
1507 case WM8996_CHIP_REVISION:
1508 case WM8996_LDO_1:
1509 case WM8996_LDO_2:
1510 case WM8996_INTERRUPT_STATUS_1:
1511 case WM8996_INTERRUPT_STATUS_2:
1512 case WM8996_INTERRUPT_RAW_STATUS_2:
1513 case WM8996_DC_SERVO_READBACK_0:
1514 case WM8996_DC_SERVO_2:
1515 case WM8996_DC_SERVO_6:
1516 case WM8996_DC_SERVO_7:
1517 case WM8996_FLL_CONTROL_6:
1518 case WM8996_MIC_DETECT_3:
1519 case WM8996_HEADPHONE_DETECT_1:
1520 case WM8996_HEADPHONE_DETECT_2:
1521 return true;
1522 default:
1523 return false;
1524 }
1525 }
1526
1527 static const int bclk_divs[] = {
1528 1, 2, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96
1529 };
1530
1531 static void wm8996_update_bclk(struct snd_soc_component *component)
1532 {
1533 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
1534 int aif, best, cur_val, bclk_rate, bclk_reg, i;
1535
1536 /* Don't bother if we're in a low frequency idle mode that
1537 * can't support audio.
1538 */
1539 if (wm8996->sysclk < 64000)
1540 return;
1541
1542 for (aif = 0; aif < WM8996_AIFS; aif++) {
1543 switch (aif) {
1544 case 0:
1545 bclk_reg = WM8996_AIF1_BCLK;
1546 break;
1547 case 1:
1548 bclk_reg = WM8996_AIF2_BCLK;
1549 break;
1550 }
1551
1552 bclk_rate = wm8996->bclk_rate[aif];
1553
1554 /* Pick a divisor for BCLK as close as we can get to ideal */
1555 best = 0;
1556 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1557 cur_val = (wm8996->sysclk / bclk_divs[i]) - bclk_rate;
1558 if (cur_val < 0) /* BCLK table is sorted */
1559 break;
1560 best = i;
1561 }
1562 bclk_rate = wm8996->sysclk / bclk_divs[best];
1563 dev_dbg(component->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
1564 bclk_divs[best], bclk_rate);
1565
1566 snd_soc_component_update_bits(component, bclk_reg,
1567 WM8996_AIF1_BCLK_DIV_MASK, best);
1568 }
1569 }
1570
1571 static int wm8996_set_bias_level(struct snd_soc_component *component,
1572 enum snd_soc_bias_level level)
1573 {
1574 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
1575 int ret;
1576
1577 switch (level) {
1578 case SND_SOC_BIAS_ON:
1579 break;
1580 case SND_SOC_BIAS_PREPARE:
1581 /* Put the MICBIASes into regulating mode */
1582 snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
1583 WM8996_MICB1_MODE, 0);
1584 snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
1585 WM8996_MICB2_MODE, 0);
1586 break;
1587
1588 case SND_SOC_BIAS_STANDBY:
1589 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1590 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
1591 wm8996->supplies);
1592 if (ret != 0) {
1593 dev_err(component->dev,
1594 "Failed to enable supplies: %d\n",
1595 ret);
1596 return ret;
1597 }
1598
1599 if (wm8996->pdata.ldo_ena >= 0) {
1600 gpio_set_value_cansleep(wm8996->pdata.ldo_ena,
1601 1);
1602 msleep(5);
1603 }
1604
1605 regcache_cache_only(wm8996->regmap, false);
1606 regcache_sync(wm8996->regmap);
1607 }
1608
1609 /* Bypass the MICBIASes for lowest power */
1610 snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
1611 WM8996_MICB1_MODE, WM8996_MICB1_MODE);
1612 snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
1613 WM8996_MICB2_MODE, WM8996_MICB2_MODE);
1614 break;
1615
1616 case SND_SOC_BIAS_OFF:
1617 regcache_cache_only(wm8996->regmap, true);
1618 if (wm8996->pdata.ldo_ena >= 0) {
1619 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
1620 regcache_cache_only(wm8996->regmap, true);
1621 }
1622 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies),
1623 wm8996->supplies);
1624 break;
1625 }
1626
1627 return 0;
1628 }
1629
1630 static int wm8996_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1631 {
1632 struct snd_soc_component *component = dai->component;
1633 int aifctrl = 0;
1634 int bclk = 0;
1635 int lrclk_tx = 0;
1636 int lrclk_rx = 0;
1637 int aifctrl_reg, bclk_reg, lrclk_tx_reg, lrclk_rx_reg;
1638
1639 switch (dai->id) {
1640 case 0:
1641 aifctrl_reg = WM8996_AIF1_CONTROL;
1642 bclk_reg = WM8996_AIF1_BCLK;
1643 lrclk_tx_reg = WM8996_AIF1_TX_LRCLK_2;
1644 lrclk_rx_reg = WM8996_AIF1_RX_LRCLK_2;
1645 break;
1646 case 1:
1647 aifctrl_reg = WM8996_AIF2_CONTROL;
1648 bclk_reg = WM8996_AIF2_BCLK;
1649 lrclk_tx_reg = WM8996_AIF2_TX_LRCLK_2;
1650 lrclk_rx_reg = WM8996_AIF2_RX_LRCLK_2;
1651 break;
1652 default:
1653 WARN(1, "Invalid dai id %d\n", dai->id);
1654 return -EINVAL;
1655 }
1656
1657 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1658 case SND_SOC_DAIFMT_NB_NF:
1659 break;
1660 case SND_SOC_DAIFMT_IB_NF:
1661 bclk |= WM8996_AIF1_BCLK_INV;
1662 break;
1663 case SND_SOC_DAIFMT_NB_IF:
1664 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1665 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1666 break;
1667 case SND_SOC_DAIFMT_IB_IF:
1668 bclk |= WM8996_AIF1_BCLK_INV;
1669 lrclk_tx |= WM8996_AIF1TX_LRCLK_INV;
1670 lrclk_rx |= WM8996_AIF1RX_LRCLK_INV;
1671 break;
1672 }
1673
1674 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1675 case SND_SOC_DAIFMT_CBS_CFS:
1676 break;
1677 case SND_SOC_DAIFMT_CBS_CFM:
1678 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1679 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1680 break;
1681 case SND_SOC_DAIFMT_CBM_CFS:
1682 bclk |= WM8996_AIF1_BCLK_MSTR;
1683 break;
1684 case SND_SOC_DAIFMT_CBM_CFM:
1685 bclk |= WM8996_AIF1_BCLK_MSTR;
1686 lrclk_tx |= WM8996_AIF1TX_LRCLK_MSTR;
1687 lrclk_rx |= WM8996_AIF1RX_LRCLK_MSTR;
1688 break;
1689 default:
1690 return -EINVAL;
1691 }
1692
1693 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1694 case SND_SOC_DAIFMT_DSP_A:
1695 break;
1696 case SND_SOC_DAIFMT_DSP_B:
1697 aifctrl |= 1;
1698 break;
1699 case SND_SOC_DAIFMT_I2S:
1700 aifctrl |= 2;
1701 break;
1702 case SND_SOC_DAIFMT_LEFT_J:
1703 aifctrl |= 3;
1704 break;
1705 default:
1706 return -EINVAL;
1707 }
1708
1709 snd_soc_component_update_bits(component, aifctrl_reg, WM8996_AIF1_FMT_MASK, aifctrl);
1710 snd_soc_component_update_bits(component, bclk_reg,
1711 WM8996_AIF1_BCLK_INV | WM8996_AIF1_BCLK_MSTR,
1712 bclk);
1713 snd_soc_component_update_bits(component, lrclk_tx_reg,
1714 WM8996_AIF1TX_LRCLK_INV |
1715 WM8996_AIF1TX_LRCLK_MSTR,
1716 lrclk_tx);
1717 snd_soc_component_update_bits(component, lrclk_rx_reg,
1718 WM8996_AIF1RX_LRCLK_INV |
1719 WM8996_AIF1RX_LRCLK_MSTR,
1720 lrclk_rx);
1721
1722 return 0;
1723 }
1724
1725 static const int dsp_divs[] = {
1726 48000, 32000, 16000, 8000
1727 };
1728
1729 static int wm8996_hw_params(struct snd_pcm_substream *substream,
1730 struct snd_pcm_hw_params *params,
1731 struct snd_soc_dai *dai)
1732 {
1733 struct snd_soc_component *component = dai->component;
1734 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
1735 int bits, i, bclk_rate, best;
1736 int aifdata = 0;
1737 int lrclk = 0;
1738 int dsp = 0;
1739 int aifdata_reg, lrclk_reg, dsp_shift;
1740
1741 switch (dai->id) {
1742 case 0:
1743 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1744 (snd_soc_component_read(component, WM8996_GPIO_1)) & WM8996_GP1_FN_MASK) {
1745 aifdata_reg = WM8996_AIF1RX_DATA_CONFIGURATION;
1746 lrclk_reg = WM8996_AIF1_RX_LRCLK_1;
1747 } else {
1748 aifdata_reg = WM8996_AIF1TX_DATA_CONFIGURATION_1;
1749 lrclk_reg = WM8996_AIF1_TX_LRCLK_1;
1750 }
1751 dsp_shift = 0;
1752 break;
1753 case 1:
1754 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1755 (snd_soc_component_read(component, WM8996_GPIO_2)) & WM8996_GP2_FN_MASK) {
1756 aifdata_reg = WM8996_AIF2RX_DATA_CONFIGURATION;
1757 lrclk_reg = WM8996_AIF2_RX_LRCLK_1;
1758 } else {
1759 aifdata_reg = WM8996_AIF2TX_DATA_CONFIGURATION_1;
1760 lrclk_reg = WM8996_AIF2_TX_LRCLK_1;
1761 }
1762 dsp_shift = WM8996_DSP2_DIV_SHIFT;
1763 break;
1764 default:
1765 WARN(1, "Invalid dai id %d\n", dai->id);
1766 return -EINVAL;
1767 }
1768
1769 bclk_rate = snd_soc_params_to_bclk(params);
1770 if (bclk_rate < 0) {
1771 dev_err(component->dev, "Unsupported BCLK rate: %d\n", bclk_rate);
1772 return bclk_rate;
1773 }
1774
1775 wm8996->bclk_rate[dai->id] = bclk_rate;
1776 wm8996->rx_rate[dai->id] = params_rate(params);
1777
1778 /* Needs looking at for TDM */
1779 bits = params_width(params);
1780 if (bits < 0)
1781 return bits;
1782 aifdata |= (bits << WM8996_AIF1TX_WL_SHIFT) | bits;
1783
1784 best = 0;
1785 for (i = 0; i < ARRAY_SIZE(dsp_divs); i++) {
1786 if (abs(dsp_divs[i] - params_rate(params)) <
1787 abs(dsp_divs[best] - params_rate(params)))
1788 best = i;
1789 }
1790 dsp |= i << dsp_shift;
1791
1792 wm8996_update_bclk(component);
1793
1794 lrclk = bclk_rate / params_rate(params);
1795 dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
1796 lrclk, bclk_rate / lrclk);
1797
1798 snd_soc_component_update_bits(component, aifdata_reg,
1799 WM8996_AIF1TX_WL_MASK |
1800 WM8996_AIF1TX_SLOT_LEN_MASK,
1801 aifdata);
1802 snd_soc_component_update_bits(component, lrclk_reg, WM8996_AIF1RX_RATE_MASK,
1803 lrclk);
1804 snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_2,
1805 WM8996_DSP1_DIV_MASK << dsp_shift, dsp);
1806
1807 return 0;
1808 }
1809
1810 static int wm8996_set_sysclk(struct snd_soc_dai *dai,
1811 int clk_id, unsigned int freq, int dir)
1812 {
1813 struct snd_soc_component *component = dai->component;
1814 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
1815 int lfclk = 0;
1816 int ratediv = 0;
1817 int sync = WM8996_REG_SYNC;
1818 int src;
1819 int old;
1820
1821 if (freq == wm8996->sysclk && clk_id == wm8996->sysclk_src)
1822 return 0;
1823
1824 /* Disable SYSCLK while we reconfigure */
1825 old = snd_soc_component_read(component, WM8996_AIF_CLOCKING_1) & WM8996_SYSCLK_ENA;
1826 snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
1827 WM8996_SYSCLK_ENA, 0);
1828
1829 switch (clk_id) {
1830 case WM8996_SYSCLK_MCLK1:
1831 wm8996->sysclk = freq;
1832 src = 0;
1833 break;
1834 case WM8996_SYSCLK_MCLK2:
1835 wm8996->sysclk = freq;
1836 src = 1;
1837 break;
1838 case WM8996_SYSCLK_FLL:
1839 wm8996->sysclk = freq;
1840 src = 2;
1841 break;
1842 default:
1843 dev_err(component->dev, "Unsupported clock source %d\n", clk_id);
1844 return -EINVAL;
1845 }
1846
1847 switch (wm8996->sysclk) {
1848 case 5644800:
1849 case 6144000:
1850 snd_soc_component_update_bits(component, WM8996_AIF_RATE,
1851 WM8996_SYSCLK_RATE, 0);
1852 break;
1853 case 22579200:
1854 case 24576000:
1855 ratediv = WM8996_SYSCLK_DIV;
1856 wm8996->sysclk /= 2;
1857 fallthrough;
1858 case 11289600:
1859 case 12288000:
1860 snd_soc_component_update_bits(component, WM8996_AIF_RATE,
1861 WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);
1862 break;
1863 case 32000:
1864 case 32768:
1865 lfclk = WM8996_LFCLK_ENA;
1866 sync = 0;
1867 break;
1868 default:
1869 dev_warn(component->dev, "Unsupported clock rate %dHz\n",
1870 wm8996->sysclk);
1871 return -EINVAL;
1872 }
1873
1874 wm8996_update_bclk(component);
1875
1876 snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
1877 WM8996_SYSCLK_SRC_MASK | WM8996_SYSCLK_DIV_MASK,
1878 src << WM8996_SYSCLK_SRC_SHIFT | ratediv);
1879 snd_soc_component_update_bits(component, WM8996_CLOCKING_1, WM8996_LFCLK_ENA, lfclk);
1880 snd_soc_component_update_bits(component, WM8996_CONTROL_INTERFACE_1,
1881 WM8996_REG_SYNC, sync);
1882 snd_soc_component_update_bits(component, WM8996_AIF_CLOCKING_1,
1883 WM8996_SYSCLK_ENA, old);
1884
1885 wm8996->sysclk_src = clk_id;
1886
1887 return 0;
1888 }
1889
1890 struct _fll_div {
1891 u16 fll_fratio;
1892 u16 fll_outdiv;
1893 u16 fll_refclk_div;
1894 u16 fll_loop_gain;
1895 u16 fll_ref_freq;
1896 u16 n;
1897 u16 theta;
1898 u16 lambda;
1899 };
1900
1901 static struct {
1902 unsigned int min;
1903 unsigned int max;
1904 u16 fll_fratio;
1905 int ratio;
1906 } fll_fratios[] = {
1907 { 0, 64000, 4, 16 },
1908 { 64000, 128000, 3, 8 },
1909 { 128000, 256000, 2, 4 },
1910 { 256000, 1000000, 1, 2 },
1911 { 1000000, 13500000, 0, 1 },
1912 };
1913
1914 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1915 unsigned int Fout)
1916 {
1917 unsigned int target;
1918 unsigned int div;
1919 unsigned int fratio, gcd_fll;
1920 int i;
1921
1922 /* Fref must be <=13.5MHz */
1923 div = 1;
1924 fll_div->fll_refclk_div = 0;
1925 while ((Fref / div) > 13500000) {
1926 div *= 2;
1927 fll_div->fll_refclk_div++;
1928
1929 if (div > 8) {
1930 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1931 Fref);
1932 return -EINVAL;
1933 }
1934 }
1935
1936 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1937
1938 /* Apply the division for our remaining calculations */
1939 Fref /= div;
1940
1941 if (Fref >= 3000000)
1942 fll_div->fll_loop_gain = 5;
1943 else
1944 fll_div->fll_loop_gain = 0;
1945
1946 if (Fref >= 48000)
1947 fll_div->fll_ref_freq = 0;
1948 else
1949 fll_div->fll_ref_freq = 1;
1950
1951 /* Fvco should be 90-100MHz; don't check the upper bound */
1952 div = 2;
1953 while (Fout * div < 90000000) {
1954 div++;
1955 if (div > 64) {
1956 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1957 Fout);
1958 return -EINVAL;
1959 }
1960 }
1961 target = Fout * div;
1962 fll_div->fll_outdiv = div - 1;
1963
1964 pr_debug("FLL Fvco=%dHz\n", target);
1965
1966 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1967 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1968 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1969 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1970 fratio = fll_fratios[i].ratio;
1971 break;
1972 }
1973 }
1974 if (i == ARRAY_SIZE(fll_fratios)) {
1975 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1976 return -EINVAL;
1977 }
1978
1979 fll_div->n = target / (fratio * Fref);
1980
1981 if (target % Fref == 0) {
1982 fll_div->theta = 0;
1983 fll_div->lambda = 0;
1984 } else {
1985 gcd_fll = gcd(target, fratio * Fref);
1986
1987 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1988 / gcd_fll;
1989 fll_div->lambda = (fratio * Fref) / gcd_fll;
1990 }
1991
1992 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1993 fll_div->n, fll_div->theta, fll_div->lambda);
1994 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1995 fll_div->fll_fratio, fll_div->fll_outdiv,
1996 fll_div->fll_refclk_div);
1997
1998 return 0;
1999 }
2000
2001 static int wm8996_set_fll(struct snd_soc_component *component, int fll_id, int source,
2002 unsigned int Fref, unsigned int Fout)
2003 {
2004 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
2005 struct i2c_client *i2c = to_i2c_client(component->dev);
2006 struct _fll_div fll_div;
2007 unsigned long timeout, time_left;
2008 int ret, reg, retry;
2009
2010 /* Any change? */
2011 if (source == wm8996->fll_src && Fref == wm8996->fll_fref &&
2012 Fout == wm8996->fll_fout)
2013 return 0;
2014
2015 if (Fout == 0) {
2016 dev_dbg(component->dev, "FLL disabled\n");
2017
2018 wm8996->fll_fref = 0;
2019 wm8996->fll_fout = 0;
2020
2021 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_1,
2022 WM8996_FLL_ENA, 0);
2023
2024 wm8996_bg_disable(component);
2025
2026 return 0;
2027 }
2028
2029 ret = fll_factors(&fll_div, Fref, Fout);
2030 if (ret != 0)
2031 return ret;
2032
2033 switch (source) {
2034 case WM8996_FLL_MCLK1:
2035 reg = 0;
2036 break;
2037 case WM8996_FLL_MCLK2:
2038 reg = 1;
2039 break;
2040 case WM8996_FLL_DACLRCLK1:
2041 reg = 2;
2042 break;
2043 case WM8996_FLL_BCLK1:
2044 reg = 3;
2045 break;
2046 default:
2047 dev_err(component->dev, "Unknown FLL source %d\n", ret);
2048 return -EINVAL;
2049 }
2050
2051 reg |= fll_div.fll_refclk_div << WM8996_FLL_REFCLK_DIV_SHIFT;
2052 reg |= fll_div.fll_ref_freq << WM8996_FLL_REF_FREQ_SHIFT;
2053
2054 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_5,
2055 WM8996_FLL_REFCLK_DIV_MASK | WM8996_FLL_REF_FREQ |
2056 WM8996_FLL_REFCLK_SRC_MASK, reg);
2057
2058 reg = 0;
2059 if (fll_div.theta || fll_div.lambda)
2060 reg |= WM8996_FLL_EFS_ENA | (3 << WM8996_FLL_LFSR_SEL_SHIFT);
2061 else
2062 reg |= 1 << WM8996_FLL_LFSR_SEL_SHIFT;
2063 snd_soc_component_write(component, WM8996_FLL_EFS_2, reg);
2064
2065 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_2,
2066 WM8996_FLL_OUTDIV_MASK |
2067 WM8996_FLL_FRATIO_MASK,
2068 (fll_div.fll_outdiv << WM8996_FLL_OUTDIV_SHIFT) |
2069 (fll_div.fll_fratio));
2070
2071 snd_soc_component_write(component, WM8996_FLL_CONTROL_3, fll_div.theta);
2072
2073 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_4,
2074 WM8996_FLL_N_MASK | WM8996_FLL_LOOP_GAIN_MASK,
2075 (fll_div.n << WM8996_FLL_N_SHIFT) |
2076 fll_div.fll_loop_gain);
2077
2078 snd_soc_component_write(component, WM8996_FLL_EFS_1, fll_div.lambda);
2079
2080 /* Enable the bandgap if it's not already enabled */
2081 ret = snd_soc_component_read(component, WM8996_FLL_CONTROL_1);
2082 if (!(ret & WM8996_FLL_ENA))
2083 wm8996_bg_enable(component);
2084
2085 /* Clear any pending completions (eg, from failed startups) */
2086 try_wait_for_completion(&wm8996->fll_lock);
2087
2088 snd_soc_component_update_bits(component, WM8996_FLL_CONTROL_1,
2089 WM8996_FLL_ENA, WM8996_FLL_ENA);
2090
2091 /* The FLL supports live reconfiguration - kick that in case we were
2092 * already enabled.
2093 */
2094 snd_soc_component_write(component, WM8996_FLL_CONTROL_6, WM8996_FLL_SWITCH_CLK);
2095
2096 /* Wait for the FLL to lock, using the interrupt if possible */
2097 if (Fref > 1000000)
2098 timeout = usecs_to_jiffies(300);
2099 else
2100 timeout = msecs_to_jiffies(2);
2101
2102 /* Allow substantially longer if we've actually got the IRQ, poll
2103 * at a slightly higher rate if we don't.
2104 */
2105 if (i2c->irq)
2106 timeout *= 10;
2107 else
2108 /* ensure timeout of atleast 1 jiffies */
2109 timeout = timeout/2 ? : 1;
2110
2111 for (retry = 0; retry < 10; retry++) {
2112 time_left = wait_for_completion_timeout(&wm8996->fll_lock,
2113 timeout);
2114 if (time_left != 0) {
2115 WARN_ON(!i2c->irq);
2116 ret = 1;
2117 break;
2118 }
2119
2120 ret = snd_soc_component_read(component, WM8996_INTERRUPT_RAW_STATUS_2);
2121 if (ret & WM8996_FLL_LOCK_STS)
2122 break;
2123 }
2124 if (retry == 10) {
2125 dev_err(component->dev, "Timed out waiting for FLL\n");
2126 ret = -ETIMEDOUT;
2127 }
2128
2129 dev_dbg(component->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2130
2131 wm8996->fll_fref = Fref;
2132 wm8996->fll_fout = Fout;
2133 wm8996->fll_src = source;
2134
2135 return ret;
2136 }
2137
2138 #ifdef CONFIG_GPIOLIB
2139 static void wm8996_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2140 {
2141 struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
2142
2143 regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2144 WM8996_GP1_LVL, !!value << WM8996_GP1_LVL_SHIFT);
2145 }
2146
2147 static int wm8996_gpio_direction_out(struct gpio_chip *chip,
2148 unsigned offset, int value)
2149 {
2150 struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
2151 int val;
2152
2153 val = (1 << WM8996_GP1_FN_SHIFT) | (!!value << WM8996_GP1_LVL_SHIFT);
2154
2155 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2156 WM8996_GP1_FN_MASK | WM8996_GP1_DIR |
2157 WM8996_GP1_LVL, val);
2158 }
2159
2160 static int wm8996_gpio_get(struct gpio_chip *chip, unsigned offset)
2161 {
2162 struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
2163 unsigned int reg;
2164 int ret;
2165
2166 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1 + offset, &reg);
2167 if (ret < 0)
2168 return ret;
2169
2170 return (reg & WM8996_GP1_LVL) != 0;
2171 }
2172
2173 static int wm8996_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2174 {
2175 struct wm8996_priv *wm8996 = gpiochip_get_data(chip);
2176
2177 return regmap_update_bits(wm8996->regmap, WM8996_GPIO_1 + offset,
2178 WM8996_GP1_FN_MASK | WM8996_GP1_DIR,
2179 (1 << WM8996_GP1_FN_SHIFT) |
2180 (1 << WM8996_GP1_DIR_SHIFT));
2181 }
2182
2183 static const struct gpio_chip wm8996_template_chip = {
2184 .label = "wm8996",
2185 .owner = THIS_MODULE,
2186 .direction_output = wm8996_gpio_direction_out,
2187 .set = wm8996_gpio_set,
2188 .direction_input = wm8996_gpio_direction_in,
2189 .get = wm8996_gpio_get,
2190 .can_sleep = 1,
2191 };
2192
2193 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2194 {
2195 int ret;
2196
2197 wm8996->gpio_chip = wm8996_template_chip;
2198 wm8996->gpio_chip.ngpio = 5;
2199 wm8996->gpio_chip.parent = wm8996->dev;
2200
2201 if (wm8996->pdata.gpio_base)
2202 wm8996->gpio_chip.base = wm8996->pdata.gpio_base;
2203 else
2204 wm8996->gpio_chip.base = -1;
2205
2206 ret = gpiochip_add_data(&wm8996->gpio_chip, wm8996);
2207 if (ret != 0)
2208 dev_err(wm8996->dev, "Failed to add GPIOs: %d\n", ret);
2209 }
2210
2211 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2212 {
2213 gpiochip_remove(&wm8996->gpio_chip);
2214 }
2215 #else
2216 static void wm8996_init_gpio(struct wm8996_priv *wm8996)
2217 {
2218 }
2219
2220 static void wm8996_free_gpio(struct wm8996_priv *wm8996)
2221 {
2222 }
2223 #endif
2224
2225 /**
2226 * wm8996_detect - Enable default WM8996 jack detection
2227 * @component: ASoC component
2228 * @jack: jack pointer
2229 * @polarity_cb: polarity callback
2230 *
2231 * The WM8996 has advanced accessory detection support for headsets.
2232 * This function provides a default implementation which integrates
2233 * the majority of this functionality with minimal user configuration.
2234 *
2235 * This will detect headset, headphone and short circuit button and
2236 * will also detect inverted microphone ground connections and update
2237 * the polarity of the connections.
2238 */
2239 int wm8996_detect(struct snd_soc_component *component, struct snd_soc_jack *jack,
2240 wm8996_polarity_fn polarity_cb)
2241 {
2242 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
2243 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2244
2245 wm8996->jack = jack;
2246 wm8996->detecting = true;
2247 wm8996->polarity_cb = polarity_cb;
2248 wm8996->jack_flips = 0;
2249
2250 if (wm8996->polarity_cb)
2251 wm8996->polarity_cb(component, 0);
2252
2253 /* Clear discarge to avoid noise during detection */
2254 snd_soc_component_update_bits(component, WM8996_MICBIAS_1,
2255 WM8996_MICB1_DISCH, 0);
2256 snd_soc_component_update_bits(component, WM8996_MICBIAS_2,
2257 WM8996_MICB2_DISCH, 0);
2258
2259 /* LDO2 powers the microphones, SYSCLK clocks detection */
2260 snd_soc_dapm_mutex_lock(dapm);
2261
2262 snd_soc_dapm_force_enable_pin_unlocked(dapm, "LDO2");
2263 snd_soc_dapm_force_enable_pin_unlocked(dapm, "SYSCLK");
2264
2265 snd_soc_dapm_mutex_unlock(dapm);
2266
2267 /* We start off just enabling microphone detection - even a
2268 * plain headphone will trigger detection.
2269 */
2270 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
2271 WM8996_MICD_ENA, WM8996_MICD_ENA);
2272
2273 /* Slowest detection rate, gives debounce for initial detection */
2274 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
2275 WM8996_MICD_RATE_MASK,
2276 WM8996_MICD_RATE_MASK);
2277
2278 /* Enable interrupts and we're off */
2279 snd_soc_component_update_bits(component, WM8996_INTERRUPT_STATUS_2_MASK,
2280 WM8996_IM_MICD_EINT | WM8996_HP_DONE_EINT, 0);
2281
2282 return 0;
2283 }
2284 EXPORT_SYMBOL_GPL(wm8996_detect);
2285
2286 static void wm8996_hpdet_irq(struct snd_soc_component *component)
2287 {
2288 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2289 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
2290 int val, reg, report;
2291
2292 /* Assume headphone in error conditions; we need to report
2293 * something or we stall our state machine.
2294 */
2295 report = SND_JACK_HEADPHONE;
2296
2297 reg = snd_soc_component_read(component, WM8996_HEADPHONE_DETECT_2);
2298 if (reg < 0) {
2299 dev_err(component->dev, "Failed to read HPDET status\n");
2300 goto out;
2301 }
2302
2303 if (!(reg & WM8996_HP_DONE)) {
2304 dev_err(component->dev, "Got HPDET IRQ but HPDET is busy\n");
2305 goto out;
2306 }
2307
2308 val = reg & WM8996_HP_LVL_MASK;
2309
2310 dev_dbg(component->dev, "HPDET measured %d ohms\n", val);
2311
2312 /* If we've got high enough impedence then report as line,
2313 * otherwise assume headphone.
2314 */
2315 if (val >= 126)
2316 report = SND_JACK_LINEOUT;
2317 else
2318 report = SND_JACK_HEADPHONE;
2319
2320 out:
2321 if (wm8996->jack_mic)
2322 report |= SND_JACK_MICROPHONE;
2323
2324 snd_soc_jack_report(wm8996->jack, report,
2325 SND_JACK_LINEOUT | SND_JACK_HEADSET);
2326
2327 wm8996->detecting = false;
2328
2329 /* If the output isn't running re-clamp it */
2330 if (!(snd_soc_component_read(component, WM8996_POWER_MANAGEMENT_1) &
2331 (WM8996_HPOUT1L_ENA | WM8996_HPOUT1R_RMV_SHORT)))
2332 snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1,
2333 WM8996_HPOUT1L_RMV_SHORT |
2334 WM8996_HPOUT1R_RMV_SHORT, 0);
2335
2336 /* Go back to looking at the microphone */
2337 snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_1,
2338 WM8996_JD_MODE_MASK, 0);
2339 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, WM8996_MICD_ENA,
2340 WM8996_MICD_ENA);
2341
2342 snd_soc_dapm_disable_pin(dapm, "Bandgap");
2343 snd_soc_dapm_sync(dapm);
2344 }
2345
2346 static void wm8996_hpdet_start(struct snd_soc_component *component)
2347 {
2348 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2349
2350 /* Unclamp the output, we can't measure while we're shorting it */
2351 snd_soc_component_update_bits(component, WM8996_ANALOGUE_HP_1,
2352 WM8996_HPOUT1L_RMV_SHORT |
2353 WM8996_HPOUT1R_RMV_SHORT,
2354 WM8996_HPOUT1L_RMV_SHORT |
2355 WM8996_HPOUT1R_RMV_SHORT);
2356
2357 /* We need bandgap for HPDET */
2358 snd_soc_dapm_force_enable_pin(dapm, "Bandgap");
2359 snd_soc_dapm_sync(dapm);
2360
2361 /* Go into headphone detect left mode */
2362 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1, WM8996_MICD_ENA, 0);
2363 snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_1,
2364 WM8996_JD_MODE_MASK, 1);
2365
2366 /* Trigger a measurement */
2367 snd_soc_component_update_bits(component, WM8996_HEADPHONE_DETECT_1,
2368 WM8996_HP_POLL, WM8996_HP_POLL);
2369 }
2370
2371 static void wm8996_report_headphone(struct snd_soc_component *component)
2372 {
2373 dev_dbg(component->dev, "Headphone detected\n");
2374 wm8996_hpdet_start(component);
2375
2376 /* Increase the detection rate a bit for responsiveness. */
2377 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
2378 WM8996_MICD_RATE_MASK |
2379 WM8996_MICD_BIAS_STARTTIME_MASK,
2380 7 << WM8996_MICD_RATE_SHIFT |
2381 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2382 }
2383
2384 static void wm8996_micd(struct snd_soc_component *component)
2385 {
2386 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
2387 int val, reg;
2388
2389 val = snd_soc_component_read(component, WM8996_MIC_DETECT_3);
2390
2391 dev_dbg(component->dev, "Microphone event: %x\n", val);
2392
2393 if (!(val & WM8996_MICD_VALID)) {
2394 dev_warn(component->dev, "Microphone detection state invalid\n");
2395 return;
2396 }
2397
2398 /* No accessory, reset everything and report removal */
2399 if (!(val & WM8996_MICD_STS)) {
2400 dev_dbg(component->dev, "Jack removal detected\n");
2401 wm8996->jack_mic = false;
2402 wm8996->detecting = true;
2403 wm8996->jack_flips = 0;
2404 snd_soc_jack_report(wm8996->jack, 0,
2405 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2406 SND_JACK_BTN_0);
2407
2408 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
2409 WM8996_MICD_RATE_MASK |
2410 WM8996_MICD_BIAS_STARTTIME_MASK,
2411 WM8996_MICD_RATE_MASK |
2412 9 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2413 return;
2414 }
2415
2416 /* If the measurement is very high we've got a microphone,
2417 * either we just detected one or if we already reported then
2418 * we've got a button release event.
2419 */
2420 if (val & 0x400) {
2421 if (wm8996->detecting) {
2422 dev_dbg(component->dev, "Microphone detected\n");
2423 wm8996->jack_mic = true;
2424 wm8996_hpdet_start(component);
2425
2426 /* Increase poll rate to give better responsiveness
2427 * for buttons */
2428 snd_soc_component_update_bits(component, WM8996_MIC_DETECT_1,
2429 WM8996_MICD_RATE_MASK |
2430 WM8996_MICD_BIAS_STARTTIME_MASK,
2431 5 << WM8996_MICD_RATE_SHIFT |
2432 7 << WM8996_MICD_BIAS_STARTTIME_SHIFT);
2433 } else {
2434 dev_dbg(component->dev, "Mic button up\n");
2435 snd_soc_jack_report(wm8996->jack, 0, SND_JACK_BTN_0);
2436 }
2437
2438 return;
2439 }
2440
2441 /* If we detected a lower impedence during initial startup
2442 * then we probably have the wrong polarity, flip it. Don't
2443 * do this for the lowest impedences to speed up detection of
2444 * plain headphones. If both polarities report a low
2445 * impedence then give up and report headphones.
2446 */
2447 if (wm8996->detecting && (val & 0x3f0)) {
2448 wm8996->jack_flips++;
2449
2450 if (wm8996->jack_flips > 1) {
2451 wm8996_report_headphone(component);
2452 return;
2453 }
2454
2455 reg = snd_soc_component_read(component, WM8996_ACCESSORY_DETECT_MODE_2);
2456 reg ^= WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2457 WM8996_MICD_BIAS_SRC;
2458 snd_soc_component_update_bits(component, WM8996_ACCESSORY_DETECT_MODE_2,
2459 WM8996_HPOUT1FB_SRC | WM8996_MICD_SRC |
2460 WM8996_MICD_BIAS_SRC, reg);
2461
2462 if (wm8996->polarity_cb)
2463 wm8996->polarity_cb(component,
2464 (reg & WM8996_MICD_SRC) != 0);
2465
2466 dev_dbg(component->dev, "Set microphone polarity to %d\n",
2467 (reg & WM8996_MICD_SRC) != 0);
2468
2469 return;
2470 }
2471
2472 /* Don't distinguish between buttons, just report any low
2473 * impedence as BTN_0.
2474 */
2475 if (val & 0x3fc) {
2476 if (wm8996->jack_mic) {
2477 dev_dbg(component->dev, "Mic button detected\n");
2478 snd_soc_jack_report(wm8996->jack, SND_JACK_BTN_0,
2479 SND_JACK_BTN_0);
2480 } else if (wm8996->detecting) {
2481 wm8996_report_headphone(component);
2482 }
2483 }
2484 }
2485
2486 static irqreturn_t wm8996_irq(int irq, void *data)
2487 {
2488 struct snd_soc_component *component = data;
2489 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
2490 int irq_val;
2491
2492 irq_val = snd_soc_component_read(component, WM8996_INTERRUPT_STATUS_2);
2493 if (irq_val < 0) {
2494 dev_err(component->dev, "Failed to read IRQ status: %d\n",
2495 irq_val);
2496 return IRQ_NONE;
2497 }
2498 irq_val &= ~snd_soc_component_read(component, WM8996_INTERRUPT_STATUS_2_MASK);
2499
2500 if (!irq_val)
2501 return IRQ_NONE;
2502
2503 snd_soc_component_write(component, WM8996_INTERRUPT_STATUS_2, irq_val);
2504
2505 if (irq_val & (WM8996_DCS_DONE_01_EINT | WM8996_DCS_DONE_23_EINT)) {
2506 dev_dbg(component->dev, "DC servo IRQ\n");
2507 complete(&wm8996->dcs_done);
2508 }
2509
2510 if (irq_val & WM8996_FIFOS_ERR_EINT)
2511 dev_err(component->dev, "Digital core FIFO error\n");
2512
2513 if (irq_val & WM8996_FLL_LOCK_EINT) {
2514 dev_dbg(component->dev, "FLL locked\n");
2515 complete(&wm8996->fll_lock);
2516 }
2517
2518 if (irq_val & WM8996_MICD_EINT)
2519 wm8996_micd(component);
2520
2521 if (irq_val & WM8996_HP_DONE_EINT)
2522 wm8996_hpdet_irq(component);
2523
2524 return IRQ_HANDLED;
2525 }
2526
2527 static irqreturn_t wm8996_edge_irq(int irq, void *data)
2528 {
2529 irqreturn_t ret = IRQ_NONE;
2530 irqreturn_t val;
2531
2532 do {
2533 val = wm8996_irq(irq, data);
2534 if (val != IRQ_NONE)
2535 ret = val;
2536 } while (val != IRQ_NONE);
2537
2538 return ret;
2539 }
2540
2541 static void wm8996_retune_mobile_pdata(struct snd_soc_component *component)
2542 {
2543 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
2544 struct wm8996_pdata *pdata = &wm8996->pdata;
2545
2546 struct snd_kcontrol_new controls[] = {
2547 SOC_ENUM_EXT("DSP1 EQ Mode",
2548 wm8996->retune_mobile_enum,
2549 wm8996_get_retune_mobile_enum,
2550 wm8996_put_retune_mobile_enum),
2551 SOC_ENUM_EXT("DSP2 EQ Mode",
2552 wm8996->retune_mobile_enum,
2553 wm8996_get_retune_mobile_enum,
2554 wm8996_put_retune_mobile_enum),
2555 };
2556 int ret, i, j;
2557 const char **t;
2558
2559 /* We need an array of texts for the enum API but the number
2560 * of texts is likely to be less than the number of
2561 * configurations due to the sample rate dependency of the
2562 * configurations. */
2563 wm8996->num_retune_mobile_texts = 0;
2564 wm8996->retune_mobile_texts = NULL;
2565 for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2566 for (j = 0; j < wm8996->num_retune_mobile_texts; j++) {
2567 if (strcmp(pdata->retune_mobile_cfgs[i].name,
2568 wm8996->retune_mobile_texts[j]) == 0)
2569 break;
2570 }
2571
2572 if (j != wm8996->num_retune_mobile_texts)
2573 continue;
2574
2575 /* Expand the array... */
2576 t = krealloc(wm8996->retune_mobile_texts,
2577 sizeof(char *) *
2578 (wm8996->num_retune_mobile_texts + 1),
2579 GFP_KERNEL);
2580 if (t == NULL)
2581 continue;
2582
2583 /* ...store the new entry... */
2584 t[wm8996->num_retune_mobile_texts] =
2585 pdata->retune_mobile_cfgs[i].name;
2586
2587 /* ...and remember the new version. */
2588 wm8996->num_retune_mobile_texts++;
2589 wm8996->retune_mobile_texts = t;
2590 }
2591
2592 dev_dbg(component->dev, "Allocated %d unique ReTune Mobile names\n",
2593 wm8996->num_retune_mobile_texts);
2594
2595 wm8996->retune_mobile_enum.items = wm8996->num_retune_mobile_texts;
2596 wm8996->retune_mobile_enum.texts = wm8996->retune_mobile_texts;
2597
2598 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
2599 if (ret != 0)
2600 dev_err(component->dev,
2601 "Failed to add ReTune Mobile controls: %d\n", ret);
2602 }
2603
2604 static const struct regmap_config wm8996_regmap = {
2605 .reg_bits = 16,
2606 .val_bits = 16,
2607
2608 .max_register = WM8996_MAX_REGISTER,
2609 .reg_defaults = wm8996_reg,
2610 .num_reg_defaults = ARRAY_SIZE(wm8996_reg),
2611 .volatile_reg = wm8996_volatile_register,
2612 .readable_reg = wm8996_readable_register,
2613 .cache_type = REGCACHE_RBTREE,
2614 };
2615
2616 static int wm8996_probe(struct snd_soc_component *component)
2617 {
2618 int ret;
2619 struct wm8996_priv *wm8996 = snd_soc_component_get_drvdata(component);
2620 struct i2c_client *i2c = to_i2c_client(component->dev);
2621 int irq_flags;
2622
2623 wm8996->component = component;
2624
2625 init_completion(&wm8996->dcs_done);
2626 init_completion(&wm8996->fll_lock);
2627
2628 if (wm8996->pdata.num_retune_mobile_cfgs)
2629 wm8996_retune_mobile_pdata(component);
2630 else
2631 snd_soc_add_component_controls(component, wm8996_eq_controls,
2632 ARRAY_SIZE(wm8996_eq_controls));
2633
2634 if (i2c->irq) {
2635 if (wm8996->pdata.irq_flags)
2636 irq_flags = wm8996->pdata.irq_flags;
2637 else
2638 irq_flags = IRQF_TRIGGER_LOW;
2639
2640 irq_flags |= IRQF_ONESHOT;
2641
2642 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2643 ret = request_threaded_irq(i2c->irq, NULL,
2644 wm8996_edge_irq,
2645 irq_flags, "wm8996", component);
2646 else
2647 ret = request_threaded_irq(i2c->irq, NULL, wm8996_irq,
2648 irq_flags, "wm8996", component);
2649
2650 if (ret == 0) {
2651 /* Unmask the interrupt */
2652 snd_soc_component_update_bits(component, WM8996_INTERRUPT_CONTROL,
2653 WM8996_IM_IRQ, 0);
2654
2655 /* Enable error reporting and DC servo status */
2656 snd_soc_component_update_bits(component,
2657 WM8996_INTERRUPT_STATUS_2_MASK,
2658 WM8996_IM_DCS_DONE_23_EINT |
2659 WM8996_IM_DCS_DONE_01_EINT |
2660 WM8996_IM_FLL_LOCK_EINT |
2661 WM8996_IM_FIFOS_ERR_EINT,
2662 0);
2663 } else {
2664 dev_err(component->dev, "Failed to request IRQ: %d\n",
2665 ret);
2666 return ret;
2667 }
2668 }
2669
2670 return 0;
2671 }
2672
2673 static void wm8996_remove(struct snd_soc_component *component)
2674 {
2675 struct i2c_client *i2c = to_i2c_client(component->dev);
2676
2677 snd_soc_component_update_bits(component, WM8996_INTERRUPT_CONTROL,
2678 WM8996_IM_IRQ, WM8996_IM_IRQ);
2679
2680 if (i2c->irq)
2681 free_irq(i2c->irq, component);
2682 }
2683
2684 static const struct snd_soc_component_driver soc_component_dev_wm8996 = {
2685 .probe = wm8996_probe,
2686 .remove = wm8996_remove,
2687 .set_bias_level = wm8996_set_bias_level,
2688 .seq_notifier = wm8996_seq_notifier,
2689 .controls = wm8996_snd_controls,
2690 .num_controls = ARRAY_SIZE(wm8996_snd_controls),
2691 .dapm_widgets = wm8996_dapm_widgets,
2692 .num_dapm_widgets = ARRAY_SIZE(wm8996_dapm_widgets),
2693 .dapm_routes = wm8996_dapm_routes,
2694 .num_dapm_routes = ARRAY_SIZE(wm8996_dapm_routes),
2695 .set_pll = wm8996_set_fll,
2696 .use_pmdown_time = 1,
2697 .endianness = 1,
2698 .non_legacy_dai_naming = 1,
2699
2700 };
2701
2702 #define WM8996_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
2703 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
2704 SNDRV_PCM_RATE_48000)
2705 #define WM8996_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE |\
2706 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE |\
2707 SNDRV_PCM_FMTBIT_S32_LE)
2708
2709 static const struct snd_soc_dai_ops wm8996_dai_ops = {
2710 .set_fmt = wm8996_set_fmt,
2711 .hw_params = wm8996_hw_params,
2712 .set_sysclk = wm8996_set_sysclk,
2713 };
2714
2715 static struct snd_soc_dai_driver wm8996_dai[] = {
2716 {
2717 .name = "wm8996-aif1",
2718 .playback = {
2719 .stream_name = "AIF1 Playback",
2720 .channels_min = 1,
2721 .channels_max = 6,
2722 .rates = WM8996_RATES,
2723 .formats = WM8996_FORMATS,
2724 .sig_bits = 24,
2725 },
2726 .capture = {
2727 .stream_name = "AIF1 Capture",
2728 .channels_min = 1,
2729 .channels_max = 6,
2730 .rates = WM8996_RATES,
2731 .formats = WM8996_FORMATS,
2732 .sig_bits = 24,
2733 },
2734 .ops = &wm8996_dai_ops,
2735 },
2736 {
2737 .name = "wm8996-aif2",
2738 .playback = {
2739 .stream_name = "AIF2 Playback",
2740 .channels_min = 1,
2741 .channels_max = 2,
2742 .rates = WM8996_RATES,
2743 .formats = WM8996_FORMATS,
2744 .sig_bits = 24,
2745 },
2746 .capture = {
2747 .stream_name = "AIF2 Capture",
2748 .channels_min = 1,
2749 .channels_max = 2,
2750 .rates = WM8996_RATES,
2751 .formats = WM8996_FORMATS,
2752 .sig_bits = 24,
2753 },
2754 .ops = &wm8996_dai_ops,
2755 },
2756 };
2757
2758 static int wm8996_i2c_probe(struct i2c_client *i2c,
2759 const struct i2c_device_id *id)
2760 {
2761 struct wm8996_priv *wm8996;
2762 int ret, i;
2763 unsigned int reg;
2764
2765 wm8996 = devm_kzalloc(&i2c->dev, sizeof(struct wm8996_priv),
2766 GFP_KERNEL);
2767 if (wm8996 == NULL)
2768 return -ENOMEM;
2769
2770 i2c_set_clientdata(i2c, wm8996);
2771 wm8996->dev = &i2c->dev;
2772
2773 if (dev_get_platdata(&i2c->dev))
2774 memcpy(&wm8996->pdata, dev_get_platdata(&i2c->dev),
2775 sizeof(wm8996->pdata));
2776
2777 if (wm8996->pdata.ldo_ena > 0) {
2778 ret = gpio_request_one(wm8996->pdata.ldo_ena,
2779 GPIOF_OUT_INIT_LOW, "WM8996 ENA");
2780 if (ret < 0) {
2781 dev_err(&i2c->dev, "Failed to request GPIO %d: %d\n",
2782 wm8996->pdata.ldo_ena, ret);
2783 goto err;
2784 }
2785 }
2786
2787 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++)
2788 wm8996->supplies[i].supply = wm8996_supply_names[i];
2789
2790 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8996->supplies),
2791 wm8996->supplies);
2792 if (ret != 0) {
2793 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
2794 goto err_gpio;
2795 }
2796
2797 wm8996->disable_nb[0].notifier_call = wm8996_regulator_event_0;
2798 wm8996->disable_nb[1].notifier_call = wm8996_regulator_event_1;
2799 wm8996->disable_nb[2].notifier_call = wm8996_regulator_event_2;
2800
2801 /* This should really be moved into the regulator core */
2802 for (i = 0; i < ARRAY_SIZE(wm8996->supplies); i++) {
2803 ret = devm_regulator_register_notifier(
2804 wm8996->supplies[i].consumer,
2805 &wm8996->disable_nb[i]);
2806 if (ret != 0) {
2807 dev_err(&i2c->dev,
2808 "Failed to register regulator notifier: %d\n",
2809 ret);
2810 }
2811 }
2812
2813 ret = regulator_bulk_enable(ARRAY_SIZE(wm8996->supplies),
2814 wm8996->supplies);
2815 if (ret != 0) {
2816 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
2817 goto err_gpio;
2818 }
2819
2820 if (wm8996->pdata.ldo_ena > 0) {
2821 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 1);
2822 msleep(5);
2823 }
2824
2825 wm8996->regmap = devm_regmap_init_i2c(i2c, &wm8996_regmap);
2826 if (IS_ERR(wm8996->regmap)) {
2827 ret = PTR_ERR(wm8996->regmap);
2828 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
2829 goto err_enable;
2830 }
2831
2832 ret = regmap_read(wm8996->regmap, WM8996_SOFTWARE_RESET, &reg);
2833 if (ret < 0) {
2834 dev_err(&i2c->dev, "Failed to read ID register: %d\n", ret);
2835 goto err_regmap;
2836 }
2837 if (reg != 0x8915) {
2838 dev_err(&i2c->dev, "Device is not a WM8996, ID %x\n", reg);
2839 ret = -EINVAL;
2840 goto err_regmap;
2841 }
2842
2843 ret = regmap_read(wm8996->regmap, WM8996_CHIP_REVISION, &reg);
2844 if (ret < 0) {
2845 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
2846 ret);
2847 goto err_regmap;
2848 }
2849
2850 dev_info(&i2c->dev, "revision %c\n",
2851 (reg & WM8996_CHIP_REV_MASK) + 'A');
2852
2853 if (wm8996->pdata.ldo_ena > 0) {
2854 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
2855 regcache_cache_only(wm8996->regmap, true);
2856 } else {
2857 ret = regmap_write(wm8996->regmap, WM8996_SOFTWARE_RESET,
2858 0x8915);
2859 if (ret != 0) {
2860 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
2861 goto err_regmap;
2862 }
2863 }
2864
2865 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
2866
2867 /* Apply platform data settings */
2868 regmap_update_bits(wm8996->regmap, WM8996_LINE_INPUT_CONTROL,
2869 WM8996_INL_MODE_MASK | WM8996_INR_MODE_MASK,
2870 wm8996->pdata.inl_mode << WM8996_INL_MODE_SHIFT |
2871 wm8996->pdata.inr_mode);
2872
2873 for (i = 0; i < ARRAY_SIZE(wm8996->pdata.gpio_default); i++) {
2874 if (!wm8996->pdata.gpio_default[i])
2875 continue;
2876
2877 regmap_write(wm8996->regmap, WM8996_GPIO_1 + i,
2878 wm8996->pdata.gpio_default[i] & 0xffff);
2879 }
2880
2881 if (wm8996->pdata.spkmute_seq)
2882 regmap_update_bits(wm8996->regmap,
2883 WM8996_PDM_SPEAKER_MUTE_SEQUENCE,
2884 WM8996_SPK_MUTE_ENDIAN |
2885 WM8996_SPK_MUTE_SEQ1_MASK,
2886 wm8996->pdata.spkmute_seq);
2887
2888 regmap_update_bits(wm8996->regmap, WM8996_ACCESSORY_DETECT_MODE_2,
2889 WM8996_MICD_BIAS_SRC | WM8996_HPOUT1FB_SRC |
2890 WM8996_MICD_SRC, wm8996->pdata.micdet_def);
2891
2892 /* Latch volume update bits */
2893 regmap_update_bits(wm8996->regmap, WM8996_LEFT_LINE_INPUT_VOLUME,
2894 WM8996_IN1_VU, WM8996_IN1_VU);
2895 regmap_update_bits(wm8996->regmap, WM8996_RIGHT_LINE_INPUT_VOLUME,
2896 WM8996_IN1_VU, WM8996_IN1_VU);
2897
2898 regmap_update_bits(wm8996->regmap, WM8996_DAC1_LEFT_VOLUME,
2899 WM8996_DAC1_VU, WM8996_DAC1_VU);
2900 regmap_update_bits(wm8996->regmap, WM8996_DAC1_RIGHT_VOLUME,
2901 WM8996_DAC1_VU, WM8996_DAC1_VU);
2902 regmap_update_bits(wm8996->regmap, WM8996_DAC2_LEFT_VOLUME,
2903 WM8996_DAC2_VU, WM8996_DAC2_VU);
2904 regmap_update_bits(wm8996->regmap, WM8996_DAC2_RIGHT_VOLUME,
2905 WM8996_DAC2_VU, WM8996_DAC2_VU);
2906
2907 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_LEFT_VOLUME,
2908 WM8996_DAC1_VU, WM8996_DAC1_VU);
2909 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT1_RIGHT_VOLUME,
2910 WM8996_DAC1_VU, WM8996_DAC1_VU);
2911 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_LEFT_VOLUME,
2912 WM8996_DAC2_VU, WM8996_DAC2_VU);
2913 regmap_update_bits(wm8996->regmap, WM8996_OUTPUT2_RIGHT_VOLUME,
2914 WM8996_DAC2_VU, WM8996_DAC2_VU);
2915
2916 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_LEFT_VOLUME,
2917 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2918 regmap_update_bits(wm8996->regmap, WM8996_DSP1_TX_RIGHT_VOLUME,
2919 WM8996_DSP1TX_VU, WM8996_DSP1TX_VU);
2920 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_LEFT_VOLUME,
2921 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2922 regmap_update_bits(wm8996->regmap, WM8996_DSP2_TX_RIGHT_VOLUME,
2923 WM8996_DSP2TX_VU, WM8996_DSP2TX_VU);
2924
2925 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_LEFT_VOLUME,
2926 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2927 regmap_update_bits(wm8996->regmap, WM8996_DSP1_RX_RIGHT_VOLUME,
2928 WM8996_DSP1RX_VU, WM8996_DSP1RX_VU);
2929 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_LEFT_VOLUME,
2930 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2931 regmap_update_bits(wm8996->regmap, WM8996_DSP2_RX_RIGHT_VOLUME,
2932 WM8996_DSP2RX_VU, WM8996_DSP2RX_VU);
2933
2934 /* No support currently for the underclocked TDM modes and
2935 * pick a default TDM layout with each channel pair working with
2936 * slots 0 and 1. */
2937 regmap_update_bits(wm8996->regmap,
2938 WM8996_AIF1RX_CHANNEL_0_CONFIGURATION,
2939 WM8996_AIF1RX_CHAN0_SLOTS_MASK |
2940 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2941 1 << WM8996_AIF1RX_CHAN0_SLOTS_SHIFT | 0);
2942 regmap_update_bits(wm8996->regmap,
2943 WM8996_AIF1RX_CHANNEL_1_CONFIGURATION,
2944 WM8996_AIF1RX_CHAN1_SLOTS_MASK |
2945 WM8996_AIF1RX_CHAN1_START_SLOT_MASK,
2946 1 << WM8996_AIF1RX_CHAN1_SLOTS_SHIFT | 1);
2947 regmap_update_bits(wm8996->regmap,
2948 WM8996_AIF1RX_CHANNEL_2_CONFIGURATION,
2949 WM8996_AIF1RX_CHAN2_SLOTS_MASK |
2950 WM8996_AIF1RX_CHAN2_START_SLOT_MASK,
2951 1 << WM8996_AIF1RX_CHAN2_SLOTS_SHIFT | 0);
2952 regmap_update_bits(wm8996->regmap,
2953 WM8996_AIF1RX_CHANNEL_3_CONFIGURATION,
2954 WM8996_AIF1RX_CHAN3_SLOTS_MASK |
2955 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2956 1 << WM8996_AIF1RX_CHAN3_SLOTS_SHIFT | 1);
2957 regmap_update_bits(wm8996->regmap,
2958 WM8996_AIF1RX_CHANNEL_4_CONFIGURATION,
2959 WM8996_AIF1RX_CHAN4_SLOTS_MASK |
2960 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2961 1 << WM8996_AIF1RX_CHAN4_SLOTS_SHIFT | 0);
2962 regmap_update_bits(wm8996->regmap,
2963 WM8996_AIF1RX_CHANNEL_5_CONFIGURATION,
2964 WM8996_AIF1RX_CHAN5_SLOTS_MASK |
2965 WM8996_AIF1RX_CHAN0_START_SLOT_MASK,
2966 1 << WM8996_AIF1RX_CHAN5_SLOTS_SHIFT | 1);
2967
2968 regmap_update_bits(wm8996->regmap,
2969 WM8996_AIF2RX_CHANNEL_0_CONFIGURATION,
2970 WM8996_AIF2RX_CHAN0_SLOTS_MASK |
2971 WM8996_AIF2RX_CHAN0_START_SLOT_MASK,
2972 1 << WM8996_AIF2RX_CHAN0_SLOTS_SHIFT | 0);
2973 regmap_update_bits(wm8996->regmap,
2974 WM8996_AIF2RX_CHANNEL_1_CONFIGURATION,
2975 WM8996_AIF2RX_CHAN1_SLOTS_MASK |
2976 WM8996_AIF2RX_CHAN1_START_SLOT_MASK,
2977 1 << WM8996_AIF2RX_CHAN1_SLOTS_SHIFT | 1);
2978
2979 regmap_update_bits(wm8996->regmap,
2980 WM8996_AIF1TX_CHANNEL_0_CONFIGURATION,
2981 WM8996_AIF1TX_CHAN0_SLOTS_MASK |
2982 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2983 1 << WM8996_AIF1TX_CHAN0_SLOTS_SHIFT | 0);
2984 regmap_update_bits(wm8996->regmap,
2985 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
2986 WM8996_AIF1TX_CHAN1_SLOTS_MASK |
2987 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2988 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
2989 regmap_update_bits(wm8996->regmap,
2990 WM8996_AIF1TX_CHANNEL_2_CONFIGURATION,
2991 WM8996_AIF1TX_CHAN2_SLOTS_MASK |
2992 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2993 1 << WM8996_AIF1TX_CHAN2_SLOTS_SHIFT | 0);
2994 regmap_update_bits(wm8996->regmap,
2995 WM8996_AIF1TX_CHANNEL_3_CONFIGURATION,
2996 WM8996_AIF1TX_CHAN3_SLOTS_MASK |
2997 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
2998 1 << WM8996_AIF1TX_CHAN3_SLOTS_SHIFT | 1);
2999 regmap_update_bits(wm8996->regmap,
3000 WM8996_AIF1TX_CHANNEL_4_CONFIGURATION,
3001 WM8996_AIF1TX_CHAN4_SLOTS_MASK |
3002 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3003 1 << WM8996_AIF1TX_CHAN4_SLOTS_SHIFT | 0);
3004 regmap_update_bits(wm8996->regmap,
3005 WM8996_AIF1TX_CHANNEL_5_CONFIGURATION,
3006 WM8996_AIF1TX_CHAN5_SLOTS_MASK |
3007 WM8996_AIF1TX_CHAN0_START_SLOT_MASK,
3008 1 << WM8996_AIF1TX_CHAN5_SLOTS_SHIFT | 1);
3009
3010 regmap_update_bits(wm8996->regmap,
3011 WM8996_AIF2TX_CHANNEL_0_CONFIGURATION,
3012 WM8996_AIF2TX_CHAN0_SLOTS_MASK |
3013 WM8996_AIF2TX_CHAN0_START_SLOT_MASK,
3014 1 << WM8996_AIF2TX_CHAN0_SLOTS_SHIFT | 0);
3015 regmap_update_bits(wm8996->regmap,
3016 WM8996_AIF1TX_CHANNEL_1_CONFIGURATION,
3017 WM8996_AIF2TX_CHAN1_SLOTS_MASK |
3018 WM8996_AIF2TX_CHAN1_START_SLOT_MASK,
3019 1 << WM8996_AIF1TX_CHAN1_SLOTS_SHIFT | 1);
3020
3021 /* If the TX LRCLK pins are not in LRCLK mode configure the
3022 * AIFs to source their clocks from the RX LRCLKs.
3023 */
3024 ret = regmap_read(wm8996->regmap, WM8996_GPIO_1, &reg);
3025 if (ret != 0) {
3026 dev_err(&i2c->dev, "Failed to read GPIO1: %d\n", ret);
3027 goto err_regmap;
3028 }
3029
3030 if (reg & WM8996_GP1_FN_MASK)
3031 regmap_update_bits(wm8996->regmap, WM8996_AIF1_TX_LRCLK_2,
3032 WM8996_AIF1TX_LRCLK_MODE,
3033 WM8996_AIF1TX_LRCLK_MODE);
3034
3035 ret = regmap_read(wm8996->regmap, WM8996_GPIO_2, &reg);
3036 if (ret != 0) {
3037 dev_err(&i2c->dev, "Failed to read GPIO2: %d\n", ret);
3038 goto err_regmap;
3039 }
3040
3041 if (reg & WM8996_GP2_FN_MASK)
3042 regmap_update_bits(wm8996->regmap, WM8996_AIF2_TX_LRCLK_2,
3043 WM8996_AIF2TX_LRCLK_MODE,
3044 WM8996_AIF2TX_LRCLK_MODE);
3045
3046 wm8996_init_gpio(wm8996);
3047
3048 ret = devm_snd_soc_register_component(&i2c->dev,
3049 &soc_component_dev_wm8996, wm8996_dai,
3050 ARRAY_SIZE(wm8996_dai));
3051 if (ret < 0)
3052 goto err_gpiolib;
3053
3054 return ret;
3055
3056 err_gpiolib:
3057 wm8996_free_gpio(wm8996);
3058 err_regmap:
3059 err_enable:
3060 if (wm8996->pdata.ldo_ena > 0)
3061 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3062 regulator_bulk_disable(ARRAY_SIZE(wm8996->supplies), wm8996->supplies);
3063 err_gpio:
3064 if (wm8996->pdata.ldo_ena > 0)
3065 gpio_free(wm8996->pdata.ldo_ena);
3066 err:
3067
3068 return ret;
3069 }
3070
3071 static int wm8996_i2c_remove(struct i2c_client *client)
3072 {
3073 struct wm8996_priv *wm8996 = i2c_get_clientdata(client);
3074
3075 wm8996_free_gpio(wm8996);
3076 if (wm8996->pdata.ldo_ena > 0) {
3077 gpio_set_value_cansleep(wm8996->pdata.ldo_ena, 0);
3078 gpio_free(wm8996->pdata.ldo_ena);
3079 }
3080
3081 return 0;
3082 }
3083
3084 static const struct i2c_device_id wm8996_i2c_id[] = {
3085 { "wm8996", 0 },
3086 { }
3087 };
3088 MODULE_DEVICE_TABLE(i2c, wm8996_i2c_id);
3089
3090 static struct i2c_driver wm8996_i2c_driver = {
3091 .driver = {
3092 .name = "wm8996",
3093 },
3094 .probe = wm8996_i2c_probe,
3095 .remove = wm8996_i2c_remove,
3096 .id_table = wm8996_i2c_id,
3097 };
3098
3099 module_i2c_driver(wm8996_i2c_driver);
3100
3101 MODULE_DESCRIPTION("ASoC WM8996 driver");
3102 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3103 MODULE_LICENSE("GPL");
Linux with added FPC-III support