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sched: Remove double_rq_lock() from __migrate_task()
[linux/fpc-iii.git] / drivers / media / tuners / r820t.c
blob96ccfebce7cad32f8891c04be9bdddc71b6e152d
1 /*
2 * Rafael Micro R820T driver
3 *
4 * Copyright (C) 2013 Mauro Carvalho Chehab
5 *
6 * This driver was written from scratch, based on an existing driver
7 * that it is part of rtl-sdr git tree, released under GPLv2:
8 * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
9 * https://github.com/n1gp/gr-baz
10 *
11 * From what I understood from the threads, the original driver was converted
12 * to userspace from a Realtek tree. I couldn't find the original tree.
13 * However, the original driver look awkward on my eyes. So, I decided to
14 * write a new version from it from the scratch, while trying to reproduce
15 * everything found there.
16 *
17 * TODO:
18 * After locking, the original driver seems to have some routines to
19 * improve reception. This was not implemented here yet.
20 *
21 * RF Gain set/get is not implemented.
22 *
23 * This program is free software; you can redistribute it and/or modify
24 * it under the terms of the GNU General Public License as published by
25 * the Free Software Foundation; either version 2 of the License, or
26 * (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 */
34
35 #include <linux/videodev2.h>
36 #include <linux/mutex.h>
37 #include <linux/slab.h>
38 #include <linux/bitrev.h>
39
40 #include "tuner-i2c.h"
41 #include "r820t.h"
42
43 /*
44 * FIXME: I think that there are only 32 registers, but better safe than
45 * sorry. After finishing the driver, we may review it.
46 */
47 #define REG_SHADOW_START 5
48 #define NUM_REGS 27
49 #define NUM_IMR 5
50 #define IMR_TRIAL 9
51
52 #define VER_NUM 49
53
54 static int debug;
55 module_param(debug, int, 0644);
56 MODULE_PARM_DESC(debug, "enable verbose debug messages");
57
58 static int no_imr_cal;
59 module_param(no_imr_cal, int, 0444);
60 MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
61
62
63 /*
64 * enums and structures
65 */
66
67 enum xtal_cap_value {
68 XTAL_LOW_CAP_30P = 0,
69 XTAL_LOW_CAP_20P,
70 XTAL_LOW_CAP_10P,
71 XTAL_LOW_CAP_0P,
72 XTAL_HIGH_CAP_0P
73 };
74
75 struct r820t_sect_type {
76 u8 phase_y;
77 u8 gain_x;
78 u16 value;
79 };
80
81 struct r820t_priv {
82 struct list_head hybrid_tuner_instance_list;
83 const struct r820t_config *cfg;
84 struct tuner_i2c_props i2c_props;
85 struct mutex lock;
86
87 u8 regs[NUM_REGS];
88 u8 buf[NUM_REGS + 1];
89 enum xtal_cap_value xtal_cap_sel;
90 u16 pll; /* kHz */
91 u32 int_freq;
92 u8 fil_cal_code;
93 bool imr_done;
94 bool has_lock;
95 bool init_done;
96 struct r820t_sect_type imr_data[NUM_IMR];
97
98 /* Store current mode */
99 u32 delsys;
100 enum v4l2_tuner_type type;
101 v4l2_std_id std;
102 u32 bw; /* in MHz */
103 };
104
105 struct r820t_freq_range {
106 u32 freq;
107 u8 open_d;
108 u8 rf_mux_ploy;
109 u8 tf_c;
110 u8 xtal_cap20p;
111 u8 xtal_cap10p;
112 u8 xtal_cap0p;
113 u8 imr_mem; /* Not used, currently */
114 };
115
116 #define VCO_POWER_REF 0x02
117 #define DIP_FREQ 32000000
118
119 /*
120 * Static constants
121 */
122
123 static LIST_HEAD(hybrid_tuner_instance_list);
124 static DEFINE_MUTEX(r820t_list_mutex);
125
126 /* Those initial values start from REG_SHADOW_START */
127 static const u8 r820t_init_array[NUM_REGS] = {
128 0x83, 0x32, 0x75, /* 05 to 07 */
129 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
130 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
131 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
132 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
133 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
134 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
135 };
136
137 /* Tuner frequency ranges */
138 static const struct r820t_freq_range freq_ranges[] = {
139 {
140 .freq = 0,
141 .open_d = 0x08, /* low */
142 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
143 .tf_c = 0xdf, /* R27[7:0] band2,band0 */
144 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
145 .xtal_cap10p = 0x01,
146 .xtal_cap0p = 0x00,
147 .imr_mem = 0,
148 }, {
149 .freq = 50, /* Start freq, in MHz */
150 .open_d = 0x08, /* low */
151 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
152 .tf_c = 0xbe, /* R27[7:0] band4,band1 */
153 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
154 .xtal_cap10p = 0x01,
155 .xtal_cap0p = 0x00,
156 .imr_mem = 0,
157 }, {
158 .freq = 55, /* Start freq, in MHz */
159 .open_d = 0x08, /* low */
160 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
161 .tf_c = 0x8b, /* R27[7:0] band7,band4 */
162 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
163 .xtal_cap10p = 0x01,
164 .xtal_cap0p = 0x00,
165 .imr_mem = 0,
166 }, {
167 .freq = 60, /* Start freq, in MHz */
168 .open_d = 0x08, /* low */
169 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
170 .tf_c = 0x7b, /* R27[7:0] band8,band4 */
171 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
172 .xtal_cap10p = 0x01,
173 .xtal_cap0p = 0x00,
174 .imr_mem = 0,
175 }, {
176 .freq = 65, /* Start freq, in MHz */
177 .open_d = 0x08, /* low */
178 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
179 .tf_c = 0x69, /* R27[7:0] band9,band6 */
180 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
181 .xtal_cap10p = 0x01,
182 .xtal_cap0p = 0x00,
183 .imr_mem = 0,
184 }, {
185 .freq = 70, /* Start freq, in MHz */
186 .open_d = 0x08, /* low */
187 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
188 .tf_c = 0x58, /* R27[7:0] band10,band7 */
189 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
190 .xtal_cap10p = 0x01,
191 .xtal_cap0p = 0x00,
192 .imr_mem = 0,
193 }, {
194 .freq = 75, /* Start freq, in MHz */
195 .open_d = 0x00, /* high */
196 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
197 .tf_c = 0x44, /* R27[7:0] band11,band11 */
198 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
199 .xtal_cap10p = 0x01,
200 .xtal_cap0p = 0x00,
201 .imr_mem = 0,
202 }, {
203 .freq = 80, /* Start freq, in MHz */
204 .open_d = 0x00, /* high */
205 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
206 .tf_c = 0x44, /* R27[7:0] band11,band11 */
207 .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
208 .xtal_cap10p = 0x01,
209 .xtal_cap0p = 0x00,
210 .imr_mem = 0,
211 }, {
212 .freq = 90, /* Start freq, in MHz */
213 .open_d = 0x00, /* high */
214 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
215 .tf_c = 0x34, /* R27[7:0] band12,band11 */
216 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
217 .xtal_cap10p = 0x01,
218 .xtal_cap0p = 0x00,
219 .imr_mem = 0,
220 }, {
221 .freq = 100, /* Start freq, in MHz */
222 .open_d = 0x00, /* high */
223 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
224 .tf_c = 0x34, /* R27[7:0] band12,band11 */
225 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
226 .xtal_cap10p = 0x01,
227 .xtal_cap0p = 0x00,
228 .imr_mem = 0,
229 }, {
230 .freq = 110, /* Start freq, in MHz */
231 .open_d = 0x00, /* high */
232 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
233 .tf_c = 0x24, /* R27[7:0] band13,band11 */
234 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
235 .xtal_cap10p = 0x01,
236 .xtal_cap0p = 0x00,
237 .imr_mem = 1,
238 }, {
239 .freq = 120, /* Start freq, in MHz */
240 .open_d = 0x00, /* high */
241 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
242 .tf_c = 0x24, /* R27[7:0] band13,band11 */
243 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
244 .xtal_cap10p = 0x01,
245 .xtal_cap0p = 0x00,
246 .imr_mem = 1,
247 }, {
248 .freq = 140, /* Start freq, in MHz */
249 .open_d = 0x00, /* high */
250 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
251 .tf_c = 0x14, /* R27[7:0] band14,band11 */
252 .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
253 .xtal_cap10p = 0x01,
254 .xtal_cap0p = 0x00,
255 .imr_mem = 1,
256 }, {
257 .freq = 180, /* Start freq, in MHz */
258 .open_d = 0x00, /* high */
259 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
260 .tf_c = 0x13, /* R27[7:0] band14,band12 */
261 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
262 .xtal_cap10p = 0x00,
263 .xtal_cap0p = 0x00,
264 .imr_mem = 1,
265 }, {
266 .freq = 220, /* Start freq, in MHz */
267 .open_d = 0x00, /* high */
268 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
269 .tf_c = 0x13, /* R27[7:0] band14,band12 */
270 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
271 .xtal_cap10p = 0x00,
272 .xtal_cap0p = 0x00,
273 .imr_mem = 2,
274 }, {
275 .freq = 250, /* Start freq, in MHz */
276 .open_d = 0x00, /* high */
277 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
278 .tf_c = 0x11, /* R27[7:0] highest,highest */
279 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
280 .xtal_cap10p = 0x00,
281 .xtal_cap0p = 0x00,
282 .imr_mem = 2,
283 }, {
284 .freq = 280, /* Start freq, in MHz */
285 .open_d = 0x00, /* high */
286 .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
287 .tf_c = 0x00, /* R27[7:0] highest,highest */
288 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
289 .xtal_cap10p = 0x00,
290 .xtal_cap0p = 0x00,
291 .imr_mem = 2,
292 }, {
293 .freq = 310, /* Start freq, in MHz */
294 .open_d = 0x00, /* high */
295 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
296 .tf_c = 0x00, /* R27[7:0] highest,highest */
297 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
298 .xtal_cap10p = 0x00,
299 .xtal_cap0p = 0x00,
300 .imr_mem = 2,
301 }, {
302 .freq = 450, /* Start freq, in MHz */
303 .open_d = 0x00, /* high */
304 .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
305 .tf_c = 0x00, /* R27[7:0] highest,highest */
306 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
307 .xtal_cap10p = 0x00,
308 .xtal_cap0p = 0x00,
309 .imr_mem = 3,
310 }, {
311 .freq = 588, /* Start freq, in MHz */
312 .open_d = 0x00, /* high */
313 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
314 .tf_c = 0x00, /* R27[7:0] highest,highest */
315 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
316 .xtal_cap10p = 0x00,
317 .xtal_cap0p = 0x00,
318 .imr_mem = 3,
319 }, {
320 .freq = 650, /* Start freq, in MHz */
321 .open_d = 0x00, /* high */
322 .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
323 .tf_c = 0x00, /* R27[7:0] highest,highest */
324 .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
325 .xtal_cap10p = 0x00,
326 .xtal_cap0p = 0x00,
327 .imr_mem = 4,
328 }
329 };
330
331 static int r820t_xtal_capacitor[][2] = {
332 { 0x0b, XTAL_LOW_CAP_30P },
333 { 0x02, XTAL_LOW_CAP_20P },
334 { 0x01, XTAL_LOW_CAP_10P },
335 { 0x00, XTAL_LOW_CAP_0P },
336 { 0x10, XTAL_HIGH_CAP_0P },
337 };
338
339 /*
340 * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
341 * input power, for raw results see:
342 * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
343 */
344
345 static const int r820t_lna_gain_steps[] = {
346 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
347 };
348
349 static const int r820t_mixer_gain_steps[] = {
350 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
351 };
352
353 /*
354 * I2C read/write code and shadow registers logic
355 */
356 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
357 int len)
358 {
359 int r = reg - REG_SHADOW_START;
360
361 if (r < 0) {
362 len += r;
363 r = 0;
364 }
365 if (len <= 0)
366 return;
367 if (len > NUM_REGS - r)
368 len = NUM_REGS - r;
369
370 tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
371 __func__, r + REG_SHADOW_START, len, len, val);
372
373 memcpy(&priv->regs[r], val, len);
374 }
375
376 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
377 int len)
378 {
379 int rc, size, pos = 0;
380
381 /* Store the shadow registers */
382 shadow_store(priv, reg, val, len);
383
384 do {
385 if (len > priv->cfg->max_i2c_msg_len - 1)
386 size = priv->cfg->max_i2c_msg_len - 1;
387 else
388 size = len;
389
390 /* Fill I2C buffer */
391 priv->buf[0] = reg;
392 memcpy(&priv->buf[1], &val[pos], size);
393
394 rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
395 if (rc != size + 1) {
396 tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
397 __func__, rc, reg, size, size, &priv->buf[1]);
398 if (rc < 0)
399 return rc;
400 return -EREMOTEIO;
401 }
402 tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
403 __func__, reg, size, size, &priv->buf[1]);
404
405 reg += size;
406 len -= size;
407 pos += size;
408 } while (len > 0);
409
410 return 0;
411 }
412
413 static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
414 {
415 return r820t_write(priv, reg, &val, 1);
416 }
417
418 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
419 {
420 reg -= REG_SHADOW_START;
421
422 if (reg >= 0 && reg < NUM_REGS)
423 return priv->regs[reg];
424 else
425 return -EINVAL;
426 }
427
428 static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
429 u8 bit_mask)
430 {
431 int rc = r820t_read_cache_reg(priv, reg);
432
433 if (rc < 0)
434 return rc;
435
436 val = (rc & ~bit_mask) | (val & bit_mask);
437
438 return r820t_write(priv, reg, &val, 1);
439 }
440
441 static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
442 {
443 int rc, i;
444 u8 *p = &priv->buf[1];
445
446 priv->buf[0] = reg;
447
448 rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
449 if (rc != len) {
450 tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
451 __func__, rc, reg, len, len, p);
452 if (rc < 0)
453 return rc;
454 return -EREMOTEIO;
455 }
456
457 /* Copy data to the output buffer */
458 for (i = 0; i < len; i++)
459 val[i] = bitrev8(p[i]);
460
461 tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
462 __func__, reg, len, len, val);
463
464 return 0;
465 }
466
467 /*
468 * r820t tuning logic
469 */
470
471 static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
472 {
473 const struct r820t_freq_range *range;
474 int i, rc;
475 u8 val, reg08, reg09;
476
477 /* Get the proper frequency range */
478 freq = freq / 1000000;
479 for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
480 if (freq < freq_ranges[i + 1].freq)
481 break;
482 }
483 range = &freq_ranges[i];
484
485 tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
486
487 /* Open Drain */
488 rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
489 if (rc < 0)
490 return rc;
491
492 /* RF_MUX,Polymux */
493 rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
494 if (rc < 0)
495 return rc;
496
497 /* TF BAND */
498 rc = r820t_write_reg(priv, 0x1b, range->tf_c);
499 if (rc < 0)
500 return rc;
501
502 /* XTAL CAP & Drive */
503 switch (priv->xtal_cap_sel) {
504 case XTAL_LOW_CAP_30P:
505 case XTAL_LOW_CAP_20P:
506 val = range->xtal_cap20p | 0x08;
507 break;
508 case XTAL_LOW_CAP_10P:
509 val = range->xtal_cap10p | 0x08;
510 break;
511 case XTAL_HIGH_CAP_0P:
512 val = range->xtal_cap0p | 0x00;
513 break;
514 default:
515 case XTAL_LOW_CAP_0P:
516 val = range->xtal_cap0p | 0x08;
517 break;
518 }
519 rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
520 if (rc < 0)
521 return rc;
522
523 if (priv->imr_done) {
524 reg08 = priv->imr_data[range->imr_mem].gain_x;
525 reg09 = priv->imr_data[range->imr_mem].phase_y;
526 } else {
527 reg08 = 0;
528 reg09 = 0;
529 }
530 rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
531 if (rc < 0)
532 return rc;
533
534 rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
535
536 return rc;
537 }
538
539 static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
540 u32 freq)
541 {
542 u32 vco_freq;
543 int rc, i;
544 unsigned sleep_time = 10000;
545 u32 vco_fra; /* VCO contribution by SDM (kHz) */
546 u32 vco_min = 1770000;
547 u32 vco_max = vco_min * 2;
548 u32 pll_ref;
549 u16 n_sdm = 2;
550 u16 sdm = 0;
551 u8 mix_div = 2;
552 u8 div_buf = 0;
553 u8 div_num = 0;
554 u8 refdiv2 = 0;
555 u8 ni, si, nint, vco_fine_tune, val;
556 u8 data[5];
557
558 /* Frequency in kHz */
559 freq = freq / 1000;
560 pll_ref = priv->cfg->xtal / 1000;
561
562 #if 0
563 /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */
564 if ((priv->cfg->rafael_chip == CHIP_R620D) ||
565 (priv->cfg->rafael_chip == CHIP_R828D) ||
566 (priv->cfg->rafael_chip == CHIP_R828)) {
567 /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
568 if (type != V4L2_TUNER_DIGITAL_TV) {
569 pll_ref /= 2;
570 refdiv2 = 0x10;
571 sleep_time = 20000;
572 }
573 } else {
574 if (priv->cfg->xtal > 24000000) {
575 pll_ref /= 2;
576 refdiv2 = 0x10;
577 }
578 }
579 #endif
580
581 rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
582 if (rc < 0)
583 return rc;
584
585 /* set pll autotune = 128kHz */
586 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
587 if (rc < 0)
588 return rc;
589
590 /* set VCO current = 100 */
591 rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
592 if (rc < 0)
593 return rc;
594
595 /* Calculate divider */
596 while (mix_div <= 64) {
597 if (((freq * mix_div) >= vco_min) &&
598 ((freq * mix_div) < vco_max)) {
599 div_buf = mix_div;
600 while (div_buf > 2) {
601 div_buf = div_buf >> 1;
602 div_num++;
603 }
604 break;
605 }
606 mix_div = mix_div << 1;
607 }
608
609 rc = r820t_read(priv, 0x00, data, sizeof(data));
610 if (rc < 0)
611 return rc;
612
613 vco_fine_tune = (data[4] & 0x30) >> 4;
614
615 tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n",
616 mix_div, div_num, vco_fine_tune);
617
618 /*
619 * XXX: R828D/16MHz seems to have always vco_fine_tune=1.
620 * Due to that, this calculation goes wrong.
621 */
622 if (priv->cfg->rafael_chip != CHIP_R828D) {
623 if (vco_fine_tune > VCO_POWER_REF)
624 div_num = div_num - 1;
625 else if (vco_fine_tune < VCO_POWER_REF)
626 div_num = div_num + 1;
627 }
628
629 rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
630 if (rc < 0)
631 return rc;
632
633 vco_freq = freq * mix_div;
634 nint = vco_freq / (2 * pll_ref);
635 vco_fra = vco_freq - 2 * pll_ref * nint;
636
637 /* boundary spur prevention */
638 if (vco_fra < pll_ref / 64) {
639 vco_fra = 0;
640 } else if (vco_fra > pll_ref * 127 / 64) {
641 vco_fra = 0;
642 nint++;
643 } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
644 vco_fra = pll_ref * 127 / 128;
645 } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
646 vco_fra = pll_ref * 129 / 128;
647 }
648
649 ni = (nint - 13) / 4;
650 si = nint - 4 * ni - 13;
651
652 rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
653 if (rc < 0)
654 return rc;
655
656 /* pw_sdm */
657 if (!vco_fra)
658 val = 0x08;
659 else
660 val = 0x00;
661
662 rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
663 if (rc < 0)
664 return rc;
665
666 /* sdm calculator */
667 while (vco_fra > 1) {
668 if (vco_fra > (2 * pll_ref / n_sdm)) {
669 sdm = sdm + 32768 / (n_sdm / 2);
670 vco_fra = vco_fra - 2 * pll_ref / n_sdm;
671 if (n_sdm >= 0x8000)
672 break;
673 }
674 n_sdm = n_sdm << 1;
675 }
676
677 tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
678 freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
679
680 rc = r820t_write_reg(priv, 0x16, sdm >> 8);
681 if (rc < 0)
682 return rc;
683 rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
684 if (rc < 0)
685 return rc;
686
687 for (i = 0; i < 2; i++) {
688 usleep_range(sleep_time, sleep_time + 1000);
689
690 /* Check if PLL has locked */
691 rc = r820t_read(priv, 0x00, data, 3);
692 if (rc < 0)
693 return rc;
694 if (data[2] & 0x40)
695 break;
696
697 if (!i) {
698 /* Didn't lock. Increase VCO current */
699 rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
700 if (rc < 0)
701 return rc;
702 }
703 }
704
705 if (!(data[2] & 0x40)) {
706 priv->has_lock = false;
707 return 0;
708 }
709
710 priv->has_lock = true;
711 tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
712
713 /* set pll autotune = 8kHz */
714 rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
715
716 return rc;
717 }
718
719 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
720 enum v4l2_tuner_type type,
721 v4l2_std_id std,
722 u32 delsys)
723 {
724 int rc;
725 u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
726 u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
727
728 tuner_dbg("adjusting tuner parameters for the standard\n");
729
730 switch (delsys) {
731 case SYS_DVBT:
732 if ((freq == 506000000) || (freq == 666000000) ||
733 (freq == 818000000)) {
734 mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */
735 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
736 cp_cur = 0x28; /* 101, 0.2 */
737 div_buf_cur = 0x20; /* 10, 200u */
738 } else {
739 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
740 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
741 cp_cur = 0x38; /* 111, auto */
742 div_buf_cur = 0x30; /* 11, 150u */
743 }
744 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
745 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
746 air_cable1_in = 0x00;
747 cable2_in = 0x00;
748 pre_dect = 0x40;
749 lna_discharge = 14;
750 filter_cur = 0x40; /* 10, low */
751 break;
752 case SYS_DVBT2:
753 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
754 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
755 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
756 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
757 air_cable1_in = 0x00;
758 cable2_in = 0x00;
759 pre_dect = 0x40;
760 lna_discharge = 14;
761 cp_cur = 0x38; /* 111, auto */
762 div_buf_cur = 0x30; /* 11, 150u */
763 filter_cur = 0x40; /* 10, low */
764 break;
765 case SYS_ISDBT:
766 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
767 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
768 lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */
769 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
770 air_cable1_in = 0x00;
771 cable2_in = 0x00;
772 pre_dect = 0x40;
773 lna_discharge = 14;
774 cp_cur = 0x38; /* 111, auto */
775 div_buf_cur = 0x30; /* 11, 150u */
776 filter_cur = 0x40; /* 10, low */
777 break;
778 default: /* DVB-T 8M */
779 mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
780 lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
781 lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
782 mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
783 air_cable1_in = 0x00;
784 cable2_in = 0x00;
785 pre_dect = 0x40;
786 lna_discharge = 14;
787 cp_cur = 0x38; /* 111, auto */
788 div_buf_cur = 0x30; /* 11, 150u */
789 filter_cur = 0x40; /* 10, low */
790 break;
791 }
792
793 if (priv->cfg->use_diplexer &&
794 ((priv->cfg->rafael_chip == CHIP_R820T) ||
795 (priv->cfg->rafael_chip == CHIP_R828S) ||
796 (priv->cfg->rafael_chip == CHIP_R820C))) {
797 if (freq > DIP_FREQ)
798 air_cable1_in = 0x00;
799 else
800 air_cable1_in = 0x60;
801 cable2_in = 0x00;
802 }
803
804
805 if (priv->cfg->use_predetect) {
806 rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40);
807 if (rc < 0)
808 return rc;
809 }
810
811 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
812 if (rc < 0)
813 return rc;
814 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
815 if (rc < 0)
816 return rc;
817 rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
818 if (rc < 0)
819 return rc;
820 rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
821 if (rc < 0)
822 return rc;
823
824 /* Air-IN only for Astrometa */
825 rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
826 if (rc < 0)
827 return rc;
828 rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
829 if (rc < 0)
830 return rc;
831
832 rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
833 if (rc < 0)
834 return rc;
835 rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
836 if (rc < 0)
837 return rc;
838 rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
839 if (rc < 0)
840 return rc;
841 /*
842 * Original driver initializes regs 0x05 and 0x06 with the
843 * same value again on this point. Probably, it is just an
844 * error there
845 */
846
847 /*
848 * Set LNA
849 */
850
851 tuner_dbg("adjusting LNA parameters\n");
852 if (type != V4L2_TUNER_ANALOG_TV) {
853 /* LNA TOP: lowest */
854 rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
855 if (rc < 0)
856 return rc;
857
858 /* 0: normal mode */
859 rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
860 if (rc < 0)
861 return rc;
862
863 /* 0: PRE_DECT off */
864 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
865 if (rc < 0)
866 return rc;
867
868 /* agc clk 250hz */
869 rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
870 if (rc < 0)
871 return rc;
872
873 msleep(250);
874
875 /* write LNA TOP = 3 */
876 rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
877 if (rc < 0)
878 return rc;
879
880 /*
881 * write discharge mode
882 * FIXME: IMHO, the mask here is wrong, but it matches
883 * what's there at the original driver
884 */
885 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
886 if (rc < 0)
887 return rc;
888
889 /* LNA discharge current */
890 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
891 if (rc < 0)
892 return rc;
893
894 /* agc clk 60hz */
895 rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
896 if (rc < 0)
897 return rc;
898 } else {
899 /* PRE_DECT off */
900 rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
901 if (rc < 0)
902 return rc;
903
904 /* write LNA TOP */
905 rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
906 if (rc < 0)
907 return rc;
908
909 /*
910 * write discharge mode
911 * FIXME: IMHO, the mask here is wrong, but it matches
912 * what's there at the original driver
913 */
914 rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
915 if (rc < 0)
916 return rc;
917
918 /* LNA discharge current */
919 rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
920 if (rc < 0)
921 return rc;
922
923 /* agc clk 1Khz, external det1 cap 1u */
924 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
925 if (rc < 0)
926 return rc;
927
928 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
929 if (rc < 0)
930 return rc;
931 }
932 return 0;
933 }
934
935 static int r820t_set_tv_standard(struct r820t_priv *priv,
936 unsigned bw,
937 enum v4l2_tuner_type type,
938 v4l2_std_id std, u32 delsys)
939
940 {
941 int rc, i;
942 u32 if_khz, filt_cal_lo;
943 u8 data[5], val;
944 u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
945 u8 lt_att, flt_ext_widest, polyfil_cur;
946 bool need_calibration;
947
948 tuner_dbg("selecting the delivery system\n");
949
950 if (delsys == SYS_ISDBT) {
951 if_khz = 4063;
952 filt_cal_lo = 59000;
953 filt_gain = 0x10; /* +3db, 6mhz on */
954 img_r = 0x00; /* image negative */
955 filt_q = 0x10; /* r10[4]:low q(1'b1) */
956 hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
957 ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
958 loop_through = 0x00; /* r5[7], lt on */
959 lt_att = 0x00; /* r31[7], lt att enable */
960 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
961 polyfil_cur = 0x60; /* r25[6:5]:min */
962 } else {
963 if (bw <= 6) {
964 if_khz = 3570;
965 filt_cal_lo = 56000; /* 52000->56000 */
966 filt_gain = 0x10; /* +3db, 6mhz on */
967 img_r = 0x00; /* image negative */
968 filt_q = 0x10; /* r10[4]:low q(1'b1) */
969 hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
970 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
971 loop_through = 0x00; /* r5[7], lt on */
972 lt_att = 0x00; /* r31[7], lt att enable */
973 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
974 polyfil_cur = 0x60; /* r25[6:5]:min */
975 } else if (bw == 7) {
976 #if 0
977 /*
978 * There are two 7 MHz tables defined on the original
979 * driver, but just the second one seems to be visible
980 * by rtl2832. Keep this one here commented, as it
981 * might be needed in the future
982 */
983
984 if_khz = 4070;
985 filt_cal_lo = 60000;
986 filt_gain = 0x10; /* +3db, 6mhz on */
987 img_r = 0x00; /* image negative */
988 filt_q = 0x10; /* r10[4]:low q(1'b1) */
989 hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
990 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
991 loop_through = 0x00; /* r5[7], lt on */
992 lt_att = 0x00; /* r31[7], lt att enable */
993 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
994 polyfil_cur = 0x60; /* r25[6:5]:min */
995 #endif
996 /* 7 MHz, second table */
997 if_khz = 4570;
998 filt_cal_lo = 63000;
999 filt_gain = 0x10; /* +3db, 6mhz on */
1000 img_r = 0x00; /* image negative */
1001 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1002 hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
1003 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1004 loop_through = 0x00; /* r5[7], lt on */
1005 lt_att = 0x00; /* r31[7], lt att enable */
1006 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1007 polyfil_cur = 0x60; /* r25[6:5]:min */
1008 } else {
1009 if_khz = 4570;
1010 filt_cal_lo = 68500;
1011 filt_gain = 0x10; /* +3db, 6mhz on */
1012 img_r = 0x00; /* image negative */
1013 filt_q = 0x10; /* r10[4]:low q(1'b1) */
1014 hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
1015 ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1016 loop_through = 0x00; /* r5[7], lt on */
1017 lt_att = 0x00; /* r31[7], lt att enable */
1018 flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
1019 polyfil_cur = 0x60; /* r25[6:5]:min */
1020 }
1021 }
1022
1023 /* Initialize the shadow registers */
1024 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1025
1026 /* Init Flag & Xtal_check Result */
1027 if (priv->imr_done)
1028 val = 1 | priv->xtal_cap_sel << 1;
1029 else
1030 val = 0;
1031 rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
1032 if (rc < 0)
1033 return rc;
1034
1035 /* version */
1036 rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1037 if (rc < 0)
1038 return rc;
1039
1040 /* for LT Gain test */
1041 if (type != V4L2_TUNER_ANALOG_TV) {
1042 rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1043 if (rc < 0)
1044 return rc;
1045 usleep_range(1000, 2000);
1046 }
1047 priv->int_freq = if_khz * 1000;
1048
1049 /* Check if standard changed. If so, filter calibration is needed */
1050 if (type != priv->type)
1051 need_calibration = true;
1052 else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1053 need_calibration = true;
1054 else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1055 ((delsys != priv->delsys) || bw != priv->bw))
1056 need_calibration = true;
1057 else
1058 need_calibration = false;
1059
1060 if (need_calibration) {
1061 tuner_dbg("calibrating the tuner\n");
1062 for (i = 0; i < 2; i++) {
1063 /* Set filt_cap */
1064 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1065 if (rc < 0)
1066 return rc;
1067
1068 /* set cali clk =on */
1069 rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1070 if (rc < 0)
1071 return rc;
1072
1073 /* X'tal cap 0pF for PLL */
1074 rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1075 if (rc < 0)
1076 return rc;
1077
1078 rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
1079 if (rc < 0 || !priv->has_lock)
1080 return rc;
1081
1082 /* Start Trigger */
1083 rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1084 if (rc < 0)
1085 return rc;
1086
1087 usleep_range(1000, 2000);
1088
1089 /* Stop Trigger */
1090 rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1091 if (rc < 0)
1092 return rc;
1093
1094 /* set cali clk =off */
1095 rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1096 if (rc < 0)
1097 return rc;
1098
1099 /* Check if calibration worked */
1100 rc = r820t_read(priv, 0x00, data, sizeof(data));
1101 if (rc < 0)
1102 return rc;
1103
1104 priv->fil_cal_code = data[4] & 0x0f;
1105 if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1106 break;
1107 }
1108 /* narrowest */
1109 if (priv->fil_cal_code == 0x0f)
1110 priv->fil_cal_code = 0;
1111 }
1112
1113 rc = r820t_write_reg_mask(priv, 0x0a,
1114 filt_q | priv->fil_cal_code, 0x1f);
1115 if (rc < 0)
1116 return rc;
1117
1118 /* Set BW, Filter_gain, & HP corner */
1119 rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
1120 if (rc < 0)
1121 return rc;
1122
1123
1124 /* Set Img_R */
1125 rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1126 if (rc < 0)
1127 return rc;
1128
1129 /* Set filt_3dB, V6MHz */
1130 rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1131 if (rc < 0)
1132 return rc;
1133
1134 /* channel filter extension */
1135 rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1136 if (rc < 0)
1137 return rc;
1138
1139 /* Loop through */
1140 rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1141 if (rc < 0)
1142 return rc;
1143
1144 /* Loop through attenuation */
1145 rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1146 if (rc < 0)
1147 return rc;
1148
1149 /* filter extension widest */
1150 rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1151 if (rc < 0)
1152 return rc;
1153
1154 /* RF poly filter current */
1155 rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1156 if (rc < 0)
1157 return rc;
1158
1159 /* Store current standard. If it changes, re-calibrate the tuner */
1160 priv->delsys = delsys;
1161 priv->type = type;
1162 priv->std = std;
1163 priv->bw = bw;
1164
1165 return 0;
1166 }
1167
1168 static int r820t_read_gain(struct r820t_priv *priv)
1169 {
1170 u8 data[4];
1171 int rc;
1172
1173 rc = r820t_read(priv, 0x00, data, sizeof(data));
1174 if (rc < 0)
1175 return rc;
1176
1177 return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4);
1178 }
1179
1180 #if 0
1181 /* FIXME: This routine requires more testing */
1182 static int r820t_set_gain_mode(struct r820t_priv *priv,
1183 bool set_manual_gain,
1184 int gain)
1185 {
1186 int rc;
1187
1188 if (set_manual_gain) {
1189 int i, total_gain = 0;
1190 uint8_t mix_index = 0, lna_index = 0;
1191 u8 data[4];
1192
1193 /* LNA auto off */
1194 rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1195 if (rc < 0)
1196 return rc;
1197
1198 /* Mixer auto off */
1199 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1200 if (rc < 0)
1201 return rc;
1202
1203 rc = r820t_read(priv, 0x00, data, sizeof(data));
1204 if (rc < 0)
1205 return rc;
1206
1207 /* set fixed VGA gain for now (16.3 dB) */
1208 rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1209 if (rc < 0)
1210 return rc;
1211
1212 for (i = 0; i < 15; i++) {
1213 if (total_gain >= gain)
1214 break;
1215
1216 total_gain += r820t_lna_gain_steps[++lna_index];
1217
1218 if (total_gain >= gain)
1219 break;
1220
1221 total_gain += r820t_mixer_gain_steps[++mix_index];
1222 }
1223
1224 /* set LNA gain */
1225 rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1226 if (rc < 0)
1227 return rc;
1228
1229 /* set Mixer gain */
1230 rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1231 if (rc < 0)
1232 return rc;
1233 } else {
1234 /* LNA */
1235 rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10);
1236 if (rc < 0)
1237 return rc;
1238
1239 /* Mixer */
1240 rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10);
1241 if (rc < 0)
1242 return rc;
1243
1244 /* set fixed VGA gain for now (26.5 dB) */
1245 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1246 if (rc < 0)
1247 return rc;
1248 }
1249
1250 return 0;
1251 }
1252 #endif
1253
1254 static int generic_set_freq(struct dvb_frontend *fe,
1255 u32 freq /* in HZ */,
1256 unsigned bw,
1257 enum v4l2_tuner_type type,
1258 v4l2_std_id std, u32 delsys)
1259 {
1260 struct r820t_priv *priv = fe->tuner_priv;
1261 int rc = -EINVAL;
1262 u32 lo_freq;
1263
1264 tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1265 freq / 1000, bw);
1266
1267 rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1268 if (rc < 0)
1269 goto err;
1270
1271 if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1272 lo_freq = freq - priv->int_freq;
1273 else
1274 lo_freq = freq + priv->int_freq;
1275
1276 rc = r820t_set_mux(priv, lo_freq);
1277 if (rc < 0)
1278 goto err;
1279
1280 rc = r820t_set_pll(priv, type, lo_freq);
1281 if (rc < 0 || !priv->has_lock)
1282 goto err;
1283
1284 rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1285 if (rc < 0)
1286 goto err;
1287
1288 tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1289 __func__, freq, r820t_read_gain(priv));
1290
1291 err:
1292
1293 if (rc < 0)
1294 tuner_dbg("%s: failed=%d\n", __func__, rc);
1295 return rc;
1296 }
1297
1298 /*
1299 * r820t standby logic
1300 */
1301
1302 static int r820t_standby(struct r820t_priv *priv)
1303 {
1304 int rc;
1305
1306 /* If device was not initialized yet, don't need to standby */
1307 if (!priv->init_done)
1308 return 0;
1309
1310 rc = r820t_write_reg(priv, 0x06, 0xb1);
1311 if (rc < 0)
1312 return rc;
1313 rc = r820t_write_reg(priv, 0x05, 0x03);
1314 if (rc < 0)
1315 return rc;
1316 rc = r820t_write_reg(priv, 0x07, 0x3a);
1317 if (rc < 0)
1318 return rc;
1319 rc = r820t_write_reg(priv, 0x08, 0x40);
1320 if (rc < 0)
1321 return rc;
1322 rc = r820t_write_reg(priv, 0x09, 0xc0);
1323 if (rc < 0)
1324 return rc;
1325 rc = r820t_write_reg(priv, 0x0a, 0x36);
1326 if (rc < 0)
1327 return rc;
1328 rc = r820t_write_reg(priv, 0x0c, 0x35);
1329 if (rc < 0)
1330 return rc;
1331 rc = r820t_write_reg(priv, 0x0f, 0x68);
1332 if (rc < 0)
1333 return rc;
1334 rc = r820t_write_reg(priv, 0x11, 0x03);
1335 if (rc < 0)
1336 return rc;
1337 rc = r820t_write_reg(priv, 0x17, 0xf4);
1338 if (rc < 0)
1339 return rc;
1340 rc = r820t_write_reg(priv, 0x19, 0x0c);
1341
1342 /* Force initial calibration */
1343 priv->type = -1;
1344
1345 return rc;
1346 }
1347
1348 /*
1349 * r820t device init logic
1350 */
1351
1352 static int r820t_xtal_check(struct r820t_priv *priv)
1353 {
1354 int rc, i;
1355 u8 data[3], val;
1356
1357 /* Initialize the shadow registers */
1358 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1359
1360 /* cap 30pF & Drive Low */
1361 rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1362 if (rc < 0)
1363 return rc;
1364
1365 /* set pll autotune = 128kHz */
1366 rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1367 if (rc < 0)
1368 return rc;
1369
1370 /* set manual initial reg = 111111; */
1371 rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1372 if (rc < 0)
1373 return rc;
1374
1375 /* set auto */
1376 rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1377 if (rc < 0)
1378 return rc;
1379
1380 /* Try several xtal capacitor alternatives */
1381 for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1382 rc = r820t_write_reg_mask(priv, 0x10,
1383 r820t_xtal_capacitor[i][0], 0x1b);
1384 if (rc < 0)
1385 return rc;
1386
1387 usleep_range(5000, 6000);
1388
1389 rc = r820t_read(priv, 0x00, data, sizeof(data));
1390 if (rc < 0)
1391 return rc;
1392 if (!(data[2] & 0x40))
1393 continue;
1394
1395 val = data[2] & 0x3f;
1396
1397 if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1398 break;
1399
1400 if (val != 0x3f)
1401 break;
1402 }
1403
1404 if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1405 return -EINVAL;
1406
1407 return r820t_xtal_capacitor[i][1];
1408 }
1409
1410 static int r820t_imr_prepare(struct r820t_priv *priv)
1411 {
1412 int rc;
1413
1414 /* Initialize the shadow registers */
1415 memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1416
1417 /* lna off (air-in off) */
1418 rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
1419 if (rc < 0)
1420 return rc;
1421
1422 /* mixer gain mode = manual */
1423 rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1424 if (rc < 0)
1425 return rc;
1426
1427 /* filter corner = lowest */
1428 rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
1429 if (rc < 0)
1430 return rc;
1431
1432 /* filter bw=+2cap, hp=5M */
1433 rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
1434 if (rc < 0)
1435 return rc;
1436
1437 /* adc=on, vga code mode, gain = 26.5dB */
1438 rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1439 if (rc < 0)
1440 return rc;
1441
1442 /* ring clk = on */
1443 rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
1444 if (rc < 0)
1445 return rc;
1446
1447 /* ring power = on */
1448 rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
1449 if (rc < 0)
1450 return rc;
1451
1452 /* from ring = ring pll in */
1453 rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
1454 if (rc < 0)
1455 return rc;
1456
1457 /* sw_pdect = det3 */
1458 rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
1459 if (rc < 0)
1460 return rc;
1461
1462 /* Set filt_3dB */
1463 rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
1464
1465 return rc;
1466 }
1467
1468 static int r820t_multi_read(struct r820t_priv *priv)
1469 {
1470 int rc, i;
1471 u16 sum = 0;
1472 u8 data[2], min = 255, max = 0;
1473
1474 usleep_range(5000, 6000);
1475
1476 for (i = 0; i < 6; i++) {
1477 rc = r820t_read(priv, 0x00, data, sizeof(data));
1478 if (rc < 0)
1479 return rc;
1480
1481 sum += data[1];
1482
1483 if (data[1] < min)
1484 min = data[1];
1485
1486 if (data[1] > max)
1487 max = data[1];
1488 }
1489 rc = sum - max - min;
1490
1491 return rc;
1492 }
1493
1494 static int r820t_imr_cross(struct r820t_priv *priv,
1495 struct r820t_sect_type iq_point[3],
1496 u8 *x_direct)
1497 {
1498 struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1499 struct r820t_sect_type tmp;
1500 int i, rc;
1501 u8 reg08, reg09;
1502
1503 reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
1504 reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
1505
1506 tmp.gain_x = 0;
1507 tmp.phase_y = 0;
1508 tmp.value = 255;
1509
1510 for (i = 0; i < 5; i++) {
1511 switch (i) {
1512 case 0:
1513 cross[i].gain_x = reg08;
1514 cross[i].phase_y = reg09;
1515 break;
1516 case 1:
1517 cross[i].gain_x = reg08; /* 0 */
1518 cross[i].phase_y = reg09 + 1; /* Q-1 */
1519 break;
1520 case 2:
1521 cross[i].gain_x = reg08; /* 0 */
1522 cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */
1523 break;
1524 case 3:
1525 cross[i].gain_x = reg08 + 1; /* Q-1 */
1526 cross[i].phase_y = reg09;
1527 break;
1528 default:
1529 cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */
1530 cross[i].phase_y = reg09;
1531 }
1532
1533 rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
1534 if (rc < 0)
1535 return rc;
1536
1537 rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
1538 if (rc < 0)
1539 return rc;
1540
1541 rc = r820t_multi_read(priv);
1542 if (rc < 0)
1543 return rc;
1544
1545 cross[i].value = rc;
1546
1547 if (cross[i].value < tmp.value)
1548 memcpy(&tmp, &cross[i], sizeof(tmp));
1549 }
1550
1551 if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */
1552 *x_direct = 0;
1553
1554 iq_point[0] = cross[0];
1555 iq_point[1] = cross[1];
1556 iq_point[2] = cross[2];
1557 } else { /* (0,0) or x-direction */
1558 *x_direct = 1;
1559
1560 iq_point[0] = cross[0];
1561 iq_point[1] = cross[3];
1562 iq_point[2] = cross[4];
1563 }
1564 return 0;
1565 }
1566
1567 static void r820t_compre_cor(struct r820t_sect_type iq[3])
1568 {
1569 int i;
1570
1571 for (i = 3; i > 0; i--) {
1572 if (iq[0].value > iq[i - 1].value)
1573 swap(iq[0], iq[i - 1]);
1574 }
1575 }
1576
1577 static int r820t_compre_step(struct r820t_priv *priv,
1578 struct r820t_sect_type iq[3], u8 reg)
1579 {
1580 int rc;
1581 struct r820t_sect_type tmp;
1582
1583 /*
1584 * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1585 * with min value:
1586 * new < min => update to min and continue
1587 * new > min => Exit
1588 */
1589
1590 /* min value already saved in iq[0] */
1591 tmp.phase_y = iq[0].phase_y;
1592 tmp.gain_x = iq[0].gain_x;
1593
1594 while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
1595 ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
1596 if (reg == 0x08)
1597 tmp.gain_x++;
1598 else
1599 tmp.phase_y++;
1600
1601 rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
1602 if (rc < 0)
1603 return rc;
1604
1605 rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
1606 if (rc < 0)
1607 return rc;
1608
1609 rc = r820t_multi_read(priv);
1610 if (rc < 0)
1611 return rc;
1612 tmp.value = rc;
1613
1614 if (tmp.value <= iq[0].value) {
1615 iq[0].gain_x = tmp.gain_x;
1616 iq[0].phase_y = tmp.phase_y;
1617 iq[0].value = tmp.value;
1618 } else {
1619 return 0;
1620 }
1621
1622 }
1623
1624 return 0;
1625 }
1626
1627 static int r820t_iq_tree(struct r820t_priv *priv,
1628 struct r820t_sect_type iq[3],
1629 u8 fix_val, u8 var_val, u8 fix_reg)
1630 {
1631 int rc, i;
1632 u8 tmp, var_reg;
1633
1634 /*
1635 * record IMC results by input gain/phase location then adjust
1636 * gain or phase positive 1 step and negtive 1 step,
1637 * both record results
1638 */
1639
1640 if (fix_reg == 0x08)
1641 var_reg = 0x09;
1642 else
1643 var_reg = 0x08;
1644
1645 for (i = 0; i < 3; i++) {
1646 rc = r820t_write_reg(priv, fix_reg, fix_val);
1647 if (rc < 0)
1648 return rc;
1649
1650 rc = r820t_write_reg(priv, var_reg, var_val);
1651 if (rc < 0)
1652 return rc;
1653
1654 rc = r820t_multi_read(priv);
1655 if (rc < 0)
1656 return rc;
1657 iq[i].value = rc;
1658
1659 if (fix_reg == 0x08) {
1660 iq[i].gain_x = fix_val;
1661 iq[i].phase_y = var_val;
1662 } else {
1663 iq[i].phase_y = fix_val;
1664 iq[i].gain_x = var_val;
1665 }
1666
1667 if (i == 0) { /* try right-side point */
1668 var_val++;
1669 } else if (i == 1) { /* try left-side point */
1670 /* if absolute location is 1, change I/Q direction */
1671 if ((var_val & 0x1f) < 0x02) {
1672 tmp = 2 - (var_val & 0x1f);
1673
1674 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1675 if (var_val & 0x20) {
1676 var_val &= 0xc0;
1677 var_val |= tmp;
1678 } else {
1679 var_val |= 0x20 | tmp;
1680 }
1681 } else {
1682 var_val -= 2;
1683 }
1684 }
1685 }
1686
1687 return 0;
1688 }
1689
1690 static int r820t_section(struct r820t_priv *priv,
1691 struct r820t_sect_type *iq_point)
1692 {
1693 int rc;
1694 struct r820t_sect_type compare_iq[3], compare_bet[3];
1695
1696 /* Try X-1 column and save min result to compare_bet[0] */
1697 if (!(iq_point->gain_x & 0x1f))
1698 compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */
1699 else
1700 compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */
1701 compare_iq[0].phase_y = iq_point->phase_y;
1702
1703 /* y-direction */
1704 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1705 compare_iq[0].phase_y, 0x08);
1706 if (rc < 0)
1707 return rc;
1708
1709 r820t_compre_cor(compare_iq);
1710
1711 compare_bet[0] = compare_iq[0];
1712
1713 /* Try X column and save min result to compare_bet[1] */
1714 compare_iq[0].gain_x = iq_point->gain_x;
1715 compare_iq[0].phase_y = iq_point->phase_y;
1716
1717 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1718 compare_iq[0].phase_y, 0x08);
1719 if (rc < 0)
1720 return rc;
1721
1722 r820t_compre_cor(compare_iq);
1723
1724 compare_bet[1] = compare_iq[0];
1725
1726 /* Try X+1 column and save min result to compare_bet[2] */
1727 if ((iq_point->gain_x & 0x1f) == 0x00)
1728 compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */
1729 else
1730 compare_iq[0].gain_x = iq_point->gain_x + 1;
1731 compare_iq[0].phase_y = iq_point->phase_y;
1732
1733 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1734 compare_iq[0].phase_y, 0x08);
1735 if (rc < 0)
1736 return rc;
1737
1738 r820t_compre_cor(compare_iq);
1739
1740 compare_bet[2] = compare_iq[0];
1741
1742 r820t_compre_cor(compare_bet);
1743
1744 *iq_point = compare_bet[0];
1745
1746 return 0;
1747 }
1748
1749 static int r820t_vga_adjust(struct r820t_priv *priv)
1750 {
1751 int rc;
1752 u8 vga_count;
1753
1754 /* increase vga power to let image significant */
1755 for (vga_count = 12; vga_count < 16; vga_count++) {
1756 rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
1757 if (rc < 0)
1758 return rc;
1759
1760 usleep_range(10000, 11000);
1761
1762 rc = r820t_multi_read(priv);
1763 if (rc < 0)
1764 return rc;
1765
1766 if (rc > 40 * 4)
1767 break;
1768 }
1769
1770 return 0;
1771 }
1772
1773 static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1774 {
1775 struct r820t_sect_type compare_iq[3];
1776 int rc;
1777 u8 x_direction = 0; /* 1:x, 0:y */
1778 u8 dir_reg, other_reg;
1779
1780 r820t_vga_adjust(priv);
1781
1782 rc = r820t_imr_cross(priv, compare_iq, &x_direction);
1783 if (rc < 0)
1784 return rc;
1785
1786 if (x_direction == 1) {
1787 dir_reg = 0x08;
1788 other_reg = 0x09;
1789 } else {
1790 dir_reg = 0x09;
1791 other_reg = 0x08;
1792 }
1793
1794 /* compare and find min of 3 points. determine i/q direction */
1795 r820t_compre_cor(compare_iq);
1796
1797 /* increase step to find min value of this direction */
1798 rc = r820t_compre_step(priv, compare_iq, dir_reg);
1799 if (rc < 0)
1800 return rc;
1801
1802 /* the other direction */
1803 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1804 compare_iq[0].phase_y, dir_reg);
1805 if (rc < 0)
1806 return rc;
1807
1808 /* compare and find min of 3 points. determine i/q direction */
1809 r820t_compre_cor(compare_iq);
1810
1811 /* increase step to find min value on this direction */
1812 rc = r820t_compre_step(priv, compare_iq, other_reg);
1813 if (rc < 0)
1814 return rc;
1815
1816 /* check 3 points again */
1817 rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
1818 compare_iq[0].phase_y, other_reg);
1819 if (rc < 0)
1820 return rc;
1821
1822 r820t_compre_cor(compare_iq);
1823
1824 /* section-9 check */
1825 rc = r820t_section(priv, compare_iq);
1826
1827 *iq_pont = compare_iq[0];
1828
1829 /* reset gain/phase control setting */
1830 rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
1831 if (rc < 0)
1832 return rc;
1833
1834 rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
1835
1836 return rc;
1837 }
1838
1839 static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1840 {
1841 int rc;
1842
1843 r820t_vga_adjust(priv);
1844
1845 /*
1846 * search surrounding points from previous point
1847 * try (x-1), (x), (x+1) columns, and find min IMR result point
1848 */
1849 rc = r820t_section(priv, iq_pont);
1850 if (rc < 0)
1851 return rc;
1852
1853 return 0;
1854 }
1855
1856 static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
1857 {
1858 struct r820t_sect_type imr_point;
1859 int rc;
1860 u32 ring_vco, ring_freq, ring_ref;
1861 u8 n_ring, n;
1862 int reg18, reg19, reg1f;
1863
1864 if (priv->cfg->xtal > 24000000)
1865 ring_ref = priv->cfg->xtal / 2000;
1866 else
1867 ring_ref = priv->cfg->xtal / 1000;
1868
1869 n_ring = 15;
1870 for (n = 0; n < 16; n++) {
1871 if ((16 + n) * 8 * ring_ref >= 3100000) {
1872 n_ring = n;
1873 break;
1874 }
1875 }
1876
1877 reg18 = r820t_read_cache_reg(priv, 0x18);
1878 reg19 = r820t_read_cache_reg(priv, 0x19);
1879 reg1f = r820t_read_cache_reg(priv, 0x1f);
1880
1881 reg18 &= 0xf0; /* set ring[3:0] */
1882 reg18 |= n_ring;
1883
1884 ring_vco = (16 + n_ring) * 8 * ring_ref;
1885
1886 reg18 &= 0xdf; /* clear ring_se23 */
1887 reg19 &= 0xfc; /* clear ring_seldiv */
1888 reg1f &= 0xfc; /* clear ring_att */
1889
1890 switch (imr_mem) {
1891 case 0:
1892 ring_freq = ring_vco / 48;
1893 reg18 |= 0x20; /* ring_se23 = 1 */
1894 reg19 |= 0x03; /* ring_seldiv = 3 */
1895 reg1f |= 0x02; /* ring_att 10 */
1896 break;
1897 case 1:
1898 ring_freq = ring_vco / 16;
1899 reg18 |= 0x00; /* ring_se23 = 0 */
1900 reg19 |= 0x02; /* ring_seldiv = 2 */
1901 reg1f |= 0x00; /* pw_ring 00 */
1902 break;
1903 case 2:
1904 ring_freq = ring_vco / 8;
1905 reg18 |= 0x00; /* ring_se23 = 0 */
1906 reg19 |= 0x01; /* ring_seldiv = 1 */
1907 reg1f |= 0x03; /* pw_ring 11 */
1908 break;
1909 case 3:
1910 ring_freq = ring_vco / 6;
1911 reg18 |= 0x20; /* ring_se23 = 1 */
1912 reg19 |= 0x00; /* ring_seldiv = 0 */
1913 reg1f |= 0x03; /* pw_ring 11 */
1914 break;
1915 case 4:
1916 ring_freq = ring_vco / 4;
1917 reg18 |= 0x00; /* ring_se23 = 0 */
1918 reg19 |= 0x00; /* ring_seldiv = 0 */
1919 reg1f |= 0x01; /* pw_ring 01 */
1920 break;
1921 default:
1922 ring_freq = ring_vco / 4;
1923 reg18 |= 0x00; /* ring_se23 = 0 */
1924 reg19 |= 0x00; /* ring_seldiv = 0 */
1925 reg1f |= 0x01; /* pw_ring 01 */
1926 break;
1927 }
1928
1929
1930 /* write pw_ring, n_ring, ringdiv2 registers */
1931
1932 /* n_ring, ring_se23 */
1933 rc = r820t_write_reg(priv, 0x18, reg18);
1934 if (rc < 0)
1935 return rc;
1936
1937 /* ring_sediv */
1938 rc = r820t_write_reg(priv, 0x19, reg19);
1939 if (rc < 0)
1940 return rc;
1941
1942 /* pw_ring */
1943 rc = r820t_write_reg(priv, 0x1f, reg1f);
1944 if (rc < 0)
1945 return rc;
1946
1947 /* mux input freq ~ rf_in freq */
1948 rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
1949 if (rc < 0)
1950 return rc;
1951
1952 rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
1953 (ring_freq - 5300) * 1000);
1954 if (!priv->has_lock)
1955 rc = -EINVAL;
1956 if (rc < 0)
1957 return rc;
1958
1959 if (im_flag) {
1960 rc = r820t_iq(priv, &imr_point);
1961 } else {
1962 imr_point.gain_x = priv->imr_data[3].gain_x;
1963 imr_point.phase_y = priv->imr_data[3].phase_y;
1964 imr_point.value = priv->imr_data[3].value;
1965
1966 rc = r820t_f_imr(priv, &imr_point);
1967 }
1968 if (rc < 0)
1969 return rc;
1970
1971 /* save IMR value */
1972 switch (imr_mem) {
1973 case 0:
1974 priv->imr_data[0].gain_x = imr_point.gain_x;
1975 priv->imr_data[0].phase_y = imr_point.phase_y;
1976 priv->imr_data[0].value = imr_point.value;
1977 break;
1978 case 1:
1979 priv->imr_data[1].gain_x = imr_point.gain_x;
1980 priv->imr_data[1].phase_y = imr_point.phase_y;
1981 priv->imr_data[1].value = imr_point.value;
1982 break;
1983 case 2:
1984 priv->imr_data[2].gain_x = imr_point.gain_x;
1985 priv->imr_data[2].phase_y = imr_point.phase_y;
1986 priv->imr_data[2].value = imr_point.value;
1987 break;
1988 case 3:
1989 priv->imr_data[3].gain_x = imr_point.gain_x;
1990 priv->imr_data[3].phase_y = imr_point.phase_y;
1991 priv->imr_data[3].value = imr_point.value;
1992 break;
1993 case 4:
1994 priv->imr_data[4].gain_x = imr_point.gain_x;
1995 priv->imr_data[4].phase_y = imr_point.phase_y;
1996 priv->imr_data[4].value = imr_point.value;
1997 break;
1998 default:
1999 priv->imr_data[4].gain_x = imr_point.gain_x;
2000 priv->imr_data[4].phase_y = imr_point.phase_y;
2001 priv->imr_data[4].value = imr_point.value;
2002 break;
2003 }
2004
2005 return 0;
2006 }
2007
2008 static int r820t_imr_callibrate(struct r820t_priv *priv)
2009 {
2010 int rc, i;
2011 int xtal_cap = 0;
2012
2013 if (priv->init_done)
2014 return 0;
2015
2016 /* Detect Xtal capacitance */
2017 if ((priv->cfg->rafael_chip == CHIP_R820T) ||
2018 (priv->cfg->rafael_chip == CHIP_R828S) ||
2019 (priv->cfg->rafael_chip == CHIP_R820C)) {
2020 priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
2021 } else {
2022 /* Initialize registers */
2023 rc = r820t_write(priv, 0x05,
2024 r820t_init_array, sizeof(r820t_init_array));
2025 if (rc < 0)
2026 return rc;
2027 for (i = 0; i < 3; i++) {
2028 rc = r820t_xtal_check(priv);
2029 if (rc < 0)
2030 return rc;
2031 if (!i || rc > xtal_cap)
2032 xtal_cap = rc;
2033 }
2034 priv->xtal_cap_sel = xtal_cap;
2035 }
2036
2037 /*
2038 * Disables IMR callibration. That emulates the same behaviour
2039 * as what is done by rtl-sdr userspace library. Useful for testing
2040 */
2041 if (no_imr_cal) {
2042 priv->init_done = true;
2043
2044 return 0;
2045 }
2046
2047 /* Initialize registers */
2048 rc = r820t_write(priv, 0x05,
2049 r820t_init_array, sizeof(r820t_init_array));
2050 if (rc < 0)
2051 return rc;
2052
2053 rc = r820t_imr_prepare(priv);
2054 if (rc < 0)
2055 return rc;
2056
2057 rc = r820t_imr(priv, 3, true);
2058 if (rc < 0)
2059 return rc;
2060 rc = r820t_imr(priv, 1, false);
2061 if (rc < 0)
2062 return rc;
2063 rc = r820t_imr(priv, 0, false);
2064 if (rc < 0)
2065 return rc;
2066 rc = r820t_imr(priv, 2, false);
2067 if (rc < 0)
2068 return rc;
2069 rc = r820t_imr(priv, 4, false);
2070 if (rc < 0)
2071 return rc;
2072
2073 priv->init_done = true;
2074 priv->imr_done = true;
2075
2076 return 0;
2077 }
2078
2079 #if 0
2080 /* Not used, for now */
2081 static int r820t_gpio(struct r820t_priv *priv, bool enable)
2082 {
2083 return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
2084 }
2085 #endif
2086
2087 /*
2088 * r820t frontend operations and tuner attach code
2089 *
2090 * All driver locks and i2c control are only in this part of the code
2091 */
2092
2093 static int r820t_init(struct dvb_frontend *fe)
2094 {
2095 struct r820t_priv *priv = fe->tuner_priv;
2096 int rc;
2097
2098 tuner_dbg("%s:\n", __func__);
2099
2100 mutex_lock(&priv->lock);
2101 if (fe->ops.i2c_gate_ctrl)
2102 fe->ops.i2c_gate_ctrl(fe, 1);
2103
2104 rc = r820t_imr_callibrate(priv);
2105 if (rc < 0)
2106 goto err;
2107
2108 /* Initialize registers */
2109 rc = r820t_write(priv, 0x05,
2110 r820t_init_array, sizeof(r820t_init_array));
2111
2112 err:
2113 if (fe->ops.i2c_gate_ctrl)
2114 fe->ops.i2c_gate_ctrl(fe, 0);
2115 mutex_unlock(&priv->lock);
2116
2117 if (rc < 0)
2118 tuner_dbg("%s: failed=%d\n", __func__, rc);
2119 return rc;
2120 }
2121
2122 static int r820t_sleep(struct dvb_frontend *fe)
2123 {
2124 struct r820t_priv *priv = fe->tuner_priv;
2125 int rc;
2126
2127 tuner_dbg("%s:\n", __func__);
2128
2129 mutex_lock(&priv->lock);
2130 if (fe->ops.i2c_gate_ctrl)
2131 fe->ops.i2c_gate_ctrl(fe, 1);
2132
2133 rc = r820t_standby(priv);
2134
2135 if (fe->ops.i2c_gate_ctrl)
2136 fe->ops.i2c_gate_ctrl(fe, 0);
2137 mutex_unlock(&priv->lock);
2138
2139 tuner_dbg("%s: failed=%d\n", __func__, rc);
2140 return rc;
2141 }
2142
2143 static int r820t_set_analog_freq(struct dvb_frontend *fe,
2144 struct analog_parameters *p)
2145 {
2146 struct r820t_priv *priv = fe->tuner_priv;
2147 unsigned bw;
2148 int rc;
2149
2150 tuner_dbg("%s called\n", __func__);
2151
2152 /* if std is not defined, choose one */
2153 if (!p->std)
2154 p->std = V4L2_STD_MN;
2155
2156 if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
2157 bw = 6;
2158 else
2159 bw = 8;
2160
2161 mutex_lock(&priv->lock);
2162 if (fe->ops.i2c_gate_ctrl)
2163 fe->ops.i2c_gate_ctrl(fe, 1);
2164
2165 rc = generic_set_freq(fe, 62500l * p->frequency, bw,
2166 V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
2167
2168 if (fe->ops.i2c_gate_ctrl)
2169 fe->ops.i2c_gate_ctrl(fe, 0);
2170 mutex_unlock(&priv->lock);
2171
2172 return rc;
2173 }
2174
2175 static int r820t_set_params(struct dvb_frontend *fe)
2176 {
2177 struct r820t_priv *priv = fe->tuner_priv;
2178 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2179 int rc;
2180 unsigned bw;
2181
2182 tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2183 __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
2184
2185 mutex_lock(&priv->lock);
2186 if (fe->ops.i2c_gate_ctrl)
2187 fe->ops.i2c_gate_ctrl(fe, 1);
2188
2189 bw = (c->bandwidth_hz + 500000) / 1000000;
2190 if (!bw)
2191 bw = 8;
2192
2193 rc = generic_set_freq(fe, c->frequency, bw,
2194 V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
2195
2196 if (fe->ops.i2c_gate_ctrl)
2197 fe->ops.i2c_gate_ctrl(fe, 0);
2198 mutex_unlock(&priv->lock);
2199
2200 if (rc)
2201 tuner_dbg("%s: failed=%d\n", __func__, rc);
2202 return rc;
2203 }
2204
2205 static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
2206 {
2207 struct r820t_priv *priv = fe->tuner_priv;
2208 int rc = 0;
2209
2210 mutex_lock(&priv->lock);
2211 if (fe->ops.i2c_gate_ctrl)
2212 fe->ops.i2c_gate_ctrl(fe, 1);
2213
2214 if (priv->has_lock) {
2215 rc = r820t_read_gain(priv);
2216 if (rc < 0)
2217 goto err;
2218
2219 /* A higher gain at LNA means a lower signal strength */
2220 *strength = (45 - rc) << 4 | 0xff;
2221 if (*strength == 0xff)
2222 *strength = 0;
2223 } else {
2224 *strength = 0;
2225 }
2226
2227 err:
2228 if (fe->ops.i2c_gate_ctrl)
2229 fe->ops.i2c_gate_ctrl(fe, 0);
2230 mutex_unlock(&priv->lock);
2231
2232 tuner_dbg("%s: %s, gain=%d strength=%d\n",
2233 __func__,
2234 priv->has_lock ? "PLL locked" : "no signal",
2235 rc, *strength);
2236
2237 return 0;
2238 }
2239
2240 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
2241 {
2242 struct r820t_priv *priv = fe->tuner_priv;
2243
2244 tuner_dbg("%s:\n", __func__);
2245
2246 *frequency = priv->int_freq;
2247
2248 return 0;
2249 }
2250
2251 static int r820t_release(struct dvb_frontend *fe)
2252 {
2253 struct r820t_priv *priv = fe->tuner_priv;
2254
2255 tuner_dbg("%s:\n", __func__);
2256
2257 mutex_lock(&r820t_list_mutex);
2258
2259 if (priv)
2260 hybrid_tuner_release_state(priv);
2261
2262 mutex_unlock(&r820t_list_mutex);
2263
2264 fe->tuner_priv = NULL;
2265
2266 return 0;
2267 }
2268
2269 static const struct dvb_tuner_ops r820t_tuner_ops = {
2270 .info = {
2271 .name = "Rafael Micro R820T",
2272 .frequency_min = 42000000,
2273 .frequency_max = 1002000000,
2274 },
2275 .init = r820t_init,
2276 .release = r820t_release,
2277 .sleep = r820t_sleep,
2278 .set_params = r820t_set_params,
2279 .set_analog_params = r820t_set_analog_freq,
2280 .get_if_frequency = r820t_get_if_frequency,
2281 .get_rf_strength = r820t_signal,
2282 };
2283
2284 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
2285 struct i2c_adapter *i2c,
2286 const struct r820t_config *cfg)
2287 {
2288 struct r820t_priv *priv;
2289 int rc = -ENODEV;
2290 u8 data[5];
2291 int instance;
2292
2293 mutex_lock(&r820t_list_mutex);
2294
2295 instance = hybrid_tuner_request_state(struct r820t_priv, priv,
2296 hybrid_tuner_instance_list,
2297 i2c, cfg->i2c_addr,
2298 "r820t");
2299 switch (instance) {
2300 case 0:
2301 /* memory allocation failure */
2302 goto err_no_gate;
2303 break;
2304 case 1:
2305 /* new tuner instance */
2306 priv->cfg = cfg;
2307
2308 mutex_init(&priv->lock);
2309
2310 fe->tuner_priv = priv;
2311 break;
2312 case 2:
2313 /* existing tuner instance */
2314 fe->tuner_priv = priv;
2315 break;
2316 }
2317
2318 if (fe->ops.i2c_gate_ctrl)
2319 fe->ops.i2c_gate_ctrl(fe, 1);
2320
2321 /* check if the tuner is there */
2322 rc = r820t_read(priv, 0x00, data, sizeof(data));
2323 if (rc < 0)
2324 goto err;
2325
2326 rc = r820t_sleep(fe);
2327 if (rc < 0)
2328 goto err;
2329
2330 tuner_info("Rafael Micro r820t successfully identified\n");
2331
2332 if (fe->ops.i2c_gate_ctrl)
2333 fe->ops.i2c_gate_ctrl(fe, 0);
2334
2335 mutex_unlock(&r820t_list_mutex);
2336
2337 memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
2338 sizeof(struct dvb_tuner_ops));
2339
2340 return fe;
2341 err:
2342 if (fe->ops.i2c_gate_ctrl)
2343 fe->ops.i2c_gate_ctrl(fe, 0);
2344
2345 err_no_gate:
2346 mutex_unlock(&r820t_list_mutex);
2347
2348 tuner_info("%s: failed=%d\n", __func__, rc);
2349 r820t_release(fe);
2350 return NULL;
2351 }
2352 EXPORT_SYMBOL_GPL(r820t_attach);
2353
2354 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2355 MODULE_AUTHOR("Mauro Carvalho Chehab");
2356 MODULE_LICENSE("GPL");
Linux with added FPC-III support