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workqueue: Make worker_attach/detach_pool() update worker->pool
[linux/fpc-iii.git] / drivers / scsi / qla2xxx / qla_nx.h
blob71a41093530e35c64e02bed60b8f8990227e4076
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_NX_H
8 #define __QLA_NX_H
9
10 #include <linux/io-64-nonatomic-lo-hi.h>
11
12 /*
13 * Following are the states of the Phantom. Phantom will set them and
14 * Host will read to check if the fields are correct.
15 */
16 #define PHAN_INITIALIZE_FAILED 0xffff
17 #define PHAN_INITIALIZE_COMPLETE 0xff01
18
19 /* Host writes the following to notify that it has done the init-handshake */
20 #define PHAN_INITIALIZE_ACK 0xf00f
21 #define PHAN_PEG_RCV_INITIALIZED 0xff01
22
23 /*CRB_RELATED*/
24 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
25 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
26
27 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
28 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
29 #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54)
30 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
31 #define CRB_TEMP_STATE QLA82XX_REG(0x1b4)
32 #define QLA82XX_DMA_SHIFT_VALUE 0x55555555
33
34 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
35 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
36 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
37 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
38 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
39 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
40 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
41
42 /* Hub 0 */
43 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
44 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
45
46 /* Hub 1 */
47 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
48 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
49 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
50 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
51 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
52 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
53 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
54 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
55 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
56 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
57 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
58 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
59 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
60 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
61 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
62
63 /* Hub 2 */
64 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
65 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
66 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
67
68 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
69 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
70 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
71 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
72 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
73 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
74 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
75 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
76 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
77 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
78 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
79 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
80 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
81
82 /* Hub 3 */
83 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
84 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
85 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
86 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
87
88 /* Hub 4 */
89 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
90 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
91 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
92 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
93 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
94 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
95 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
96 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
97 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
98 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
99 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
100 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
101
102 /* Hub 5 */
103 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
104 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
105 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
106 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
107 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
108 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
109 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
110
111 /* Hub 6 */
112 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
113 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
114 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
115 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
116 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
117 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
118 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
119 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
120 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
121
122 /* This field defines PCI/X adr [25:20] of agents on the CRB */
123 /* */
124 #define QLA82XX_HW_PX_MAP_CRB_PH 0
125 #define QLA82XX_HW_PX_MAP_CRB_PS 1
126 #define QLA82XX_HW_PX_MAP_CRB_MN 2
127 #define QLA82XX_HW_PX_MAP_CRB_MS 3
128 #define QLA82XX_HW_PX_MAP_CRB_SRE 5
129 #define QLA82XX_HW_PX_MAP_CRB_NIU 6
130 #define QLA82XX_HW_PX_MAP_CRB_QMN 7
131 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
132 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
133 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
134 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
135 #define QLA82XX_HW_PX_MAP_CRB_QMS 12
136 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
137 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
138 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
139 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
140 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
141 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
142 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
143 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
144 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
145 #define QLA82XX_HW_PX_MAP_CRB_PGND 21
146 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
147 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
148 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
149 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
150 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
151 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
152 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
153 #define QLA82XX_HW_PX_MAP_CRB_SN 29
154 #define QLA82XX_HW_PX_MAP_CRB_EG 31
155 #define QLA82XX_HW_PX_MAP_CRB_PH2 32
156 #define QLA82XX_HW_PX_MAP_CRB_PS2 33
157 #define QLA82XX_HW_PX_MAP_CRB_CAM 34
158 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
159 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
160 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
161 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
162 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
163 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
164 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
165 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
166 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
167 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
168 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
169 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
170 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
171 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
172 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
173 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
174 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
175 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
176 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
177 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
178 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
179 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
180 #define QLA82XX_HW_PX_MAP_CRB_SMB 58
181 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
182 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
183 #define QLA82XX_HW_PX_MAP_CRB_LPC 61
184 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
185 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
186 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
187 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
188 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
189
190 /* This field defines CRB adr [31:20] of the agents */
191 /* */
192
193 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
194 QLA82XX_HW_MN_CRB_AGT_ADR)
195 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
196 QLA82XX_HW_PH_CRB_AGT_ADR)
197 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
198 QLA82XX_HW_MS_CRB_AGT_ADR)
199 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
200 QLA82XX_HW_PS_CRB_AGT_ADR)
201 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
202 QLA82XX_HW_SS_CRB_AGT_ADR)
203 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
204 QLA82XX_HW_RPMX3_CRB_AGT_ADR)
205 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
206 QLA82XX_HW_QMS_CRB_AGT_ADR)
207 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
208 QLA82XX_HW_SQGS0_CRB_AGT_ADR)
209 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
210 QLA82XX_HW_SQGS1_CRB_AGT_ADR)
211 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
212 QLA82XX_HW_SQGS2_CRB_AGT_ADR)
213 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
214 QLA82XX_HW_SQGS3_CRB_AGT_ADR)
215 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
216 QLA82XX_HW_C2C0_CRB_AGT_ADR)
217 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
218 QLA82XX_HW_C2C1_CRB_AGT_ADR)
219 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
220 QLA82XX_HW_RPMX2_CRB_AGT_ADR)
221 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
222 QLA82XX_HW_RPMX4_CRB_AGT_ADR)
223 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
224 QLA82XX_HW_RPMX7_CRB_AGT_ADR)
225 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
226 QLA82XX_HW_RPMX9_CRB_AGT_ADR)
227 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
228 QLA82XX_HW_SMB_CRB_AGT_ADR)
229 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
230 QLA82XX_HW_NIU_CRB_AGT_ADR)
231 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
232 QLA82XX_HW_I2C0_CRB_AGT_ADR)
233 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
234 QLA82XX_HW_I2C1_CRB_AGT_ADR)
235 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
236 QLA82XX_HW_SRE_CRB_AGT_ADR)
237 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
238 QLA82XX_HW_EG_CRB_AGT_ADR)
239 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
240 QLA82XX_HW_RPMX0_CRB_AGT_ADR)
241 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
242 QLA82XX_HW_QM_CRB_AGT_ADR)
243 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
244 QLA82XX_HW_SQG0_CRB_AGT_ADR)
245 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
246 QLA82XX_HW_SQG1_CRB_AGT_ADR)
247 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
248 QLA82XX_HW_SQG2_CRB_AGT_ADR)
249 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
250 QLA82XX_HW_SQG3_CRB_AGT_ADR)
251 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
252 QLA82XX_HW_RPMX1_CRB_AGT_ADR)
253 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
254 QLA82XX_HW_RPMX5_CRB_AGT_ADR)
255 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
256 QLA82XX_HW_RPMX6_CRB_AGT_ADR)
257 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
258 QLA82XX_HW_RPMX8_CRB_AGT_ADR)
259 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
260 QLA82XX_HW_CAS0_CRB_AGT_ADR)
261 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
262 QLA82XX_HW_CAS1_CRB_AGT_ADR)
263 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
264 QLA82XX_HW_CAS2_CRB_AGT_ADR)
265 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
266 QLA82XX_HW_CAS3_CRB_AGT_ADR)
267 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
268 QLA82XX_HW_PEGNI_CRB_AGT_ADR)
269 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
270 QLA82XX_HW_PEGND_CRB_AGT_ADR)
271 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
272 QLA82XX_HW_PEGN0_CRB_AGT_ADR)
273 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
274 QLA82XX_HW_PEGN1_CRB_AGT_ADR)
275 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
276 QLA82XX_HW_PEGN2_CRB_AGT_ADR)
277 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
278 QLA82XX_HW_PEGN3_CRB_AGT_ADR)
279 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
280 QLA82XX_HW_PEGN4_CRB_AGT_ADR)
281 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
282 QLA82XX_HW_PEGNC_CRB_AGT_ADR)
283 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
284 QLA82XX_HW_PEGR0_CRB_AGT_ADR)
285 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
286 QLA82XX_HW_PEGR1_CRB_AGT_ADR)
287 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
288 QLA82XX_HW_PEGR2_CRB_AGT_ADR)
289 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
290 QLA82XX_HW_PEGR3_CRB_AGT_ADR)
291 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
292 QLA82XX_HW_PEGSI_CRB_AGT_ADR)
293 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
294 QLA82XX_HW_PEGSD_CRB_AGT_ADR)
295 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
296 QLA82XX_HW_PEGS0_CRB_AGT_ADR)
297 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
298 QLA82XX_HW_PEGS1_CRB_AGT_ADR)
299 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
300 QLA82XX_HW_PEGS2_CRB_AGT_ADR)
301 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
302 QLA82XX_HW_PEGS3_CRB_AGT_ADR)
303 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
304 QLA82XX_HW_PEGSC_CRB_AGT_ADR)
305 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
306 QLA82XX_HW_NCM_CRB_AGT_ADR)
307 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
308 QLA82XX_HW_TMR_CRB_AGT_ADR)
309 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
310 QLA82XX_HW_XDMA_CRB_AGT_ADR)
311 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
312 QLA82XX_HW_SN_CRB_AGT_ADR)
313 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
314 QLA82XX_HW_I2Q_CRB_AGT_ADR)
315 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
316 QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
317 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
318 QLA82XX_HW_OCM0_CRB_AGT_ADR)
319 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
320 QLA82XX_HW_OCM1_CRB_AGT_ADR)
321 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
322 QLA82XX_HW_LPC_CRB_AGT_ADR)
323
324 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
325 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
326 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
327 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
328 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
329 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
330 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
331 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
332 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
333
334 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
335 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
336 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
337
338 #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */
339 #define QLA82XX_PCI_CRB_WINDOW(A) \
340 (QLA82XX_PCI_CRBSPACE + (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
341 #define QLA82XX_CRB_C2C_0 \
342 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
343 #define QLA82XX_CRB_C2C_1 \
344 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
345 #define QLA82XX_CRB_C2C_2 \
346 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
347 #define QLA82XX_CRB_CAM \
348 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
349 #define QLA82XX_CRB_CASPER \
350 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
351 #define QLA82XX_CRB_CASPER_0 \
352 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
353 #define QLA82XX_CRB_CASPER_1 \
354 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
355 #define QLA82XX_CRB_CASPER_2 \
356 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
357 #define QLA82XX_CRB_DDR_MD \
358 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
359 #define QLA82XX_CRB_DDR_NET \
360 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
361 #define QLA82XX_CRB_EPG \
362 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
363 #define QLA82XX_CRB_I2Q \
364 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
365 #define QLA82XX_CRB_NIU \
366 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
367
368 #define QLA82XX_CRB_PCIX_HOST \
369 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
370 #define QLA82XX_CRB_PCIX_HOST2 \
371 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
372 #define QLA82XX_CRB_PCIX_MD \
373 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
374 #define QLA82XX_CRB_PCIE \
375 QLA82XX_CRB_PCIX_MD
376
377 /* window 1 pcie slot */
378 #define QLA82XX_CRB_PCIE2 \
379 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
380 #define QLA82XX_CRB_PEG_MD_0 \
381 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
382 #define QLA82XX_CRB_PEG_MD_1 \
383 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
384 #define QLA82XX_CRB_PEG_MD_2 \
385 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
386 #define QLA82XX_CRB_PEG_MD_3 \
387 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
388 #define QLA82XX_CRB_PEG_MD_3 \
389 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
390 #define QLA82XX_CRB_PEG_MD_D \
391 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
392 #define QLA82XX_CRB_PEG_MD_I \
393 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
394 #define QLA82XX_CRB_PEG_NET_0 \
395 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
396 #define QLA82XX_CRB_PEG_NET_1 \
397 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
398 #define QLA82XX_CRB_PEG_NET_2 \
399 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
400 #define QLA82XX_CRB_PEG_NET_3 \
401 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
402 #define QLA82XX_CRB_PEG_NET_4 \
403 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
404 #define QLA82XX_CRB_PEG_NET_D \
405 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
406 #define QLA82XX_CRB_PEG_NET_I \
407 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
408 #define QLA82XX_CRB_PQM_MD \
409 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
410 #define QLA82XX_CRB_PQM_NET \
411 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
412 #define QLA82XX_CRB_QDR_MD \
413 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
414 #define QLA82XX_CRB_QDR_NET \
415 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
416 #define QLA82XX_CRB_ROMUSB \
417 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
418 #define QLA82XX_CRB_RPMX_0 \
419 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
420 #define QLA82XX_CRB_RPMX_1 \
421 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
422 #define QLA82XX_CRB_RPMX_2 \
423 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
424 #define QLA82XX_CRB_RPMX_3 \
425 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
426 #define QLA82XX_CRB_RPMX_4 \
427 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
428 #define QLA82XX_CRB_RPMX_5 \
429 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
430 #define QLA82XX_CRB_RPMX_6 \
431 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
432 #define QLA82XX_CRB_RPMX_7 \
433 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
434 #define QLA82XX_CRB_SQM_MD_0 \
435 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
436 #define QLA82XX_CRB_SQM_MD_1 \
437 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
438 #define QLA82XX_CRB_SQM_MD_2 \
439 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
440 #define QLA82XX_CRB_SQM_MD_3 \
441 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
442 #define QLA82XX_CRB_SQM_NET_0 \
443 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
444 #define QLA82XX_CRB_SQM_NET_1 \
445 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
446 #define QLA82XX_CRB_SQM_NET_2 \
447 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
448 #define QLA82XX_CRB_SQM_NET_3 \
449 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
450 #define QLA82XX_CRB_SRE \
451 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
452 #define QLA82XX_CRB_TIMER \
453 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
454 #define QLA82XX_CRB_XDMA \
455 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
456 #define QLA82XX_CRB_I2C0 \
457 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
458 #define QLA82XX_CRB_I2C1 \
459 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
460 #define QLA82XX_CRB_OCM0 \
461 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
462 #define QLA82XX_CRB_SMB \
463 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
464 #define QLA82XX_CRB_MAX \
465 QLA82XX_PCI_CRB_WINDOW(64)
466
467 /*
468 * ====================== BASE ADDRESSES ON-CHIP ======================
469 * Base addresses of major components on-chip.
470 * ====================== BASE ADDRESSES ON-CHIP ======================
471 */
472 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
473 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
474
475 /* Imbus address bit used to indicate a host address. This bit is
476 * eliminated by the pcie bar and bar select before presentation
477 * over pcie. */
478 /* host memory via IMBUS */
479 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
480 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
481 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
482 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
483 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
484 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
485 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
486 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
487 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
488
489 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
490 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
491 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
492 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
493 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
494 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
495 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
496
497 /*
498 * Register offsets for MN
499 */
500 #define MIU_CONTROL (0x000)
501 #define MIU_TAG (0x004)
502 #define MIU_TEST_AGT_CTRL (0x090)
503 #define MIU_TEST_AGT_ADDR_LO (0x094)
504 #define MIU_TEST_AGT_ADDR_HI (0x098)
505 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
506 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
507 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
508 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
509 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
510 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
511 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
512 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
513
514 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
515 #define MIU_TA_CTL_START 1
516 #define MIU_TA_CTL_ENABLE 2
517 #define MIU_TA_CTL_WRITE 4
518 #define MIU_TA_CTL_BUSY 8
519
520 /*CAM RAM */
521 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
522 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
523
524 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
525 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
526 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
527 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
528
529 #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8))
530 #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc))
531
532 #define HALT_STATUS_UNRECOVERABLE 0x80000000
533 #define HALT_STATUS_RECOVERABLE 0x40000000
534
535 /* Driver Coexistence Defines */
536 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
537 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
538 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
539 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
540 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
541 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
542
543 /* Every driver should use these Device State */
544 #define QLA8XXX_DEV_COLD 1
545 #define QLA8XXX_DEV_INITIALIZING 2
546 #define QLA8XXX_DEV_READY 3
547 #define QLA8XXX_DEV_NEED_RESET 4
548 #define QLA8XXX_DEV_NEED_QUIESCENT 5
549 #define QLA8XXX_DEV_FAILED 6
550 #define QLA8XXX_DEV_QUIESCENT 7
551 #define MAX_STATES 8 /* Increment if new state added */
552 #define QLA8XXX_BAD_VALUE 0xbad0bad0
553
554 #define QLA82XX_IDC_VERSION 1
555 #define QLA82XX_ROM_DEV_INIT_TIMEOUT 30
556 #define QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT 10
557
558 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
559 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
560 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
561 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
562 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
563 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
564
565 #define PCIE_SETUP_FUNCTION (0x12040)
566 #define PCIE_SETUP_FUNCTION2 (0x12048)
567
568 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
569 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
570
571 #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */
572 #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */
573 #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */
574 #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */
575 #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */
576 #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/
577
578 /* Different drive state */
579 #define QLA82XX_DRVST_NOT_RDY 0
580 #define QLA82XX_DRVST_RST_RDY 1
581 #define QLA82XX_DRVST_QSNT_RDY 2
582
583 /* Different drive active state */
584 #define QLA82XX_DRV_NOT_ACTIVE 0
585 #define QLA82XX_DRV_ACTIVE 1
586
587 /*
588 * The PCI VendorID and DeviceID for our board.
589 */
590 #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021
591 #define PCI_DEVICE_ID_QLOGIC_ISP8044 0x8044
592
593 #define QLA82XX_MSIX_TBL_SPACE 8192
594 #define QLA82XX_PCI_REG_MSIX_TBL 0x44
595 #define QLA82XX_PCI_MSIX_CONTROL 0x40
596
597 struct crb_128M_2M_sub_block_map {
598 unsigned valid;
599 unsigned start_128M;
600 unsigned end_128M;
601 unsigned start_2M;
602 };
603
604 struct crb_128M_2M_block_map {
605 struct crb_128M_2M_sub_block_map sub_block[16];
606 };
607
608 struct crb_addr_pair {
609 long addr;
610 long data;
611 };
612
613 #define ADDR_ERROR ((unsigned long) 0xffffffff)
614 #define MAX_CTL_CHECK 1000
615
616 /***************************************************************************
617 * PCI related defines.
618 **************************************************************************/
619
620 /*
621 * Interrupt related defines.
622 */
623 #define PCIX_TARGET_STATUS (0x10118)
624 #define PCIX_TARGET_STATUS_F1 (0x10160)
625 #define PCIX_TARGET_STATUS_F2 (0x10164)
626 #define PCIX_TARGET_STATUS_F3 (0x10168)
627 #define PCIX_TARGET_STATUS_F4 (0x10360)
628 #define PCIX_TARGET_STATUS_F5 (0x10364)
629 #define PCIX_TARGET_STATUS_F6 (0x10368)
630 #define PCIX_TARGET_STATUS_F7 (0x1036c)
631
632 #define PCIX_TARGET_MASK (0x10128)
633 #define PCIX_TARGET_MASK_F1 (0x10170)
634 #define PCIX_TARGET_MASK_F2 (0x10174)
635 #define PCIX_TARGET_MASK_F3 (0x10178)
636 #define PCIX_TARGET_MASK_F4 (0x10370)
637 #define PCIX_TARGET_MASK_F5 (0x10374)
638 #define PCIX_TARGET_MASK_F6 (0x10378)
639 #define PCIX_TARGET_MASK_F7 (0x1037c)
640
641 /*
642 * Message Signaled Interrupts
643 */
644 #define PCIX_MSI_F0 (0x13000)
645 #define PCIX_MSI_F1 (0x13004)
646 #define PCIX_MSI_F2 (0x13008)
647 #define PCIX_MSI_F3 (0x1300c)
648 #define PCIX_MSI_F4 (0x13010)
649 #define PCIX_MSI_F5 (0x13014)
650 #define PCIX_MSI_F6 (0x13018)
651 #define PCIX_MSI_F7 (0x1301c)
652 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
653 #define PCIX_INT_VECTOR (0x10100)
654 #define PCIX_INT_MASK (0x10104)
655
656 /*
657 * Interrupt state machine and other bits.
658 */
659 #define PCIE_MISCCFG_RC (0x1206c)
660
661 #define ISR_INT_TARGET_STATUS \
662 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
663 #define ISR_INT_TARGET_STATUS_F1 \
664 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
665 #define ISR_INT_TARGET_STATUS_F2 \
666 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
667 #define ISR_INT_TARGET_STATUS_F3 \
668 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
669 #define ISR_INT_TARGET_STATUS_F4 \
670 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
671 #define ISR_INT_TARGET_STATUS_F5 \
672 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
673 #define ISR_INT_TARGET_STATUS_F6 \
674 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
675 #define ISR_INT_TARGET_STATUS_F7 \
676 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
677
678 #define ISR_INT_TARGET_MASK \
679 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
680 #define ISR_INT_TARGET_MASK_F1 \
681 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
682 #define ISR_INT_TARGET_MASK_F2 \
683 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
684 #define ISR_INT_TARGET_MASK_F3 \
685 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
686 #define ISR_INT_TARGET_MASK_F4 \
687 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
688 #define ISR_INT_TARGET_MASK_F5 \
689 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
690 #define ISR_INT_TARGET_MASK_F6 \
691 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
692 #define ISR_INT_TARGET_MASK_F7 \
693 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
694
695 #define ISR_INT_VECTOR \
696 (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
697 #define ISR_INT_MASK \
698 (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
699 #define ISR_INT_STATE_REG \
700 (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
701
702 #define ISR_MSI_INT_TRIGGER(FUNC) \
703 (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
704
705 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
706 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
707
708 /*
709 * PCI Interrupt Vector Values.
710 */
711 #define PCIX_INT_VECTOR_BIT_F0 0x0080
712 #define PCIX_INT_VECTOR_BIT_F1 0x0100
713 #define PCIX_INT_VECTOR_BIT_F2 0x0200
714 #define PCIX_INT_VECTOR_BIT_F3 0x0400
715 #define PCIX_INT_VECTOR_BIT_F4 0x0800
716 #define PCIX_INT_VECTOR_BIT_F5 0x1000
717 #define PCIX_INT_VECTOR_BIT_F6 0x2000
718 #define PCIX_INT_VECTOR_BIT_F7 0x4000
719
720 struct qla82xx_legacy_intr_set {
721 uint32_t int_vec_bit;
722 uint32_t tgt_status_reg;
723 uint32_t tgt_mask_reg;
724 uint32_t pci_int_reg;
725 };
726
727 #define QLA82XX_LEGACY_INTR_CONFIG \
728 { \
729 { \
730 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
731 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
732 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
733 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
734 \
735 { \
736 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
737 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
738 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
739 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
740 \
741 { \
742 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
743 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
744 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
745 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
746 \
747 { \
748 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
749 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
750 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
751 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
752 \
753 { \
754 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
755 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
756 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
757 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
758 \
759 { \
760 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
761 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
762 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
763 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
764 \
765 { \
766 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
767 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
768 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
769 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
770 \
771 { \
772 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
773 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
774 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
775 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
776 }
777
778 #define BRDCFG_START 0x4000
779 #define BOOTLD_START 0x10000
780 #define IMAGE_START 0x100000
781 #define FLASH_ADDR_START 0x43000
782
783 /* Magic number to let user know flash is programmed */
784 #define QLA82XX_BDINFO_MAGIC 0x12345678
785 #define QLA82XX_FW_MAGIC_OFFSET (BRDCFG_START + 0x128)
786 #define FW_SIZE_OFFSET (0x3e840c)
787 #define QLA82XX_FW_MIN_SIZE 0x3fffff
788
789 /* UNIFIED ROMIMAGE START */
790 #define QLA82XX_URI_FW_MIN_SIZE 0xc8000
791 #define QLA82XX_URI_DIR_SECT_PRODUCT_TBL 0x0
792 #define QLA82XX_URI_DIR_SECT_BOOTLD 0x6
793 #define QLA82XX_URI_DIR_SECT_FW 0x7
794
795 /* Offsets */
796 #define QLA82XX_URI_CHIP_REV_OFF 10
797 #define QLA82XX_URI_FLAGS_OFF 11
798 #define QLA82XX_URI_BIOS_VERSION_OFF 12
799 #define QLA82XX_URI_BOOTLD_IDX_OFF 27
800 #define QLA82XX_URI_FIRMWARE_IDX_OFF 29
801
802 struct qla82xx_uri_table_desc{
803 uint32_t findex;
804 uint32_t num_entries;
805 uint32_t entry_size;
806 uint32_t reserved[5];
807 };
808
809 struct qla82xx_uri_data_desc{
810 uint32_t findex;
811 uint32_t size;
812 uint32_t reserved[5];
813 };
814
815 /* UNIFIED ROMIMAGE END */
816
817 #define QLA82XX_UNIFIED_ROMIMAGE 3
818 #define QLA82XX_FLASH_ROMIMAGE 4
819 #define QLA82XX_UNKNOWN_ROMIMAGE 0xff
820
821 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
822 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
823
824 /* Request and response queue size */
825 #define REQUEST_ENTRY_CNT_82XX 128 /* Number of request entries. */
826 #define RESPONSE_ENTRY_CNT_82XX 128 /* Number of response entries.*/
827
828 /*
829 * ISP 8021 I/O Register Set structure definitions.
830 */
831 struct device_reg_82xx {
832 uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */
833 uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */
834 uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */
835
836 uint16_t mailbox_in[32]; /* Mail box In registers */
837 uint16_t unused_1[32];
838 uint32_t hint; /* Host interrupt register */
839 #define HINT_MBX_INT_PENDING BIT_0
840 uint16_t unused_2[62];
841 uint16_t mailbox_out[32]; /* Mail box Out registers */
842 uint32_t unused_3[48];
843
844 uint32_t host_status; /* host status */
845 #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */
846 #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */
847 uint32_t host_int; /* Interrupt status. */
848 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
849 };
850
851 struct fcp_cmnd {
852 struct scsi_lun lun;
853 uint8_t crn;
854 uint8_t task_attribute;
855 uint8_t task_management;
856 uint8_t additional_cdb_len;
857 uint8_t cdb[260]; /* 256 for CDB len and 4 for FCP_DL */
858 };
859
860 struct dsd_dma {
861 struct list_head list;
862 dma_addr_t dsd_list_dma;
863 void *dsd_addr;
864 };
865
866 #define QLA_DSDS_PER_IOCB 37
867 #define QLA_DSD_SIZE 12
868 struct ct6_dsd {
869 uint16_t fcp_cmnd_len;
870 dma_addr_t fcp_cmnd_dma;
871 struct fcp_cmnd *fcp_cmnd;
872 int dsd_use_cnt;
873 struct list_head dsd_list;
874 };
875
876 #define MBC_TOGGLE_INTERRUPT 0x10
877 #define MBC_SET_LED_CONFIG 0x125 /* FCoE specific LED control */
878 #define MBC_GET_LED_CONFIG 0x126 /* FCoE specific LED control */
879
880 /* Flash offset */
881 #define FLT_REG_BOOTLOAD_82XX 0x72
882 #define FLT_REG_BOOT_CODE_82XX 0x78
883 #define FLT_REG_FW_82XX 0x74
884 #define FLT_REG_GOLD_FW_82XX 0x75
885 #define FLT_REG_VPD_8XXX 0x81
886
887 #define FA_VPD_SIZE_82XX 0x400
888
889 #define FA_FLASH_LAYOUT_ADDR_82 0xFC400
890
891 /******************************************************************************
892 *
893 * Definitions specific to M25P flash
894 *
895 *******************************************************************************
896 * Instructions
897 */
898 #define M25P_INSTR_WREN 0x06
899 #define M25P_INSTR_WRDI 0x04
900 #define M25P_INSTR_RDID 0x9f
901 #define M25P_INSTR_RDSR 0x05
902 #define M25P_INSTR_WRSR 0x01
903 #define M25P_INSTR_READ 0x03
904 #define M25P_INSTR_FAST_READ 0x0b
905 #define M25P_INSTR_PP 0x02
906 #define M25P_INSTR_SE 0xd8
907 #define M25P_INSTR_BE 0xc7
908 #define M25P_INSTR_DP 0xb9
909 #define M25P_INSTR_RES 0xab
910
911 /* Minidump related */
912
913 /*
914 * Version of the template
915 * 4 Bytes
916 * X.Major.Minor.RELEASE
917 */
918 #define QLA82XX_MINIDUMP_VERSION 0x10101
919
920 /*
921 * Entry Type Defines
922 */
923 #define QLA82XX_RDNOP 0
924 #define QLA82XX_RDCRB 1
925 #define QLA82XX_RDMUX 2
926 #define QLA82XX_QUEUE 3
927 #define QLA82XX_BOARD 4
928 #define QLA82XX_RDSRE 5
929 #define QLA82XX_RDOCM 6
930 #define QLA82XX_CACHE 10
931 #define QLA82XX_L1DAT 11
932 #define QLA82XX_L1INS 12
933 #define QLA82XX_L2DTG 21
934 #define QLA82XX_L2ITG 22
935 #define QLA82XX_L2DAT 23
936 #define QLA82XX_L2INS 24
937 #define QLA82XX_RDROM 71
938 #define QLA82XX_RDMEM 72
939 #define QLA82XX_CNTRL 98
940 #define QLA82XX_TLHDR 99
941 #define QLA82XX_RDEND 255
942 #define QLA8044_POLLRD 35
943 #define QLA8044_RDMUX2 36
944 #define QLA8044_L1DTG 8
945 #define QLA8044_L1ITG 9
946 #define QLA8044_POLLRDMWR 37
947
948 /*
949 * Opcodes for Control Entries.
950 * These Flags are bit fields.
951 */
952 #define QLA82XX_DBG_OPCODE_WR 0x01
953 #define QLA82XX_DBG_OPCODE_RW 0x02
954 #define QLA82XX_DBG_OPCODE_AND 0x04
955 #define QLA82XX_DBG_OPCODE_OR 0x08
956 #define QLA82XX_DBG_OPCODE_POLL 0x10
957 #define QLA82XX_DBG_OPCODE_RDSTATE 0x20
958 #define QLA82XX_DBG_OPCODE_WRSTATE 0x40
959 #define QLA82XX_DBG_OPCODE_MDSTATE 0x80
960
961 /*
962 * Template Header and Entry Header definitions start here.
963 */
964
965 /*
966 * Template Header
967 * Parts of the template header can be modified by the driver.
968 * These include the saved_state_array, capture_debug_level, driver_timestamp
969 */
970
971 #define QLA82XX_DBG_STATE_ARRAY_LEN 16
972 #define QLA82XX_DBG_CAP_SIZE_ARRAY_LEN 8
973 #define QLA82XX_DBG_RSVD_ARRAY_LEN 8
974
975 /*
976 * Driver Flags
977 */
978 #define QLA82XX_DBG_SKIPPED_FLAG 0x80 /* driver skipped this entry */
979 #define QLA82XX_DEFAULT_CAP_MASK 0xFF /* default capture mask */
980
981 struct qla82xx_md_template_hdr {
982 uint32_t entry_type;
983 uint32_t first_entry_offset;
984 uint32_t size_of_template;
985 uint32_t capture_debug_level;
986
987 uint32_t num_of_entries;
988 uint32_t version;
989 uint32_t driver_timestamp;
990 uint32_t template_checksum;
991
992 uint32_t driver_capture_mask;
993 uint32_t driver_info[3];
994
995 uint32_t saved_state_array[QLA82XX_DBG_STATE_ARRAY_LEN];
996 uint32_t capture_size_array[QLA82XX_DBG_CAP_SIZE_ARRAY_LEN];
997
998 /* markers_array used to capture some special locations on board */
999 uint32_t markers_array[QLA82XX_DBG_RSVD_ARRAY_LEN];
1000 uint32_t num_of_free_entries; /* For internal use */
1001 uint32_t free_entry_offset; /* For internal use */
1002 uint32_t total_table_size; /* For internal use */
1003 uint32_t bkup_table_offset; /* For internal use */
1004 } __packed;
1005
1006 /*
1007 * Entry Header: Common to All Entry Types
1008 */
1009
1010 /*
1011 * Driver Code is for driver to write some info about the entry.
1012 * Currently not used.
1013 */
1014 typedef struct qla82xx_md_entry_hdr {
1015 uint32_t entry_type;
1016 uint32_t entry_size;
1017 uint32_t entry_capture_size;
1018 struct {
1019 uint8_t entry_capture_mask;
1020 uint8_t entry_code;
1021 uint8_t driver_code;
1022 uint8_t driver_flags;
1023 } d_ctrl;
1024 } __packed qla82xx_md_entry_hdr_t;
1025
1026 /*
1027 * Read CRB entry header
1028 */
1029 struct qla82xx_md_entry_crb {
1030 qla82xx_md_entry_hdr_t h;
1031 uint32_t addr;
1032 struct {
1033 uint8_t addr_stride;
1034 uint8_t state_index_a;
1035 uint16_t poll_timeout;
1036 } crb_strd;
1037
1038 uint32_t data_size;
1039 uint32_t op_count;
1040
1041 struct {
1042 uint8_t opcode;
1043 uint8_t state_index_v;
1044 uint8_t shl;
1045 uint8_t shr;
1046 } crb_ctrl;
1047
1048 uint32_t value_1;
1049 uint32_t value_2;
1050 uint32_t value_3;
1051 } __packed;
1052
1053 /*
1054 * Cache entry header
1055 */
1056 struct qla82xx_md_entry_cache {
1057 qla82xx_md_entry_hdr_t h;
1058
1059 uint32_t tag_reg_addr;
1060 struct {
1061 uint16_t tag_value_stride;
1062 uint16_t init_tag_value;
1063 } addr_ctrl;
1064
1065 uint32_t data_size;
1066 uint32_t op_count;
1067
1068 uint32_t control_addr;
1069 struct {
1070 uint16_t write_value;
1071 uint8_t poll_mask;
1072 uint8_t poll_wait;
1073 } cache_ctrl;
1074
1075 uint32_t read_addr;
1076 struct {
1077 uint8_t read_addr_stride;
1078 uint8_t read_addr_cnt;
1079 uint16_t rsvd_1;
1080 } read_ctrl;
1081 } __packed;
1082
1083 /*
1084 * Read OCM
1085 */
1086 struct qla82xx_md_entry_rdocm {
1087 qla82xx_md_entry_hdr_t h;
1088
1089 uint32_t rsvd_0;
1090 uint32_t rsvd_1;
1091 uint32_t data_size;
1092 uint32_t op_count;
1093
1094 uint32_t rsvd_2;
1095 uint32_t rsvd_3;
1096 uint32_t read_addr;
1097 uint32_t read_addr_stride;
1098 uint32_t read_addr_cntrl;
1099 } __packed;
1100
1101 /*
1102 * Read Memory
1103 */
1104 struct qla82xx_md_entry_rdmem {
1105 qla82xx_md_entry_hdr_t h;
1106 uint32_t rsvd[6];
1107 uint32_t read_addr;
1108 uint32_t read_data_size;
1109 } __packed;
1110
1111 /*
1112 * Read ROM
1113 */
1114 struct qla82xx_md_entry_rdrom {
1115 qla82xx_md_entry_hdr_t h;
1116 uint32_t rsvd[6];
1117 uint32_t read_addr;
1118 uint32_t read_data_size;
1119 } __packed;
1120
1121 struct qla82xx_md_entry_mux {
1122 qla82xx_md_entry_hdr_t h;
1123
1124 uint32_t select_addr;
1125 uint32_t rsvd_0;
1126 uint32_t data_size;
1127 uint32_t op_count;
1128
1129 uint32_t select_value;
1130 uint32_t select_value_stride;
1131 uint32_t read_addr;
1132 uint32_t rsvd_1;
1133 } __packed;
1134
1135 struct qla82xx_md_entry_queue {
1136 qla82xx_md_entry_hdr_t h;
1137
1138 uint32_t select_addr;
1139 struct {
1140 uint16_t queue_id_stride;
1141 uint16_t rsvd_0;
1142 } q_strd;
1143
1144 uint32_t data_size;
1145 uint32_t op_count;
1146 uint32_t rsvd_1;
1147 uint32_t rsvd_2;
1148
1149 uint32_t read_addr;
1150 struct {
1151 uint8_t read_addr_stride;
1152 uint8_t read_addr_cnt;
1153 uint16_t rsvd_3;
1154 } rd_strd;
1155 } __packed;
1156
1157 #define MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE 0x129
1158 #define RQST_TMPLT_SIZE 0x0
1159 #define RQST_TMPLT 0x1
1160 #define MD_DIRECT_ROM_WINDOW 0x42110030
1161 #define MD_DIRECT_ROM_READ_BASE 0x42150000
1162 #define MD_MIU_TEST_AGT_CTRL 0x41000090
1163 #define MD_MIU_TEST_AGT_ADDR_LO 0x41000094
1164 #define MD_MIU_TEST_AGT_ADDR_HI 0x41000098
1165
1166 extern const int MD_MIU_TEST_AGT_RDDATA[4];
1167
1168 #define CRB_NIU_XG_PAUSE_CTL_P0 0x1
1169 #define CRB_NIU_XG_PAUSE_CTL_P1 0x8
1170
1171 #define qla82xx_get_temp_val(x) ((x) >> 16)
1172 #define qla82xx_get_temp_state(x) ((x) & 0xffff)
1173 #define qla82xx_encode_temp(val, state) (((val) << 16) | (state))
1174
1175 /*
1176 * Temperature control.
1177 */
1178 enum {
1179 QLA82XX_TEMP_NORMAL = 0x1, /* Normal operating range */
1180 QLA82XX_TEMP_WARN, /* Sound alert, temperature getting high */
1181 QLA82XX_TEMP_PANIC /* Fatal error, hardware has shut down. */
1182 };
1183
1184 #define LEG_INTR_PTR_OFFSET 0x38C0
1185 #define LEG_INTR_TRIG_OFFSET 0x38C4
1186 #define LEG_INTR_MASK_OFFSET 0x38C8
1187 #endif
Linux with added FPC-III support