1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
4 * Author: Chao Xie <chao.xie@marvell.com>
5 * Neil Zhang <zhangwm@marvell.com>
8 #include <linux/module.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmapool.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/ioport.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/timer.h>
20 #include <linux/list.h>
21 #include <linux/interrupt.h>
22 #include <linux/moduleparam.h>
23 #include <linux/device.h>
24 #include <linux/usb/ch9.h>
25 #include <linux/usb/gadget.h>
26 #include <linux/usb/otg.h>
29 #include <linux/irq.h>
30 #include <linux/platform_device.h>
31 #include <linux/clk.h>
32 #include <linux/platform_data/mv_usb.h>
33 #include <asm/unaligned.h>
37 #define DRIVER_DESC "Marvell PXA USB Device Controller driver"
39 #define ep_dir(ep) (((ep)->ep_num == 0) ? \
40 ((ep)->udc->ep0_dir) : ((ep)->direction))
42 /* timeout value -- usec */
43 #define RESET_TIMEOUT 10000
44 #define FLUSH_TIMEOUT 10000
45 #define EPSTATUS_TIMEOUT 10000
46 #define PRIME_TIMEOUT 10000
47 #define READSAFE_TIMEOUT 1000
49 #define LOOPS_USEC_SHIFT 1
50 #define LOOPS_USEC (1 << LOOPS_USEC_SHIFT)
51 #define LOOPS(timeout) ((timeout) >> LOOPS_USEC_SHIFT)
53 static DECLARE_COMPLETION(release_done
);
55 static const char driver_name
[] = "mv_udc";
56 static const char driver_desc
[] = DRIVER_DESC
;
58 static void nuke(struct mv_ep
*ep
, int status
);
59 static void stop_activity(struct mv_udc
*udc
, struct usb_gadget_driver
*driver
);
61 /* for endpoint 0 operations */
62 static const struct usb_endpoint_descriptor mv_ep0_desc
= {
63 .bLength
= USB_DT_ENDPOINT_SIZE
,
64 .bDescriptorType
= USB_DT_ENDPOINT
,
65 .bEndpointAddress
= 0,
66 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
67 .wMaxPacketSize
= EP0_MAX_PKT_SIZE
,
70 static void ep0_reset(struct mv_udc
*udc
)
77 for (i
= 0; i
< 2; i
++) {
82 ep
->dqh
= &udc
->ep_dqh
[i
];
84 /* configure ep0 endpoint capabilities in dQH */
85 ep
->dqh
->max_packet_length
=
86 (EP0_MAX_PKT_SIZE
<< EP_QUEUE_HEAD_MAX_PKT_LEN_POS
)
89 ep
->dqh
->next_dtd_ptr
= EP_QUEUE_HEAD_NEXT_TERMINATE
;
91 epctrlx
= readl(&udc
->op_regs
->epctrlx
[0]);
93 epctrlx
|= EPCTRL_TX_ENABLE
94 | (USB_ENDPOINT_XFER_CONTROL
95 << EPCTRL_TX_EP_TYPE_SHIFT
);
98 epctrlx
|= EPCTRL_RX_ENABLE
99 | (USB_ENDPOINT_XFER_CONTROL
100 << EPCTRL_RX_EP_TYPE_SHIFT
);
103 writel(epctrlx
, &udc
->op_regs
->epctrlx
[0]);
107 /* protocol ep0 stall, will automatically be cleared on new transaction */
108 static void ep0_stall(struct mv_udc
*udc
)
112 /* set TX and RX to stall */
113 epctrlx
= readl(&udc
->op_regs
->epctrlx
[0]);
114 epctrlx
|= EPCTRL_RX_EP_STALL
| EPCTRL_TX_EP_STALL
;
115 writel(epctrlx
, &udc
->op_regs
->epctrlx
[0]);
117 /* update ep0 state */
118 udc
->ep0_state
= WAIT_FOR_SETUP
;
119 udc
->ep0_dir
= EP_DIR_OUT
;
122 static int process_ep_req(struct mv_udc
*udc
, int index
,
123 struct mv_req
*curr_req
)
125 struct mv_dtd
*curr_dtd
;
126 struct mv_dqh
*curr_dqh
;
127 int actual
, remaining_length
;
133 curr_dqh
= &udc
->ep_dqh
[index
];
134 direction
= index
% 2;
136 curr_dtd
= curr_req
->head
;
137 actual
= curr_req
->req
.length
;
139 for (i
= 0; i
< curr_req
->dtd_count
; i
++) {
140 if (curr_dtd
->size_ioc_sts
& DTD_STATUS_ACTIVE
) {
141 dev_dbg(&udc
->dev
->dev
, "%s, dTD not completed\n",
142 udc
->eps
[index
].name
);
146 errors
= curr_dtd
->size_ioc_sts
& DTD_ERROR_MASK
;
149 (curr_dtd
->size_ioc_sts
& DTD_PACKET_SIZE
)
150 >> DTD_LENGTH_BIT_POS
;
151 actual
-= remaining_length
;
153 if (remaining_length
) {
155 dev_dbg(&udc
->dev
->dev
,
156 "TX dTD remains data\n");
163 dev_info(&udc
->dev
->dev
,
164 "complete_tr error: ep=%d %s: error = 0x%x\n",
165 index
>> 1, direction
? "SEND" : "RECV",
167 if (errors
& DTD_STATUS_HALTED
) {
168 /* Clear the errors and Halt condition */
169 curr_dqh
->size_ioc_int_sts
&= ~errors
;
171 } else if (errors
& DTD_STATUS_DATA_BUFF_ERR
) {
173 } else if (errors
& DTD_STATUS_TRANSACTION_ERR
) {
177 if (i
!= curr_req
->dtd_count
- 1)
178 curr_dtd
= (struct mv_dtd
*)curr_dtd
->next_dtd_virt
;
183 if (direction
== EP_DIR_OUT
)
184 bit_pos
= 1 << curr_req
->ep
->ep_num
;
186 bit_pos
= 1 << (16 + curr_req
->ep
->ep_num
);
188 while (curr_dqh
->curr_dtd_ptr
== curr_dtd
->td_dma
) {
189 if (curr_dtd
->dtd_next
== EP_QUEUE_HEAD_NEXT_TERMINATE
) {
190 while (readl(&udc
->op_regs
->epstatus
) & bit_pos
)
197 curr_req
->req
.actual
= actual
;
203 * done() - retire a request; caller blocked irqs
204 * @status : request status to be set, only works when
205 * request is still in progress.
207 static void done(struct mv_ep
*ep
, struct mv_req
*req
, int status
)
208 __releases(&ep
->udc
->lock
)
209 __acquires(&ep
->udc
->lock
)
211 struct mv_udc
*udc
= NULL
;
212 unsigned char stopped
= ep
->stopped
;
213 struct mv_dtd
*curr_td
, *next_td
;
216 udc
= (struct mv_udc
*)ep
->udc
;
217 /* Removed the req from fsl_ep->queue */
218 list_del_init(&req
->queue
);
220 /* req.status should be set as -EINPROGRESS in ep_queue() */
221 if (req
->req
.status
== -EINPROGRESS
)
222 req
->req
.status
= status
;
224 status
= req
->req
.status
;
226 /* Free dtd for the request */
228 for (j
= 0; j
< req
->dtd_count
; j
++) {
230 if (j
!= req
->dtd_count
- 1)
231 next_td
= curr_td
->next_dtd_virt
;
232 dma_pool_free(udc
->dtd_pool
, curr_td
, curr_td
->td_dma
);
235 usb_gadget_unmap_request(&udc
->gadget
, &req
->req
, ep_dir(ep
));
237 if (status
&& (status
!= -ESHUTDOWN
))
238 dev_info(&udc
->dev
->dev
, "complete %s req %p stat %d len %u/%u",
239 ep
->ep
.name
, &req
->req
, status
,
240 req
->req
.actual
, req
->req
.length
);
244 spin_unlock(&ep
->udc
->lock
);
246 usb_gadget_giveback_request(&ep
->ep
, &req
->req
);
248 spin_lock(&ep
->udc
->lock
);
249 ep
->stopped
= stopped
;
252 static int queue_dtd(struct mv_ep
*ep
, struct mv_req
*req
)
256 u32 bit_pos
, direction
;
257 u32 usbcmd
, epstatus
;
262 direction
= ep_dir(ep
);
263 dqh
= &(udc
->ep_dqh
[ep
->ep_num
* 2 + direction
]);
264 bit_pos
= 1 << (((direction
== EP_DIR_OUT
) ? 0 : 16) + ep
->ep_num
);
266 /* check if the pipe is empty */
267 if (!(list_empty(&ep
->queue
))) {
268 struct mv_req
*lastreq
;
269 lastreq
= list_entry(ep
->queue
.prev
, struct mv_req
, queue
);
270 lastreq
->tail
->dtd_next
=
271 req
->head
->td_dma
& EP_QUEUE_HEAD_NEXT_POINTER_MASK
;
275 if (readl(&udc
->op_regs
->epprime
) & bit_pos
)
278 loops
= LOOPS(READSAFE_TIMEOUT
);
280 /* start with setting the semaphores */
281 usbcmd
= readl(&udc
->op_regs
->usbcmd
);
282 usbcmd
|= USBCMD_ATDTW_TRIPWIRE_SET
;
283 writel(usbcmd
, &udc
->op_regs
->usbcmd
);
285 /* read the endpoint status */
286 epstatus
= readl(&udc
->op_regs
->epstatus
) & bit_pos
;
289 * Reread the ATDTW semaphore bit to check if it is
290 * cleared. When hardware see a hazard, it will clear
291 * the bit or else we remain set to 1 and we can
292 * proceed with priming of endpoint if not already
295 if (readl(&udc
->op_regs
->usbcmd
)
296 & USBCMD_ATDTW_TRIPWIRE_SET
)
301 dev_err(&udc
->dev
->dev
,
302 "Timeout for ATDTW_TRIPWIRE...\n");
309 /* Clear the semaphore */
310 usbcmd
= readl(&udc
->op_regs
->usbcmd
);
311 usbcmd
&= USBCMD_ATDTW_TRIPWIRE_CLEAR
;
312 writel(usbcmd
, &udc
->op_regs
->usbcmd
);
318 /* Write dQH next pointer and terminate bit to 0 */
319 dqh
->next_dtd_ptr
= req
->head
->td_dma
320 & EP_QUEUE_HEAD_NEXT_POINTER_MASK
;
322 /* clear active and halt bit, in case set from a previous error */
323 dqh
->size_ioc_int_sts
&= ~(DTD_STATUS_ACTIVE
| DTD_STATUS_HALTED
);
325 /* Ensure that updates to the QH will occur before priming. */
328 /* Prime the Endpoint */
329 writel(bit_pos
, &udc
->op_regs
->epprime
);
335 static struct mv_dtd
*build_dtd(struct mv_req
*req
, unsigned *length
,
336 dma_addr_t
*dma
, int *is_last
)
343 /* how big will this transfer be? */
344 if (usb_endpoint_xfer_isoc(req
->ep
->ep
.desc
)) {
346 mult
= (dqh
->max_packet_length
>> EP_QUEUE_HEAD_MULT_POS
)
348 *length
= min(req
->req
.length
- req
->req
.actual
,
349 (unsigned)(mult
* req
->ep
->ep
.maxpacket
));
351 *length
= min(req
->req
.length
- req
->req
.actual
,
352 (unsigned)EP_MAX_LENGTH_TRANSFER
);
357 * Be careful that no _GFP_HIGHMEM is set,
358 * or we can not use dma_to_virt
360 dtd
= dma_pool_alloc(udc
->dtd_pool
, GFP_ATOMIC
, dma
);
365 /* initialize buffer page pointers */
366 temp
= (u32
)(req
->req
.dma
+ req
->req
.actual
);
367 dtd
->buff_ptr0
= cpu_to_le32(temp
);
369 dtd
->buff_ptr1
= cpu_to_le32(temp
+ 0x1000);
370 dtd
->buff_ptr2
= cpu_to_le32(temp
+ 0x2000);
371 dtd
->buff_ptr3
= cpu_to_le32(temp
+ 0x3000);
372 dtd
->buff_ptr4
= cpu_to_le32(temp
+ 0x4000);
374 req
->req
.actual
+= *length
;
376 /* zlp is needed if req->req.zero is set */
378 if (*length
== 0 || (*length
% req
->ep
->ep
.maxpacket
) != 0)
382 } else if (req
->req
.length
== req
->req
.actual
)
387 /* Fill in the transfer size; set active bit */
388 temp
= ((*length
<< DTD_LENGTH_BIT_POS
) | DTD_STATUS_ACTIVE
);
390 /* Enable interrupt for the last dtd of a request */
391 if (*is_last
&& !req
->req
.no_interrupt
)
396 dtd
->size_ioc_sts
= temp
;
403 /* generate dTD linked list for a request */
404 static int req_to_dtd(struct mv_req
*req
)
407 int is_last
, is_first
= 1;
408 struct mv_dtd
*dtd
, *last_dtd
= NULL
;
412 dtd
= build_dtd(req
, &count
, &dma
, &is_last
);
420 last_dtd
->dtd_next
= dma
;
421 last_dtd
->next_dtd_virt
= dtd
;
427 /* set terminate bit to 1 for the last dTD */
428 dtd
->dtd_next
= DTD_NEXT_TERMINATE
;
435 static int mv_ep_enable(struct usb_ep
*_ep
,
436 const struct usb_endpoint_descriptor
*desc
)
442 u32 bit_pos
, epctrlx
, direction
;
443 const unsigned char zlt
= 1;
444 unsigned char ios
, mult
;
447 ep
= container_of(_ep
, struct mv_ep
, ep
);
451 || desc
->bDescriptorType
!= USB_DT_ENDPOINT
)
454 if (!udc
->driver
|| udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)
457 direction
= ep_dir(ep
);
458 max
= usb_endpoint_maxp(desc
);
461 * disable HW zero length termination select
462 * driver handles zero length packet through req->req.zero
464 bit_pos
= 1 << ((direction
== EP_DIR_OUT
? 0 : 16) + ep
->ep_num
);
466 /* Check if the Endpoint is Primed */
467 if ((readl(&udc
->op_regs
->epprime
) & bit_pos
)
468 || (readl(&udc
->op_regs
->epstatus
) & bit_pos
)) {
469 dev_info(&udc
->dev
->dev
,
470 "ep=%d %s: Init ERROR: ENDPTPRIME=0x%x,"
471 " ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
472 (unsigned)ep
->ep_num
, direction
? "SEND" : "RECV",
473 (unsigned)readl(&udc
->op_regs
->epprime
),
474 (unsigned)readl(&udc
->op_regs
->epstatus
),
479 /* Set the max packet length, interrupt on Setup and Mult fields */
482 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
483 case USB_ENDPOINT_XFER_BULK
:
484 case USB_ENDPOINT_XFER_INT
:
486 case USB_ENDPOINT_XFER_CONTROL
:
489 case USB_ENDPOINT_XFER_ISOC
:
490 /* Calculate transactions needed for high bandwidth iso */
491 mult
= usb_endpoint_maxp_mult(desc
);
492 /* 3 transactions at most */
500 spin_lock_irqsave(&udc
->lock
, flags
);
501 /* Get the endpoint queue head address */
503 dqh
->max_packet_length
= (max
<< EP_QUEUE_HEAD_MAX_PKT_LEN_POS
)
504 | (mult
<< EP_QUEUE_HEAD_MULT_POS
)
505 | (zlt
? EP_QUEUE_HEAD_ZLT_SEL
: 0)
506 | (ios
? EP_QUEUE_HEAD_IOS
: 0);
507 dqh
->next_dtd_ptr
= 1;
508 dqh
->size_ioc_int_sts
= 0;
510 ep
->ep
.maxpacket
= max
;
514 /* Enable the endpoint for Rx or Tx and set the endpoint type */
515 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
516 if (direction
== EP_DIR_IN
) {
517 epctrlx
&= ~EPCTRL_TX_ALL_MASK
;
518 epctrlx
|= EPCTRL_TX_ENABLE
| EPCTRL_TX_DATA_TOGGLE_RST
519 | ((desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
)
520 << EPCTRL_TX_EP_TYPE_SHIFT
);
522 epctrlx
&= ~EPCTRL_RX_ALL_MASK
;
523 epctrlx
|= EPCTRL_RX_ENABLE
| EPCTRL_RX_DATA_TOGGLE_RST
524 | ((desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
)
525 << EPCTRL_RX_EP_TYPE_SHIFT
);
527 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
530 * Implement Guideline (GL# USB-7) The unused endpoint type must
531 * be programmed to bulk.
533 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
534 if ((epctrlx
& EPCTRL_RX_ENABLE
) == 0) {
535 epctrlx
|= (USB_ENDPOINT_XFER_BULK
536 << EPCTRL_RX_EP_TYPE_SHIFT
);
537 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
540 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
541 if ((epctrlx
& EPCTRL_TX_ENABLE
) == 0) {
542 epctrlx
|= (USB_ENDPOINT_XFER_BULK
543 << EPCTRL_TX_EP_TYPE_SHIFT
);
544 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
547 spin_unlock_irqrestore(&udc
->lock
, flags
);
554 static int mv_ep_disable(struct usb_ep
*_ep
)
559 u32 epctrlx
, direction
;
562 ep
= container_of(_ep
, struct mv_ep
, ep
);
563 if ((_ep
== NULL
) || !ep
->ep
.desc
)
568 /* Get the endpoint queue head address */
571 spin_lock_irqsave(&udc
->lock
, flags
);
573 direction
= ep_dir(ep
);
575 /* Reset the max packet length and the interrupt on Setup */
576 dqh
->max_packet_length
= 0;
578 /* Disable the endpoint for Rx or Tx and reset the endpoint type */
579 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
580 epctrlx
&= ~((direction
== EP_DIR_IN
)
581 ? (EPCTRL_TX_ENABLE
| EPCTRL_TX_TYPE
)
582 : (EPCTRL_RX_ENABLE
| EPCTRL_RX_TYPE
));
583 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
585 /* nuke all pending requests (does flush) */
586 nuke(ep
, -ESHUTDOWN
);
591 spin_unlock_irqrestore(&udc
->lock
, flags
);
596 static struct usb_request
*
597 mv_alloc_request(struct usb_ep
*_ep
, gfp_t gfp_flags
)
599 struct mv_req
*req
= NULL
;
601 req
= kzalloc(sizeof *req
, gfp_flags
);
605 req
->req
.dma
= DMA_ADDR_INVALID
;
606 INIT_LIST_HEAD(&req
->queue
);
611 static void mv_free_request(struct usb_ep
*_ep
, struct usb_request
*_req
)
613 struct mv_req
*req
= NULL
;
615 req
= container_of(_req
, struct mv_req
, req
);
621 static void mv_ep_fifo_flush(struct usb_ep
*_ep
)
624 u32 bit_pos
, direction
;
631 ep
= container_of(_ep
, struct mv_ep
, ep
);
636 direction
= ep_dir(ep
);
639 bit_pos
= (1 << 16) | 1;
640 else if (direction
== EP_DIR_OUT
)
641 bit_pos
= 1 << ep
->ep_num
;
643 bit_pos
= 1 << (16 + ep
->ep_num
);
645 loops
= LOOPS(EPSTATUS_TIMEOUT
);
647 unsigned int inter_loops
;
650 dev_err(&udc
->dev
->dev
,
651 "TIMEOUT for ENDPTSTATUS=0x%x, bit_pos=0x%x\n",
652 (unsigned)readl(&udc
->op_regs
->epstatus
),
656 /* Write 1 to the Flush register */
657 writel(bit_pos
, &udc
->op_regs
->epflush
);
659 /* Wait until flushing completed */
660 inter_loops
= LOOPS(FLUSH_TIMEOUT
);
661 while (readl(&udc
->op_regs
->epflush
)) {
663 * ENDPTFLUSH bit should be cleared to indicate this
664 * operation is complete
666 if (inter_loops
== 0) {
667 dev_err(&udc
->dev
->dev
,
668 "TIMEOUT for ENDPTFLUSH=0x%x,"
670 (unsigned)readl(&udc
->op_regs
->epflush
),
678 } while (readl(&udc
->op_regs
->epstatus
) & bit_pos
);
681 /* queues (submits) an I/O request to an endpoint */
683 mv_ep_queue(struct usb_ep
*_ep
, struct usb_request
*_req
, gfp_t gfp_flags
)
685 struct mv_ep
*ep
= container_of(_ep
, struct mv_ep
, ep
);
686 struct mv_req
*req
= container_of(_req
, struct mv_req
, req
);
687 struct mv_udc
*udc
= ep
->udc
;
691 /* catch various bogus parameters */
692 if (!_req
|| !req
->req
.complete
|| !req
->req
.buf
693 || !list_empty(&req
->queue
)) {
694 dev_err(&udc
->dev
->dev
, "%s, bad params", __func__
);
697 if (unlikely(!_ep
|| !ep
->ep
.desc
)) {
698 dev_err(&udc
->dev
->dev
, "%s, bad ep", __func__
);
703 if (!udc
->driver
|| udc
->gadget
.speed
== USB_SPEED_UNKNOWN
)
708 /* map virtual address to hardware */
709 retval
= usb_gadget_map_request(&udc
->gadget
, _req
, ep_dir(ep
));
713 req
->req
.status
= -EINPROGRESS
;
717 spin_lock_irqsave(&udc
->lock
, flags
);
719 /* build dtds and push them to device queue */
720 if (!req_to_dtd(req
)) {
721 retval
= queue_dtd(ep
, req
);
723 spin_unlock_irqrestore(&udc
->lock
, flags
);
724 dev_err(&udc
->dev
->dev
, "Failed to queue dtd\n");
728 spin_unlock_irqrestore(&udc
->lock
, flags
);
729 dev_err(&udc
->dev
->dev
, "Failed to dma_pool_alloc\n");
734 /* Update ep0 state */
736 udc
->ep0_state
= DATA_STATE_XMIT
;
738 /* irq handler advances the queue */
739 list_add_tail(&req
->queue
, &ep
->queue
);
740 spin_unlock_irqrestore(&udc
->lock
, flags
);
745 usb_gadget_unmap_request(&udc
->gadget
, _req
, ep_dir(ep
));
750 static void mv_prime_ep(struct mv_ep
*ep
, struct mv_req
*req
)
752 struct mv_dqh
*dqh
= ep
->dqh
;
755 /* Write dQH next pointer and terminate bit to 0 */
756 dqh
->next_dtd_ptr
= req
->head
->td_dma
757 & EP_QUEUE_HEAD_NEXT_POINTER_MASK
;
759 /* clear active and halt bit, in case set from a previous error */
760 dqh
->size_ioc_int_sts
&= ~(DTD_STATUS_ACTIVE
| DTD_STATUS_HALTED
);
762 /* Ensure that updates to the QH will occure before priming. */
765 bit_pos
= 1 << (((ep_dir(ep
) == EP_DIR_OUT
) ? 0 : 16) + ep
->ep_num
);
767 /* Prime the Endpoint */
768 writel(bit_pos
, &ep
->udc
->op_regs
->epprime
);
771 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
772 static int mv_ep_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
774 struct mv_ep
*ep
= container_of(_ep
, struct mv_ep
, ep
);
776 struct mv_udc
*udc
= ep
->udc
;
778 int stopped
, ret
= 0;
784 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
785 stopped
= ep
->stopped
;
787 /* Stop the ep before we deal with the queue */
789 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
790 if (ep_dir(ep
) == EP_DIR_IN
)
791 epctrlx
&= ~EPCTRL_TX_ENABLE
;
793 epctrlx
&= ~EPCTRL_RX_ENABLE
;
794 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
796 /* make sure it's actually queued on this endpoint */
797 list_for_each_entry(req
, &ep
->queue
, queue
) {
798 if (&req
->req
== _req
)
801 if (&req
->req
!= _req
) {
806 /* The request is in progress, or completed but not dequeued */
807 if (ep
->queue
.next
== &req
->queue
) {
808 _req
->status
= -ECONNRESET
;
809 mv_ep_fifo_flush(_ep
); /* flush current transfer */
811 /* The request isn't the last request in this ep queue */
812 if (req
->queue
.next
!= &ep
->queue
) {
813 struct mv_req
*next_req
;
815 next_req
= list_entry(req
->queue
.next
,
816 struct mv_req
, queue
);
818 /* Point the QH to the first TD of next request */
819 mv_prime_ep(ep
, next_req
);
824 qh
->next_dtd_ptr
= 1;
825 qh
->size_ioc_int_sts
= 0;
828 /* The request hasn't been processed, patch up the TD chain */
830 struct mv_req
*prev_req
;
832 prev_req
= list_entry(req
->queue
.prev
, struct mv_req
, queue
);
833 writel(readl(&req
->tail
->dtd_next
),
834 &prev_req
->tail
->dtd_next
);
838 done(ep
, req
, -ECONNRESET
);
842 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep
->ep_num
]);
843 if (ep_dir(ep
) == EP_DIR_IN
)
844 epctrlx
|= EPCTRL_TX_ENABLE
;
846 epctrlx
|= EPCTRL_RX_ENABLE
;
847 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep
->ep_num
]);
848 ep
->stopped
= stopped
;
850 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
854 static void ep_set_stall(struct mv_udc
*udc
, u8 ep_num
, u8 direction
, int stall
)
858 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep_num
]);
861 if (direction
== EP_DIR_IN
)
862 epctrlx
|= EPCTRL_TX_EP_STALL
;
864 epctrlx
|= EPCTRL_RX_EP_STALL
;
866 if (direction
== EP_DIR_IN
) {
867 epctrlx
&= ~EPCTRL_TX_EP_STALL
;
868 epctrlx
|= EPCTRL_TX_DATA_TOGGLE_RST
;
870 epctrlx
&= ~EPCTRL_RX_EP_STALL
;
871 epctrlx
|= EPCTRL_RX_DATA_TOGGLE_RST
;
874 writel(epctrlx
, &udc
->op_regs
->epctrlx
[ep_num
]);
877 static int ep_is_stall(struct mv_udc
*udc
, u8 ep_num
, u8 direction
)
881 epctrlx
= readl(&udc
->op_regs
->epctrlx
[ep_num
]);
883 if (direction
== EP_DIR_OUT
)
884 return (epctrlx
& EPCTRL_RX_EP_STALL
) ? 1 : 0;
886 return (epctrlx
& EPCTRL_TX_EP_STALL
) ? 1 : 0;
889 static int mv_ep_set_halt_wedge(struct usb_ep
*_ep
, int halt
, int wedge
)
892 unsigned long flags
= 0;
896 ep
= container_of(_ep
, struct mv_ep
, ep
);
898 if (!_ep
|| !ep
->ep
.desc
) {
903 if (ep
->ep
.desc
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
904 status
= -EOPNOTSUPP
;
909 * Attempt to halt IN ep will fail if any transfer requests
912 if (halt
&& (ep_dir(ep
) == EP_DIR_IN
) && !list_empty(&ep
->queue
)) {
917 spin_lock_irqsave(&ep
->udc
->lock
, flags
);
918 ep_set_stall(udc
, ep
->ep_num
, ep_dir(ep
), halt
);
923 spin_unlock_irqrestore(&ep
->udc
->lock
, flags
);
925 if (ep
->ep_num
== 0) {
926 udc
->ep0_state
= WAIT_FOR_SETUP
;
927 udc
->ep0_dir
= EP_DIR_OUT
;
933 static int mv_ep_set_halt(struct usb_ep
*_ep
, int halt
)
935 return mv_ep_set_halt_wedge(_ep
, halt
, 0);
938 static int mv_ep_set_wedge(struct usb_ep
*_ep
)
940 return mv_ep_set_halt_wedge(_ep
, 1, 1);
943 static const struct usb_ep_ops mv_ep_ops
= {
944 .enable
= mv_ep_enable
,
945 .disable
= mv_ep_disable
,
947 .alloc_request
= mv_alloc_request
,
948 .free_request
= mv_free_request
,
950 .queue
= mv_ep_queue
,
951 .dequeue
= mv_ep_dequeue
,
953 .set_wedge
= mv_ep_set_wedge
,
954 .set_halt
= mv_ep_set_halt
,
955 .fifo_flush
= mv_ep_fifo_flush
, /* flush fifo */
958 static int udc_clock_enable(struct mv_udc
*udc
)
960 return clk_prepare_enable(udc
->clk
);
963 static void udc_clock_disable(struct mv_udc
*udc
)
965 clk_disable_unprepare(udc
->clk
);
968 static void udc_stop(struct mv_udc
*udc
)
972 /* Disable interrupts */
973 tmp
= readl(&udc
->op_regs
->usbintr
);
974 tmp
&= ~(USBINTR_INT_EN
| USBINTR_ERR_INT_EN
|
975 USBINTR_PORT_CHANGE_DETECT_EN
| USBINTR_RESET_EN
);
976 writel(tmp
, &udc
->op_regs
->usbintr
);
980 /* Reset the Run the bit in the command register to stop VUSB */
981 tmp
= readl(&udc
->op_regs
->usbcmd
);
982 tmp
&= ~USBCMD_RUN_STOP
;
983 writel(tmp
, &udc
->op_regs
->usbcmd
);
986 static void udc_start(struct mv_udc
*udc
)
990 usbintr
= USBINTR_INT_EN
| USBINTR_ERR_INT_EN
991 | USBINTR_PORT_CHANGE_DETECT_EN
992 | USBINTR_RESET_EN
| USBINTR_DEVICE_SUSPEND
;
993 /* Enable interrupts */
994 writel(usbintr
, &udc
->op_regs
->usbintr
);
998 /* Set the Run bit in the command register */
999 writel(USBCMD_RUN_STOP
, &udc
->op_regs
->usbcmd
);
1002 static int udc_reset(struct mv_udc
*udc
)
1007 /* Stop the controller */
1008 tmp
= readl(&udc
->op_regs
->usbcmd
);
1009 tmp
&= ~USBCMD_RUN_STOP
;
1010 writel(tmp
, &udc
->op_regs
->usbcmd
);
1012 /* Reset the controller to get default values */
1013 writel(USBCMD_CTRL_RESET
, &udc
->op_regs
->usbcmd
);
1015 /* wait for reset to complete */
1016 loops
= LOOPS(RESET_TIMEOUT
);
1017 while (readl(&udc
->op_regs
->usbcmd
) & USBCMD_CTRL_RESET
) {
1019 dev_err(&udc
->dev
->dev
,
1020 "Wait for RESET completed TIMEOUT\n");
1027 /* set controller to device mode */
1028 tmp
= readl(&udc
->op_regs
->usbmode
);
1029 tmp
|= USBMODE_CTRL_MODE_DEVICE
;
1031 /* turn setup lockout off, require setup tripwire in usbcmd */
1032 tmp
|= USBMODE_SETUP_LOCK_OFF
;
1034 writel(tmp
, &udc
->op_regs
->usbmode
);
1036 writel(0x0, &udc
->op_regs
->epsetupstat
);
1038 /* Configure the Endpoint List Address */
1039 writel(udc
->ep_dqh_dma
& USB_EP_LIST_ADDRESS_MASK
,
1040 &udc
->op_regs
->eplistaddr
);
1042 portsc
= readl(&udc
->op_regs
->portsc
[0]);
1043 if (readl(&udc
->cap_regs
->hcsparams
) & HCSPARAMS_PPC
)
1044 portsc
&= (~PORTSCX_W1C_BITS
| ~PORTSCX_PORT_POWER
);
1047 portsc
|= PORTSCX_FORCE_FULL_SPEED_CONNECT
;
1049 portsc
&= (~PORTSCX_FORCE_FULL_SPEED_CONNECT
);
1051 writel(portsc
, &udc
->op_regs
->portsc
[0]);
1053 tmp
= readl(&udc
->op_regs
->epctrlx
[0]);
1054 tmp
&= ~(EPCTRL_TX_EP_STALL
| EPCTRL_RX_EP_STALL
);
1055 writel(tmp
, &udc
->op_regs
->epctrlx
[0]);
1060 static int mv_udc_enable_internal(struct mv_udc
*udc
)
1067 dev_dbg(&udc
->dev
->dev
, "enable udc\n");
1068 retval
= udc_clock_enable(udc
);
1072 if (udc
->pdata
->phy_init
) {
1073 retval
= udc
->pdata
->phy_init(udc
->phy_regs
);
1075 dev_err(&udc
->dev
->dev
,
1076 "init phy error %d\n", retval
);
1077 udc_clock_disable(udc
);
1086 static int mv_udc_enable(struct mv_udc
*udc
)
1088 if (udc
->clock_gating
)
1089 return mv_udc_enable_internal(udc
);
1094 static void mv_udc_disable_internal(struct mv_udc
*udc
)
1097 dev_dbg(&udc
->dev
->dev
, "disable udc\n");
1098 if (udc
->pdata
->phy_deinit
)
1099 udc
->pdata
->phy_deinit(udc
->phy_regs
);
1100 udc_clock_disable(udc
);
1105 static void mv_udc_disable(struct mv_udc
*udc
)
1107 if (udc
->clock_gating
)
1108 mv_udc_disable_internal(udc
);
1111 static int mv_udc_get_frame(struct usb_gadget
*gadget
)
1119 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1121 retval
= readl(&udc
->op_regs
->frindex
) & USB_FRINDEX_MASKS
;
1126 /* Tries to wake up the host connected to this gadget */
1127 static int mv_udc_wakeup(struct usb_gadget
*gadget
)
1129 struct mv_udc
*udc
= container_of(gadget
, struct mv_udc
, gadget
);
1132 /* Remote wakeup feature not enabled by host */
1133 if (!udc
->remote_wakeup
)
1136 portsc
= readl(&udc
->op_regs
->portsc
);
1137 /* not suspended? */
1138 if (!(portsc
& PORTSCX_PORT_SUSPEND
))
1140 /* trigger force resume */
1141 portsc
|= PORTSCX_PORT_FORCE_RESUME
;
1142 writel(portsc
, &udc
->op_regs
->portsc
[0]);
1146 static int mv_udc_vbus_session(struct usb_gadget
*gadget
, int is_active
)
1149 unsigned long flags
;
1152 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1153 spin_lock_irqsave(&udc
->lock
, flags
);
1155 udc
->vbus_active
= (is_active
!= 0);
1157 dev_dbg(&udc
->dev
->dev
, "%s: softconnect %d, vbus_active %d\n",
1158 __func__
, udc
->softconnect
, udc
->vbus_active
);
1160 if (udc
->driver
&& udc
->softconnect
&& udc
->vbus_active
) {
1161 retval
= mv_udc_enable(udc
);
1163 /* Clock is disabled, need re-init registers */
1168 } else if (udc
->driver
&& udc
->softconnect
) {
1172 /* stop all the transfer in queue*/
1173 stop_activity(udc
, udc
->driver
);
1175 mv_udc_disable(udc
);
1179 spin_unlock_irqrestore(&udc
->lock
, flags
);
1183 static int mv_udc_pullup(struct usb_gadget
*gadget
, int is_on
)
1186 unsigned long flags
;
1189 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1190 spin_lock_irqsave(&udc
->lock
, flags
);
1192 udc
->softconnect
= (is_on
!= 0);
1194 dev_dbg(&udc
->dev
->dev
, "%s: softconnect %d, vbus_active %d\n",
1195 __func__
, udc
->softconnect
, udc
->vbus_active
);
1197 if (udc
->driver
&& udc
->softconnect
&& udc
->vbus_active
) {
1198 retval
= mv_udc_enable(udc
);
1200 /* Clock is disabled, need re-init registers */
1205 } else if (udc
->driver
&& udc
->vbus_active
) {
1206 /* stop all the transfer in queue*/
1207 stop_activity(udc
, udc
->driver
);
1209 mv_udc_disable(udc
);
1212 spin_unlock_irqrestore(&udc
->lock
, flags
);
1216 static int mv_udc_start(struct usb_gadget
*, struct usb_gadget_driver
*);
1217 static int mv_udc_stop(struct usb_gadget
*);
1218 /* device controller usb_gadget_ops structure */
1219 static const struct usb_gadget_ops mv_ops
= {
1221 /* returns the current frame number */
1222 .get_frame
= mv_udc_get_frame
,
1224 /* tries to wake up the host connected to this gadget */
1225 .wakeup
= mv_udc_wakeup
,
1227 /* notify controller that VBUS is powered or not */
1228 .vbus_session
= mv_udc_vbus_session
,
1230 /* D+ pullup, software-controlled connect/disconnect to USB host */
1231 .pullup
= mv_udc_pullup
,
1232 .udc_start
= mv_udc_start
,
1233 .udc_stop
= mv_udc_stop
,
1236 static int eps_init(struct mv_udc
*udc
)
1242 /* initialize ep0 */
1245 strncpy(ep
->name
, "ep0", sizeof(ep
->name
));
1246 ep
->ep
.name
= ep
->name
;
1247 ep
->ep
.ops
= &mv_ep_ops
;
1250 usb_ep_set_maxpacket_limit(&ep
->ep
, EP0_MAX_PKT_SIZE
);
1251 ep
->ep
.caps
.type_control
= true;
1252 ep
->ep
.caps
.dir_in
= true;
1253 ep
->ep
.caps
.dir_out
= true;
1255 ep
->ep
.desc
= &mv_ep0_desc
;
1256 INIT_LIST_HEAD(&ep
->queue
);
1258 ep
->ep_type
= USB_ENDPOINT_XFER_CONTROL
;
1260 /* initialize other endpoints */
1261 for (i
= 2; i
< udc
->max_eps
* 2; i
++) {
1264 snprintf(name
, sizeof(name
), "ep%din", i
/ 2);
1265 ep
->direction
= EP_DIR_IN
;
1266 ep
->ep
.caps
.dir_in
= true;
1268 snprintf(name
, sizeof(name
), "ep%dout", i
/ 2);
1269 ep
->direction
= EP_DIR_OUT
;
1270 ep
->ep
.caps
.dir_out
= true;
1273 strncpy(ep
->name
, name
, sizeof(ep
->name
));
1274 ep
->ep
.name
= ep
->name
;
1276 ep
->ep
.caps
.type_iso
= true;
1277 ep
->ep
.caps
.type_bulk
= true;
1278 ep
->ep
.caps
.type_int
= true;
1280 ep
->ep
.ops
= &mv_ep_ops
;
1282 usb_ep_set_maxpacket_limit(&ep
->ep
, (unsigned short) ~0);
1285 INIT_LIST_HEAD(&ep
->queue
);
1286 list_add_tail(&ep
->ep
.ep_list
, &udc
->gadget
.ep_list
);
1288 ep
->dqh
= &udc
->ep_dqh
[i
];
1294 /* delete all endpoint requests, called with spinlock held */
1295 static void nuke(struct mv_ep
*ep
, int status
)
1297 /* called with spinlock held */
1300 /* endpoint fifo flush */
1301 mv_ep_fifo_flush(&ep
->ep
);
1303 while (!list_empty(&ep
->queue
)) {
1304 struct mv_req
*req
= NULL
;
1305 req
= list_entry(ep
->queue
.next
, struct mv_req
, queue
);
1306 done(ep
, req
, status
);
1310 static void gadget_reset(struct mv_udc
*udc
, struct usb_gadget_driver
*driver
)
1314 nuke(&udc
->eps
[0], -ESHUTDOWN
);
1316 list_for_each_entry(ep
, &udc
->gadget
.ep_list
, ep
.ep_list
) {
1317 nuke(ep
, -ESHUTDOWN
);
1320 /* report reset; the driver is already quiesced */
1322 spin_unlock(&udc
->lock
);
1323 usb_gadget_udc_reset(&udc
->gadget
, driver
);
1324 spin_lock(&udc
->lock
);
1327 /* stop all USB activities */
1328 static void stop_activity(struct mv_udc
*udc
, struct usb_gadget_driver
*driver
)
1332 nuke(&udc
->eps
[0], -ESHUTDOWN
);
1334 list_for_each_entry(ep
, &udc
->gadget
.ep_list
, ep
.ep_list
) {
1335 nuke(ep
, -ESHUTDOWN
);
1338 /* report disconnect; the driver is already quiesced */
1340 spin_unlock(&udc
->lock
);
1341 driver
->disconnect(&udc
->gadget
);
1342 spin_lock(&udc
->lock
);
1346 static int mv_udc_start(struct usb_gadget
*gadget
,
1347 struct usb_gadget_driver
*driver
)
1351 unsigned long flags
;
1353 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1358 spin_lock_irqsave(&udc
->lock
, flags
);
1360 /* hook up the driver ... */
1361 driver
->driver
.bus
= NULL
;
1362 udc
->driver
= driver
;
1364 udc
->usb_state
= USB_STATE_ATTACHED
;
1365 udc
->ep0_state
= WAIT_FOR_SETUP
;
1366 udc
->ep0_dir
= EP_DIR_OUT
;
1368 spin_unlock_irqrestore(&udc
->lock
, flags
);
1370 if (udc
->transceiver
) {
1371 retval
= otg_set_peripheral(udc
->transceiver
->otg
,
1374 dev_err(&udc
->dev
->dev
,
1375 "unable to register peripheral to otg\n");
1381 /* When boot with cable attached, there will be no vbus irq occurred */
1383 queue_work(udc
->qwork
, &udc
->vbus_work
);
1388 static int mv_udc_stop(struct usb_gadget
*gadget
)
1391 unsigned long flags
;
1393 udc
= container_of(gadget
, struct mv_udc
, gadget
);
1395 spin_lock_irqsave(&udc
->lock
, flags
);
1400 /* stop all usb activities */
1401 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1402 stop_activity(udc
, NULL
);
1403 mv_udc_disable(udc
);
1405 spin_unlock_irqrestore(&udc
->lock
, flags
);
1407 /* unbind gadget driver */
1413 static void mv_set_ptc(struct mv_udc
*udc
, u32 mode
)
1417 portsc
= readl(&udc
->op_regs
->portsc
[0]);
1418 portsc
|= mode
<< 16;
1419 writel(portsc
, &udc
->op_regs
->portsc
[0]);
1422 static void prime_status_complete(struct usb_ep
*ep
, struct usb_request
*_req
)
1424 struct mv_ep
*mvep
= container_of(ep
, struct mv_ep
, ep
);
1425 struct mv_req
*req
= container_of(_req
, struct mv_req
, req
);
1427 unsigned long flags
;
1431 dev_info(&udc
->dev
->dev
, "switch to test mode %d\n", req
->test_mode
);
1433 spin_lock_irqsave(&udc
->lock
, flags
);
1434 if (req
->test_mode
) {
1435 mv_set_ptc(udc
, req
->test_mode
);
1438 spin_unlock_irqrestore(&udc
->lock
, flags
);
1442 udc_prime_status(struct mv_udc
*udc
, u8 direction
, u16 status
, bool empty
)
1449 udc
->ep0_dir
= direction
;
1450 udc
->ep0_state
= WAIT_FOR_OUT_STATUS
;
1452 req
= udc
->status_req
;
1454 /* fill in the reqest structure */
1455 if (empty
== false) {
1456 *((u16
*) req
->req
.buf
) = cpu_to_le16(status
);
1457 req
->req
.length
= 2;
1459 req
->req
.length
= 0;
1462 req
->req
.status
= -EINPROGRESS
;
1463 req
->req
.actual
= 0;
1464 if (udc
->test_mode
) {
1465 req
->req
.complete
= prime_status_complete
;
1466 req
->test_mode
= udc
->test_mode
;
1469 req
->req
.complete
= NULL
;
1472 if (req
->req
.dma
== DMA_ADDR_INVALID
) {
1473 req
->req
.dma
= dma_map_single(ep
->udc
->gadget
.dev
.parent
,
1474 req
->req
.buf
, req
->req
.length
,
1475 ep_dir(ep
) ? DMA_TO_DEVICE
: DMA_FROM_DEVICE
);
1479 /* prime the data phase */
1480 if (!req_to_dtd(req
)) {
1481 retval
= queue_dtd(ep
, req
);
1483 dev_err(&udc
->dev
->dev
,
1484 "Failed to queue dtd when prime status\n");
1487 } else{ /* no mem */
1489 dev_err(&udc
->dev
->dev
,
1490 "Failed to dma_pool_alloc when prime status\n");
1494 list_add_tail(&req
->queue
, &ep
->queue
);
1498 usb_gadget_unmap_request(&udc
->gadget
, &req
->req
, ep_dir(ep
));
1503 static void mv_udc_testmode(struct mv_udc
*udc
, u16 index
)
1505 if (index
<= TEST_FORCE_EN
) {
1506 udc
->test_mode
= index
;
1507 if (udc_prime_status(udc
, EP_DIR_IN
, 0, true))
1510 dev_err(&udc
->dev
->dev
,
1511 "This test mode(%d) is not supported\n", index
);
1514 static void ch9setaddress(struct mv_udc
*udc
, struct usb_ctrlrequest
*setup
)
1516 udc
->dev_addr
= (u8
)setup
->wValue
;
1518 /* update usb state */
1519 udc
->usb_state
= USB_STATE_ADDRESS
;
1521 if (udc_prime_status(udc
, EP_DIR_IN
, 0, true))
1525 static void ch9getstatus(struct mv_udc
*udc
, u8 ep_num
,
1526 struct usb_ctrlrequest
*setup
)
1531 if ((setup
->bRequestType
& (USB_DIR_IN
| USB_TYPE_MASK
))
1532 != (USB_DIR_IN
| USB_TYPE_STANDARD
))
1535 if ((setup
->bRequestType
& USB_RECIP_MASK
) == USB_RECIP_DEVICE
) {
1536 status
= 1 << USB_DEVICE_SELF_POWERED
;
1537 status
|= udc
->remote_wakeup
<< USB_DEVICE_REMOTE_WAKEUP
;
1538 } else if ((setup
->bRequestType
& USB_RECIP_MASK
)
1539 == USB_RECIP_INTERFACE
) {
1540 /* get interface status */
1542 } else if ((setup
->bRequestType
& USB_RECIP_MASK
)
1543 == USB_RECIP_ENDPOINT
) {
1544 u8 ep_num
, direction
;
1546 ep_num
= setup
->wIndex
& USB_ENDPOINT_NUMBER_MASK
;
1547 direction
= (setup
->wIndex
& USB_ENDPOINT_DIR_MASK
)
1548 ? EP_DIR_IN
: EP_DIR_OUT
;
1549 status
= ep_is_stall(udc
, ep_num
, direction
)
1550 << USB_ENDPOINT_HALT
;
1553 retval
= udc_prime_status(udc
, EP_DIR_IN
, status
, false);
1557 udc
->ep0_state
= DATA_STATE_XMIT
;
1560 static void ch9clearfeature(struct mv_udc
*udc
, struct usb_ctrlrequest
*setup
)
1566 if ((setup
->bRequestType
& (USB_TYPE_MASK
| USB_RECIP_MASK
))
1567 == ((USB_TYPE_STANDARD
| USB_RECIP_DEVICE
))) {
1568 switch (setup
->wValue
) {
1569 case USB_DEVICE_REMOTE_WAKEUP
:
1570 udc
->remote_wakeup
= 0;
1575 } else if ((setup
->bRequestType
& (USB_TYPE_MASK
| USB_RECIP_MASK
))
1576 == ((USB_TYPE_STANDARD
| USB_RECIP_ENDPOINT
))) {
1577 switch (setup
->wValue
) {
1578 case USB_ENDPOINT_HALT
:
1579 ep_num
= setup
->wIndex
& USB_ENDPOINT_NUMBER_MASK
;
1580 direction
= (setup
->wIndex
& USB_ENDPOINT_DIR_MASK
)
1581 ? EP_DIR_IN
: EP_DIR_OUT
;
1582 if (setup
->wValue
!= 0 || setup
->wLength
!= 0
1583 || ep_num
> udc
->max_eps
)
1585 ep
= &udc
->eps
[ep_num
* 2 + direction
];
1588 spin_unlock(&udc
->lock
);
1589 ep_set_stall(udc
, ep_num
, direction
, 0);
1590 spin_lock(&udc
->lock
);
1598 if (udc_prime_status(udc
, EP_DIR_IN
, 0, true))
1604 static void ch9setfeature(struct mv_udc
*udc
, struct usb_ctrlrequest
*setup
)
1609 if ((setup
->bRequestType
& (USB_TYPE_MASK
| USB_RECIP_MASK
))
1610 == ((USB_TYPE_STANDARD
| USB_RECIP_DEVICE
))) {
1611 switch (setup
->wValue
) {
1612 case USB_DEVICE_REMOTE_WAKEUP
:
1613 udc
->remote_wakeup
= 1;
1615 case USB_DEVICE_TEST_MODE
:
1616 if (setup
->wIndex
& 0xFF
1617 || udc
->gadget
.speed
!= USB_SPEED_HIGH
)
1620 if (udc
->usb_state
!= USB_STATE_CONFIGURED
1621 && udc
->usb_state
!= USB_STATE_ADDRESS
1622 && udc
->usb_state
!= USB_STATE_DEFAULT
)
1625 mv_udc_testmode(udc
, (setup
->wIndex
>> 8));
1630 } else if ((setup
->bRequestType
& (USB_TYPE_MASK
| USB_RECIP_MASK
))
1631 == ((USB_TYPE_STANDARD
| USB_RECIP_ENDPOINT
))) {
1632 switch (setup
->wValue
) {
1633 case USB_ENDPOINT_HALT
:
1634 ep_num
= setup
->wIndex
& USB_ENDPOINT_NUMBER_MASK
;
1635 direction
= (setup
->wIndex
& USB_ENDPOINT_DIR_MASK
)
1636 ? EP_DIR_IN
: EP_DIR_OUT
;
1637 if (setup
->wValue
!= 0 || setup
->wLength
!= 0
1638 || ep_num
> udc
->max_eps
)
1640 spin_unlock(&udc
->lock
);
1641 ep_set_stall(udc
, ep_num
, direction
, 1);
1642 spin_lock(&udc
->lock
);
1650 if (udc_prime_status(udc
, EP_DIR_IN
, 0, true))
1656 static void handle_setup_packet(struct mv_udc
*udc
, u8 ep_num
,
1657 struct usb_ctrlrequest
*setup
)
1658 __releases(&ep
->udc
->lock
)
1659 __acquires(&ep
->udc
->lock
)
1661 bool delegate
= false;
1663 nuke(&udc
->eps
[ep_num
* 2 + EP_DIR_OUT
], -ESHUTDOWN
);
1665 dev_dbg(&udc
->dev
->dev
, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1666 setup
->bRequestType
, setup
->bRequest
,
1667 setup
->wValue
, setup
->wIndex
, setup
->wLength
);
1668 /* We process some standard setup requests here */
1669 if ((setup
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1670 switch (setup
->bRequest
) {
1671 case USB_REQ_GET_STATUS
:
1672 ch9getstatus(udc
, ep_num
, setup
);
1675 case USB_REQ_SET_ADDRESS
:
1676 ch9setaddress(udc
, setup
);
1679 case USB_REQ_CLEAR_FEATURE
:
1680 ch9clearfeature(udc
, setup
);
1683 case USB_REQ_SET_FEATURE
:
1684 ch9setfeature(udc
, setup
);
1693 /* delegate USB standard requests to the gadget driver */
1694 if (delegate
== true) {
1695 /* USB requests handled by gadget */
1696 if (setup
->wLength
) {
1697 /* DATA phase from gadget, STATUS phase from udc */
1698 udc
->ep0_dir
= (setup
->bRequestType
& USB_DIR_IN
)
1699 ? EP_DIR_IN
: EP_DIR_OUT
;
1700 spin_unlock(&udc
->lock
);
1701 if (udc
->driver
->setup(&udc
->gadget
,
1702 &udc
->local_setup_buff
) < 0)
1704 spin_lock(&udc
->lock
);
1705 udc
->ep0_state
= (setup
->bRequestType
& USB_DIR_IN
)
1706 ? DATA_STATE_XMIT
: DATA_STATE_RECV
;
1708 /* no DATA phase, IN STATUS phase from gadget */
1709 udc
->ep0_dir
= EP_DIR_IN
;
1710 spin_unlock(&udc
->lock
);
1711 if (udc
->driver
->setup(&udc
->gadget
,
1712 &udc
->local_setup_buff
) < 0)
1714 spin_lock(&udc
->lock
);
1715 udc
->ep0_state
= WAIT_FOR_OUT_STATUS
;
1720 /* complete DATA or STATUS phase of ep0 prime status phase if needed */
1721 static void ep0_req_complete(struct mv_udc
*udc
,
1722 struct mv_ep
*ep0
, struct mv_req
*req
)
1726 if (udc
->usb_state
== USB_STATE_ADDRESS
) {
1727 /* set the new address */
1728 new_addr
= (u32
)udc
->dev_addr
;
1729 writel(new_addr
<< USB_DEVICE_ADDRESS_BIT_SHIFT
,
1730 &udc
->op_regs
->deviceaddr
);
1735 switch (udc
->ep0_state
) {
1736 case DATA_STATE_XMIT
:
1737 /* receive status phase */
1738 if (udc_prime_status(udc
, EP_DIR_OUT
, 0, true))
1741 case DATA_STATE_RECV
:
1742 /* send status phase */
1743 if (udc_prime_status(udc
, EP_DIR_IN
, 0 , true))
1746 case WAIT_FOR_OUT_STATUS
:
1747 udc
->ep0_state
= WAIT_FOR_SETUP
;
1749 case WAIT_FOR_SETUP
:
1750 dev_err(&udc
->dev
->dev
, "unexpect ep0 packets\n");
1758 static void get_setup_data(struct mv_udc
*udc
, u8 ep_num
, u8
*buffer_ptr
)
1763 dqh
= &udc
->ep_dqh
[ep_num
* 2 + EP_DIR_OUT
];
1765 /* Clear bit in ENDPTSETUPSTAT */
1766 writel((1 << ep_num
), &udc
->op_regs
->epsetupstat
);
1768 /* while a hazard exists when setup package arrives */
1770 /* Set Setup Tripwire */
1771 temp
= readl(&udc
->op_regs
->usbcmd
);
1772 writel(temp
| USBCMD_SETUP_TRIPWIRE_SET
, &udc
->op_regs
->usbcmd
);
1774 /* Copy the setup packet to local buffer */
1775 memcpy(buffer_ptr
, (u8
*) dqh
->setup_buffer
, 8);
1776 } while (!(readl(&udc
->op_regs
->usbcmd
) & USBCMD_SETUP_TRIPWIRE_SET
));
1778 /* Clear Setup Tripwire */
1779 temp
= readl(&udc
->op_regs
->usbcmd
);
1780 writel(temp
& ~USBCMD_SETUP_TRIPWIRE_SET
, &udc
->op_regs
->usbcmd
);
1783 static void irq_process_tr_complete(struct mv_udc
*udc
)
1786 int i
, ep_num
= 0, direction
= 0;
1787 struct mv_ep
*curr_ep
;
1788 struct mv_req
*curr_req
, *temp_req
;
1792 * We use separate loops for ENDPTSETUPSTAT and ENDPTCOMPLETE
1793 * because the setup packets are to be read ASAP
1796 /* Process all Setup packet received interrupts */
1797 tmp
= readl(&udc
->op_regs
->epsetupstat
);
1800 for (i
= 0; i
< udc
->max_eps
; i
++) {
1801 if (tmp
& (1 << i
)) {
1802 get_setup_data(udc
, i
,
1803 (u8
*)(&udc
->local_setup_buff
));
1804 handle_setup_packet(udc
, i
,
1805 &udc
->local_setup_buff
);
1810 /* Don't clear the endpoint setup status register here.
1811 * It is cleared as a setup packet is read out of the buffer
1814 /* Process non-setup transaction complete interrupts */
1815 tmp
= readl(&udc
->op_regs
->epcomplete
);
1820 writel(tmp
, &udc
->op_regs
->epcomplete
);
1822 for (i
= 0; i
< udc
->max_eps
* 2; i
++) {
1826 bit_pos
= 1 << (ep_num
+ 16 * direction
);
1828 if (!(bit_pos
& tmp
))
1832 curr_ep
= &udc
->eps
[0];
1834 curr_ep
= &udc
->eps
[i
];
1835 /* process the req queue until an uncomplete request */
1836 list_for_each_entry_safe(curr_req
, temp_req
,
1837 &curr_ep
->queue
, queue
) {
1838 status
= process_ep_req(udc
, i
, curr_req
);
1842 /* write back status to req */
1843 curr_req
->req
.status
= status
;
1845 /* ep0 request completion */
1847 ep0_req_complete(udc
, curr_ep
, curr_req
);
1850 done(curr_ep
, curr_req
, status
);
1856 static void irq_process_reset(struct mv_udc
*udc
)
1861 udc
->ep0_dir
= EP_DIR_OUT
;
1862 udc
->ep0_state
= WAIT_FOR_SETUP
;
1863 udc
->remote_wakeup
= 0; /* default to 0 on reset */
1865 /* The address bits are past bit 25-31. Set the address */
1866 tmp
= readl(&udc
->op_regs
->deviceaddr
);
1867 tmp
&= ~(USB_DEVICE_ADDRESS_MASK
);
1868 writel(tmp
, &udc
->op_regs
->deviceaddr
);
1870 /* Clear all the setup token semaphores */
1871 tmp
= readl(&udc
->op_regs
->epsetupstat
);
1872 writel(tmp
, &udc
->op_regs
->epsetupstat
);
1874 /* Clear all the endpoint complete status bits */
1875 tmp
= readl(&udc
->op_regs
->epcomplete
);
1876 writel(tmp
, &udc
->op_regs
->epcomplete
);
1878 /* wait until all endptprime bits cleared */
1879 loops
= LOOPS(PRIME_TIMEOUT
);
1880 while (readl(&udc
->op_regs
->epprime
) & 0xFFFFFFFF) {
1882 dev_err(&udc
->dev
->dev
,
1883 "Timeout for ENDPTPRIME = 0x%x\n",
1884 readl(&udc
->op_regs
->epprime
));
1891 /* Write 1s to the Flush register */
1892 writel((u32
)~0, &udc
->op_regs
->epflush
);
1894 if (readl(&udc
->op_regs
->portsc
[0]) & PORTSCX_PORT_RESET
) {
1895 dev_info(&udc
->dev
->dev
, "usb bus reset\n");
1896 udc
->usb_state
= USB_STATE_DEFAULT
;
1897 /* reset all the queues, stop all USB activities */
1898 gadget_reset(udc
, udc
->driver
);
1900 dev_info(&udc
->dev
->dev
, "USB reset portsc 0x%x\n",
1901 readl(&udc
->op_regs
->portsc
));
1909 /* reset all the queues, stop all USB activities */
1910 stop_activity(udc
, udc
->driver
);
1912 /* reset ep0 dQH and endptctrl */
1915 /* enable interrupt and set controller to run state */
1918 udc
->usb_state
= USB_STATE_ATTACHED
;
1922 static void handle_bus_resume(struct mv_udc
*udc
)
1924 udc
->usb_state
= udc
->resume_state
;
1925 udc
->resume_state
= 0;
1927 /* report resume to the driver */
1929 if (udc
->driver
->resume
) {
1930 spin_unlock(&udc
->lock
);
1931 udc
->driver
->resume(&udc
->gadget
);
1932 spin_lock(&udc
->lock
);
1937 static void irq_process_suspend(struct mv_udc
*udc
)
1939 udc
->resume_state
= udc
->usb_state
;
1940 udc
->usb_state
= USB_STATE_SUSPENDED
;
1942 if (udc
->driver
->suspend
) {
1943 spin_unlock(&udc
->lock
);
1944 udc
->driver
->suspend(&udc
->gadget
);
1945 spin_lock(&udc
->lock
);
1949 static void irq_process_port_change(struct mv_udc
*udc
)
1953 portsc
= readl(&udc
->op_regs
->portsc
[0]);
1954 if (!(portsc
& PORTSCX_PORT_RESET
)) {
1956 u32 speed
= portsc
& PORTSCX_PORT_SPEED_MASK
;
1958 case PORTSCX_PORT_SPEED_HIGH
:
1959 udc
->gadget
.speed
= USB_SPEED_HIGH
;
1961 case PORTSCX_PORT_SPEED_FULL
:
1962 udc
->gadget
.speed
= USB_SPEED_FULL
;
1964 case PORTSCX_PORT_SPEED_LOW
:
1965 udc
->gadget
.speed
= USB_SPEED_LOW
;
1968 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1973 if (portsc
& PORTSCX_PORT_SUSPEND
) {
1974 udc
->resume_state
= udc
->usb_state
;
1975 udc
->usb_state
= USB_STATE_SUSPENDED
;
1976 if (udc
->driver
->suspend
) {
1977 spin_unlock(&udc
->lock
);
1978 udc
->driver
->suspend(&udc
->gadget
);
1979 spin_lock(&udc
->lock
);
1983 if (!(portsc
& PORTSCX_PORT_SUSPEND
)
1984 && udc
->usb_state
== USB_STATE_SUSPENDED
) {
1985 handle_bus_resume(udc
);
1988 if (!udc
->resume_state
)
1989 udc
->usb_state
= USB_STATE_DEFAULT
;
1992 static void irq_process_error(struct mv_udc
*udc
)
1994 /* Increment the error count */
1998 static irqreturn_t
mv_udc_irq(int irq
, void *dev
)
2000 struct mv_udc
*udc
= (struct mv_udc
*)dev
;
2003 /* Disable ISR when stopped bit is set */
2007 spin_lock(&udc
->lock
);
2009 status
= readl(&udc
->op_regs
->usbsts
);
2010 intr
= readl(&udc
->op_regs
->usbintr
);
2014 spin_unlock(&udc
->lock
);
2018 /* Clear all the interrupts occurred */
2019 writel(status
, &udc
->op_regs
->usbsts
);
2021 if (status
& USBSTS_ERR
)
2022 irq_process_error(udc
);
2024 if (status
& USBSTS_RESET
)
2025 irq_process_reset(udc
);
2027 if (status
& USBSTS_PORT_CHANGE
)
2028 irq_process_port_change(udc
);
2030 if (status
& USBSTS_INT
)
2031 irq_process_tr_complete(udc
);
2033 if (status
& USBSTS_SUSPEND
)
2034 irq_process_suspend(udc
);
2036 spin_unlock(&udc
->lock
);
2041 static irqreturn_t
mv_udc_vbus_irq(int irq
, void *dev
)
2043 struct mv_udc
*udc
= (struct mv_udc
*)dev
;
2045 /* polling VBUS and init phy may cause too much time*/
2047 queue_work(udc
->qwork
, &udc
->vbus_work
);
2052 static void mv_udc_vbus_work(struct work_struct
*work
)
2057 udc
= container_of(work
, struct mv_udc
, vbus_work
);
2058 if (!udc
->pdata
->vbus
)
2061 vbus
= udc
->pdata
->vbus
->poll();
2062 dev_info(&udc
->dev
->dev
, "vbus is %d\n", vbus
);
2064 if (vbus
== VBUS_HIGH
)
2065 mv_udc_vbus_session(&udc
->gadget
, 1);
2066 else if (vbus
== VBUS_LOW
)
2067 mv_udc_vbus_session(&udc
->gadget
, 0);
2070 /* release device structure */
2071 static void gadget_release(struct device
*_dev
)
2075 udc
= dev_get_drvdata(_dev
);
2077 complete(udc
->done
);
2080 static int mv_udc_remove(struct platform_device
*pdev
)
2084 udc
= platform_get_drvdata(pdev
);
2086 usb_del_gadget_udc(&udc
->gadget
);
2089 flush_workqueue(udc
->qwork
);
2090 destroy_workqueue(udc
->qwork
);
2093 /* free memory allocated in probe */
2094 dma_pool_destroy(udc
->dtd_pool
);
2097 dma_free_coherent(&pdev
->dev
, udc
->ep_dqh_size
,
2098 udc
->ep_dqh
, udc
->ep_dqh_dma
);
2100 mv_udc_disable(udc
);
2102 /* free dev, wait for the release() finished */
2103 wait_for_completion(udc
->done
);
2108 static int mv_udc_probe(struct platform_device
*pdev
)
2110 struct mv_usb_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
2116 if (pdata
== NULL
) {
2117 dev_err(&pdev
->dev
, "missing platform_data\n");
2121 udc
= devm_kzalloc(&pdev
->dev
, sizeof(*udc
), GFP_KERNEL
);
2125 udc
->done
= &release_done
;
2126 udc
->pdata
= dev_get_platdata(&pdev
->dev
);
2127 spin_lock_init(&udc
->lock
);
2131 if (pdata
->mode
== MV_USB_MODE_OTG
) {
2132 udc
->transceiver
= devm_usb_get_phy(&pdev
->dev
,
2134 if (IS_ERR(udc
->transceiver
)) {
2135 retval
= PTR_ERR(udc
->transceiver
);
2137 if (retval
== -ENXIO
)
2140 udc
->transceiver
= NULL
;
2141 return -EPROBE_DEFER
;
2145 /* udc only have one sysclk. */
2146 udc
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
2147 if (IS_ERR(udc
->clk
))
2148 return PTR_ERR(udc
->clk
);
2150 r
= platform_get_resource_byname(udc
->dev
, IORESOURCE_MEM
, "capregs");
2152 dev_err(&pdev
->dev
, "no I/O memory resource defined\n");
2156 udc
->cap_regs
= (struct mv_cap_regs __iomem
*)
2157 devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
2158 if (udc
->cap_regs
== NULL
) {
2159 dev_err(&pdev
->dev
, "failed to map I/O memory\n");
2163 r
= platform_get_resource_byname(udc
->dev
, IORESOURCE_MEM
, "phyregs");
2165 dev_err(&pdev
->dev
, "no phy I/O memory resource defined\n");
2169 udc
->phy_regs
= devm_ioremap(&pdev
->dev
, r
->start
, resource_size(r
));
2170 if (udc
->phy_regs
== NULL
) {
2171 dev_err(&pdev
->dev
, "failed to map phy I/O memory\n");
2175 /* we will acces controller register, so enable the clk */
2176 retval
= mv_udc_enable_internal(udc
);
2181 (struct mv_op_regs __iomem
*)((unsigned long)udc
->cap_regs
2182 + (readl(&udc
->cap_regs
->caplength_hciversion
)
2184 udc
->max_eps
= readl(&udc
->cap_regs
->dccparams
) & DCCPARAMS_DEN_MASK
;
2187 * some platform will use usb to download image, it may not disconnect
2188 * usb gadget before loading kernel. So first stop udc here.
2191 writel(0xFFFFFFFF, &udc
->op_regs
->usbsts
);
2193 size
= udc
->max_eps
* sizeof(struct mv_dqh
) *2;
2194 size
= (size
+ DQH_ALIGNMENT
- 1) & ~(DQH_ALIGNMENT
- 1);
2195 udc
->ep_dqh
= dma_alloc_coherent(&pdev
->dev
, size
,
2196 &udc
->ep_dqh_dma
, GFP_KERNEL
);
2198 if (udc
->ep_dqh
== NULL
) {
2199 dev_err(&pdev
->dev
, "allocate dQH memory failed\n");
2201 goto err_disable_clock
;
2203 udc
->ep_dqh_size
= size
;
2205 /* create dTD dma_pool resource */
2206 udc
->dtd_pool
= dma_pool_create("mv_dtd",
2208 sizeof(struct mv_dtd
),
2212 if (!udc
->dtd_pool
) {
2217 size
= udc
->max_eps
* sizeof(struct mv_ep
) *2;
2218 udc
->eps
= devm_kzalloc(&pdev
->dev
, size
, GFP_KERNEL
);
2219 if (udc
->eps
== NULL
) {
2221 goto err_destroy_dma
;
2224 /* initialize ep0 status request structure */
2225 udc
->status_req
= devm_kzalloc(&pdev
->dev
, sizeof(struct mv_req
),
2227 if (!udc
->status_req
) {
2229 goto err_destroy_dma
;
2231 INIT_LIST_HEAD(&udc
->status_req
->queue
);
2233 /* allocate a small amount of memory to get valid address */
2234 udc
->status_req
->req
.buf
= kzalloc(8, GFP_KERNEL
);
2235 udc
->status_req
->req
.dma
= DMA_ADDR_INVALID
;
2237 udc
->resume_state
= USB_STATE_NOTATTACHED
;
2238 udc
->usb_state
= USB_STATE_POWERED
;
2239 udc
->ep0_dir
= EP_DIR_OUT
;
2240 udc
->remote_wakeup
= 0;
2242 r
= platform_get_resource(udc
->dev
, IORESOURCE_IRQ
, 0);
2244 dev_err(&pdev
->dev
, "no IRQ resource defined\n");
2246 goto err_destroy_dma
;
2248 udc
->irq
= r
->start
;
2249 if (devm_request_irq(&pdev
->dev
, udc
->irq
, mv_udc_irq
,
2250 IRQF_SHARED
, driver_name
, udc
)) {
2251 dev_err(&pdev
->dev
, "Request irq %d for UDC failed\n",
2254 goto err_destroy_dma
;
2257 /* initialize gadget structure */
2258 udc
->gadget
.ops
= &mv_ops
; /* usb_gadget_ops */
2259 udc
->gadget
.ep0
= &udc
->eps
[0].ep
; /* gadget ep0 */
2260 INIT_LIST_HEAD(&udc
->gadget
.ep_list
); /* ep_list */
2261 udc
->gadget
.speed
= USB_SPEED_UNKNOWN
; /* speed */
2262 udc
->gadget
.max_speed
= USB_SPEED_HIGH
; /* support dual speed */
2264 /* the "gadget" abstracts/virtualizes the controller */
2265 udc
->gadget
.name
= driver_name
; /* gadget name */
2269 /* VBUS detect: we can disable/enable clock on demand.*/
2270 if (udc
->transceiver
)
2271 udc
->clock_gating
= 1;
2272 else if (pdata
->vbus
) {
2273 udc
->clock_gating
= 1;
2274 retval
= devm_request_threaded_irq(&pdev
->dev
,
2275 pdata
->vbus
->irq
, NULL
,
2276 mv_udc_vbus_irq
, IRQF_ONESHOT
, "vbus", udc
);
2278 dev_info(&pdev
->dev
,
2279 "Can not request irq for VBUS, "
2280 "disable clock gating\n");
2281 udc
->clock_gating
= 0;
2284 udc
->qwork
= create_singlethread_workqueue("mv_udc_queue");
2286 dev_err(&pdev
->dev
, "cannot create workqueue\n");
2288 goto err_destroy_dma
;
2291 INIT_WORK(&udc
->vbus_work
, mv_udc_vbus_work
);
2295 * When clock gating is supported, we can disable clk and phy.
2296 * If not, it means that VBUS detection is not supported, we
2297 * have to enable vbus active all the time to let controller work.
2299 if (udc
->clock_gating
)
2300 mv_udc_disable_internal(udc
);
2302 udc
->vbus_active
= 1;
2304 retval
= usb_add_gadget_udc_release(&pdev
->dev
, &udc
->gadget
,
2307 goto err_create_workqueue
;
2309 platform_set_drvdata(pdev
, udc
);
2310 dev_info(&pdev
->dev
, "successful probe UDC device %s clock gating.\n",
2311 udc
->clock_gating
? "with" : "without");
2315 err_create_workqueue
:
2316 destroy_workqueue(udc
->qwork
);
2318 dma_pool_destroy(udc
->dtd_pool
);
2320 dma_free_coherent(&pdev
->dev
, udc
->ep_dqh_size
,
2321 udc
->ep_dqh
, udc
->ep_dqh_dma
);
2323 mv_udc_disable_internal(udc
);
2329 static int mv_udc_suspend(struct device
*dev
)
2333 udc
= dev_get_drvdata(dev
);
2335 /* if OTG is enabled, the following will be done in OTG driver*/
2336 if (udc
->transceiver
)
2339 if (udc
->pdata
->vbus
&& udc
->pdata
->vbus
->poll
)
2340 if (udc
->pdata
->vbus
->poll() == VBUS_HIGH
) {
2341 dev_info(&udc
->dev
->dev
, "USB cable is connected!\n");
2346 * only cable is unplugged, udc can suspend.
2347 * So do not care about clock_gating == 1.
2349 if (!udc
->clock_gating
) {
2352 spin_lock_irq(&udc
->lock
);
2353 /* stop all usb activities */
2354 stop_activity(udc
, udc
->driver
);
2355 spin_unlock_irq(&udc
->lock
);
2357 mv_udc_disable_internal(udc
);
2363 static int mv_udc_resume(struct device
*dev
)
2368 udc
= dev_get_drvdata(dev
);
2370 /* if OTG is enabled, the following will be done in OTG driver*/
2371 if (udc
->transceiver
)
2374 if (!udc
->clock_gating
) {
2375 retval
= mv_udc_enable_internal(udc
);
2379 if (udc
->driver
&& udc
->softconnect
) {
2389 static const struct dev_pm_ops mv_udc_pm_ops
= {
2390 .suspend
= mv_udc_suspend
,
2391 .resume
= mv_udc_resume
,
2395 static void mv_udc_shutdown(struct platform_device
*pdev
)
2400 udc
= platform_get_drvdata(pdev
);
2401 /* reset controller mode to IDLE */
2403 mode
= readl(&udc
->op_regs
->usbmode
);
2405 writel(mode
, &udc
->op_regs
->usbmode
);
2406 mv_udc_disable(udc
);
2409 static struct platform_driver udc_driver
= {
2410 .probe
= mv_udc_probe
,
2411 .remove
= mv_udc_remove
,
2412 .shutdown
= mv_udc_shutdown
,
2416 .pm
= &mv_udc_pm_ops
,
2421 module_platform_driver(udc_driver
);
2422 MODULE_ALIAS("platform:mv-udc");
2423 MODULE_DESCRIPTION(DRIVER_DESC
);
2424 MODULE_AUTHOR("Chao Xie <chao.xie@marvell.com>");
2425 MODULE_LICENSE("GPL");