drivers/gpio/gpio-ath79.c

   1 /*
   2  *  Atheros AR71XX/AR724X/AR913X GPIO API support
   3  *
   4  *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>
   5  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   6  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
   7  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/gpio/driver.h>
  15 #include <linux/platform_data/gpio-ath79.h>
  16 #include <linux/of_device.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/module.h>
  19 #include <linux/irq.h>
  20
  21 #define AR71XX_GPIO_REG_OE              0x00
  22 #define AR71XX_GPIO_REG_IN              0x04
  23 #define AR71XX_GPIO_REG_SET             0x0c
  24 #define AR71XX_GPIO_REG_CLEAR           0x10
  25
  26 #define AR71XX_GPIO_REG_INT_ENABLE      0x14
  27 #define AR71XX_GPIO_REG_INT_TYPE        0x18
  28 #define AR71XX_GPIO_REG_INT_POLARITY    0x1c
  29 #define AR71XX_GPIO_REG_INT_PENDING     0x20
  30 #define AR71XX_GPIO_REG_INT_MASK        0x24
  31
  32 struct ath79_gpio_ctrl {
  33         struct gpio_chip gc;
  34         void __iomem *base;
  35         raw_spinlock_t lock;
  36         unsigned long both_edges;
  37 };
  38
  39 static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
  40 {
  41         struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
  42
  43         return container_of(gc, struct ath79_gpio_ctrl, gc);
  44 }
  45
  46 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
  47 {
  48         return readl(ctrl->base + reg);
  49 }
  50
  51 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
  52                         unsigned reg, u32 val)
  53 {
  54         return writel(val, ctrl->base + reg);
  55 }
  56
  57 static bool ath79_gpio_update_bits(
  58         struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
  59 {
  60         u32 old_val, new_val;
  61
  62         old_val = ath79_gpio_read(ctrl, reg);
  63         new_val = (old_val & ~mask) | (bits & mask);
  64
  65         if (new_val != old_val)
  66                 ath79_gpio_write(ctrl, reg, new_val);
  67
  68         return new_val != old_val;
  69 }
  70
  71 static void ath79_gpio_irq_unmask(struct irq_data *data)
  72 {
  73         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  74         u32 mask = BIT(irqd_to_hwirq(data));
  75         unsigned long flags;
  76
  77         raw_spin_lock_irqsave(&ctrl->lock, flags);
  78         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
  79         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  80 }
  81
  82 static void ath79_gpio_irq_mask(struct irq_data *data)
  83 {
  84         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  85         u32 mask = BIT(irqd_to_hwirq(data));
  86         unsigned long flags;
  87
  88         raw_spin_lock_irqsave(&ctrl->lock, flags);
  89         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
  90         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
  91 }
  92
  93 static void ath79_gpio_irq_enable(struct irq_data *data)
  94 {
  95         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
  96         u32 mask = BIT(irqd_to_hwirq(data));
  97         unsigned long flags;
  98
  99         raw_spin_lock_irqsave(&ctrl->lock, flags);
 100         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
 101         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
 102         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 103 }
 104
 105 static void ath79_gpio_irq_disable(struct irq_data *data)
 106 {
 107         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
 108         u32 mask = BIT(irqd_to_hwirq(data));
 109         unsigned long flags;
 110
 111         raw_spin_lock_irqsave(&ctrl->lock, flags);
 112         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
 113         ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
 114         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 115 }
 116
 117 static int ath79_gpio_irq_set_type(struct irq_data *data,
 118                                 unsigned int flow_type)
 119 {
 120         struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
 121         u32 mask = BIT(irqd_to_hwirq(data));
 122         u32 type = 0, polarity = 0;
 123         unsigned long flags;
 124         bool disabled;
 125
 126         switch (flow_type) {
 127         case IRQ_TYPE_EDGE_RISING:
 128                 polarity |= mask;
 129         case IRQ_TYPE_EDGE_FALLING:
 130         case IRQ_TYPE_EDGE_BOTH:
 131                 break;
 132
 133         case IRQ_TYPE_LEVEL_HIGH:
 134                 polarity |= mask;
 135         case IRQ_TYPE_LEVEL_LOW:
 136                 type |= mask;
 137                 break;
 138
 139         default:
 140                 return -EINVAL;
 141         }
 142
 143         raw_spin_lock_irqsave(&ctrl->lock, flags);
 144
 145         if (flow_type == IRQ_TYPE_EDGE_BOTH) {
 146                 ctrl->both_edges |= mask;
 147                 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
 148         } else {
 149                 ctrl->both_edges &= ~mask;
 150         }
 151
 152         /* As the IRQ configuration can't be loaded atomically we
 153          * have to disable the interrupt while the configuration state
 154          * is invalid.
 155          */
 156         disabled = ath79_gpio_update_bits(
 157                 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
 158
 159         ath79_gpio_update_bits(
 160                 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
 161         ath79_gpio_update_bits(
 162                 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
 163
 164         if (disabled)
 165                 ath79_gpio_update_bits(
 166                         ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
 167
 168         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 169
 170         return 0;
 171 }
 172
 173 static struct irq_chip ath79_gpio_irqchip = {
 174         .name = "gpio-ath79",
 175         .irq_enable = ath79_gpio_irq_enable,
 176         .irq_disable = ath79_gpio_irq_disable,
 177         .irq_mask = ath79_gpio_irq_mask,
 178         .irq_unmask = ath79_gpio_irq_unmask,
 179         .irq_set_type = ath79_gpio_irq_set_type,
 180 };
 181
 182 static void ath79_gpio_irq_handler(struct irq_desc *desc)
 183 {
 184         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 185         struct irq_chip *irqchip = irq_desc_get_chip(desc);
 186         struct ath79_gpio_ctrl *ctrl =
 187                 container_of(gc, struct ath79_gpio_ctrl, gc);
 188         unsigned long flags, pending;
 189         u32 both_edges, state;
 190         int irq;
 191
 192         chained_irq_enter(irqchip, desc);
 193
 194         raw_spin_lock_irqsave(&ctrl->lock, flags);
 195
 196         pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
 197
 198         /* Update the polarity of the both edges irqs */
 199         both_edges = ctrl->both_edges & pending;
 200         if (both_edges) {
 201                 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
 202                 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
 203                                 both_edges, ~state);
 204         }
 205
 206         raw_spin_unlock_irqrestore(&ctrl->lock, flags);
 207
 208         if (pending) {
 209                 for_each_set_bit(irq, &pending, gc->ngpio)
 210                         generic_handle_irq(
 211                                 irq_linear_revmap(gc->irqdomain, irq));
 212         }
 213
 214         chained_irq_exit(irqchip, desc);
 215 }
 216
 217 static const struct of_device_id ath79_gpio_of_match[] = {
 218         { .compatible = "qca,ar7100-gpio" },
 219         { .compatible = "qca,ar9340-gpio" },
 220         {},
 221 };
 222 MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
 223
 224 static int ath79_gpio_probe(struct platform_device *pdev)
 225 {
 226         struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
 227         struct device_node *np = pdev->dev.of_node;
 228         struct ath79_gpio_ctrl *ctrl;
 229         struct resource *res;
 230         u32 ath79_gpio_count;
 231         bool oe_inverted;
 232         int err;
 233
 234         ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
 235         if (!ctrl)
 236                 return -ENOMEM;
 237         platform_set_drvdata(pdev, ctrl);
 238
 239         if (np) {
 240                 err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
 241                 if (err) {
 242                         dev_err(&pdev->dev, "ngpios property is not valid\n");
 243                         return err;
 244                 }
 245                 oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
 246         } else if (pdata) {
 247                 ath79_gpio_count = pdata->ngpios;
 248                 oe_inverted = pdata->oe_inverted;
 249         } else {
 250                 dev_err(&pdev->dev, "No DT node or platform data found\n");
 251                 return -EINVAL;
 252         }
 253
 254         if (ath79_gpio_count >= 32) {
 255                 dev_err(&pdev->dev, "ngpios must be less than 32\n");
 256                 return -EINVAL;
 257         }
 258
 259         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 260         ctrl->base = devm_ioremap_nocache(
 261                 &pdev->dev, res->start, resource_size(res));
 262         if (!ctrl->base)
 263                 return -ENOMEM;
 264
 265         raw_spin_lock_init(&ctrl->lock);
 266         err = bgpio_init(&ctrl->gc, &pdev->dev, 4,
 267                         ctrl->base + AR71XX_GPIO_REG_IN,
 268                         ctrl->base + AR71XX_GPIO_REG_SET,
 269                         ctrl->base + AR71XX_GPIO_REG_CLEAR,
 270                         oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
 271                         oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
 272                         0);
 273         if (err) {
 274                 dev_err(&pdev->dev, "bgpio_init failed\n");
 275                 return err;
 276         }
 277         /* Use base 0 to stay compatible with legacy platforms */
 278         ctrl->gc.base = 0;
 279
 280         err = gpiochip_add_data(&ctrl->gc, ctrl);
 281         if (err) {
 282                 dev_err(&pdev->dev,
 283                         "cannot add AR71xx GPIO chip, error=%d", err);
 284                 return err;
 285         }
 286
 287         if (np && !of_property_read_bool(np, "interrupt-controller"))
 288                 return 0;
 289
 290         err = gpiochip_irqchip_add(&ctrl->gc, &ath79_gpio_irqchip, 0,
 291                                 handle_simple_irq, IRQ_TYPE_NONE);
 292         if (err) {
 293                 dev_err(&pdev->dev, "failed to add gpiochip_irqchip\n");
 294                 goto gpiochip_remove;
 295         }
 296
 297         gpiochip_set_chained_irqchip(&ctrl->gc, &ath79_gpio_irqchip,
 298                                 platform_get_irq(pdev, 0),
 299                                 ath79_gpio_irq_handler);
 300
 301         return 0;
 302
 303 gpiochip_remove:
 304         gpiochip_remove(&ctrl->gc);
 305         return err;
 306 }
 307
 308 static int ath79_gpio_remove(struct platform_device *pdev)
 309 {
 310         struct ath79_gpio_ctrl *ctrl = platform_get_drvdata(pdev);
 311
 312         gpiochip_remove(&ctrl->gc);
 313         return 0;
 314 }
 315
 316 static struct platform_driver ath79_gpio_driver = {
 317         .driver = {
 318                 .name = "ath79-gpio",
 319                 .of_match_table = ath79_gpio_of_match,
 320         },
 321         .probe = ath79_gpio_probe,
 322         .remove = ath79_gpio_remove,
 323 };
 324
 325 module_platform_driver(ath79_gpio_driver);