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dm kcopyd: avoid pointless job splitting
[linux/fpc-iii.git] / drivers / usb / musb / musb_core.c
blobab8e1001e5e288ae9fd06417567cc62b4d4897f5
1 /*
2 * MUSB OTG driver core code
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
20 * 02110-1301 USA
21 *
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 */
34
35 /*
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
37 *
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
42 *
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
47 *
48 *
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
53 *
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
56 *
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
61 *
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
66 * each direction.
67 *
68 * RESULT: one device may be perceived as blocking another one.
69 *
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
74 *
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
80 */
81
82 /*
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
88 *
89 * Most of the conditional compilation will (someday) vanish.
90 */
91
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
101
102 #include "musb_core.h"
103
104 #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
105
106
107 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
108 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
109
110 #define MUSB_VERSION "6.0"
111
112 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
113
114 #define MUSB_DRIVER_NAME "musb-hdrc"
115 const char musb_driver_name[] = MUSB_DRIVER_NAME;
116
117 MODULE_DESCRIPTION(DRIVER_INFO);
118 MODULE_AUTHOR(DRIVER_AUTHOR);
119 MODULE_LICENSE("GPL");
120 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
121
122
123 /*-------------------------------------------------------------------------*/
124
125 static inline struct musb *dev_to_musb(struct device *dev)
126 {
127 return dev_get_drvdata(dev);
128 }
129
130 /*-------------------------------------------------------------------------*/
131
132 #ifndef CONFIG_BLACKFIN
133 static int musb_ulpi_read(struct otg_transceiver *otg, u32 offset)
134 {
135 void __iomem *addr = otg->io_priv;
136 int i = 0;
137 u8 r;
138 u8 power;
139
140 /* Make sure the transceiver is not in low power mode */
141 power = musb_readb(addr, MUSB_POWER);
142 power &= ~MUSB_POWER_SUSPENDM;
143 musb_writeb(addr, MUSB_POWER, power);
144
145 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
146 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
147 */
148
149 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
150 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
151 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
152
153 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
154 & MUSB_ULPI_REG_CMPLT)) {
155 i++;
156 if (i == 10000)
157 return -ETIMEDOUT;
158
159 }
160 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
161 r &= ~MUSB_ULPI_REG_CMPLT;
162 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
163
164 return musb_readb(addr, MUSB_ULPI_REG_DATA);
165 }
166
167 static int musb_ulpi_write(struct otg_transceiver *otg,
168 u32 offset, u32 data)
169 {
170 void __iomem *addr = otg->io_priv;
171 int i = 0;
172 u8 r = 0;
173 u8 power;
174
175 /* Make sure the transceiver is not in low power mode */
176 power = musb_readb(addr, MUSB_POWER);
177 power &= ~MUSB_POWER_SUSPENDM;
178 musb_writeb(addr, MUSB_POWER, power);
179
180 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
181 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
182 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
183
184 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
185 & MUSB_ULPI_REG_CMPLT)) {
186 i++;
187 if (i == 10000)
188 return -ETIMEDOUT;
189 }
190
191 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
192 r &= ~MUSB_ULPI_REG_CMPLT;
193 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
194
195 return 0;
196 }
197 #else
198 #define musb_ulpi_read NULL
199 #define musb_ulpi_write NULL
200 #endif
201
202 static struct otg_io_access_ops musb_ulpi_access = {
203 .read = musb_ulpi_read,
204 .write = musb_ulpi_write,
205 };
206
207 /*-------------------------------------------------------------------------*/
208
209 #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
210
211 /*
212 * Load an endpoint's FIFO
213 */
214 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
215 {
216 struct musb *musb = hw_ep->musb;
217 void __iomem *fifo = hw_ep->fifo;
218
219 prefetch((u8 *)src);
220
221 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
222 'T', hw_ep->epnum, fifo, len, src);
223
224 /* we can't assume unaligned reads work */
225 if (likely((0x01 & (unsigned long) src) == 0)) {
226 u16 index = 0;
227
228 /* best case is 32bit-aligned source address */
229 if ((0x02 & (unsigned long) src) == 0) {
230 if (len >= 4) {
231 writesl(fifo, src + index, len >> 2);
232 index += len & ~0x03;
233 }
234 if (len & 0x02) {
235 musb_writew(fifo, 0, *(u16 *)&src[index]);
236 index += 2;
237 }
238 } else {
239 if (len >= 2) {
240 writesw(fifo, src + index, len >> 1);
241 index += len & ~0x01;
242 }
243 }
244 if (len & 0x01)
245 musb_writeb(fifo, 0, src[index]);
246 } else {
247 /* byte aligned */
248 writesb(fifo, src, len);
249 }
250 }
251
252 #if !defined(CONFIG_USB_MUSB_AM35X)
253 /*
254 * Unload an endpoint's FIFO
255 */
256 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
257 {
258 struct musb *musb = hw_ep->musb;
259 void __iomem *fifo = hw_ep->fifo;
260
261 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
262 'R', hw_ep->epnum, fifo, len, dst);
263
264 /* we can't assume unaligned writes work */
265 if (likely((0x01 & (unsigned long) dst) == 0)) {
266 u16 index = 0;
267
268 /* best case is 32bit-aligned destination address */
269 if ((0x02 & (unsigned long) dst) == 0) {
270 if (len >= 4) {
271 readsl(fifo, dst, len >> 2);
272 index = len & ~0x03;
273 }
274 if (len & 0x02) {
275 *(u16 *)&dst[index] = musb_readw(fifo, 0);
276 index += 2;
277 }
278 } else {
279 if (len >= 2) {
280 readsw(fifo, dst, len >> 1);
281 index = len & ~0x01;
282 }
283 }
284 if (len & 0x01)
285 dst[index] = musb_readb(fifo, 0);
286 } else {
287 /* byte aligned */
288 readsb(fifo, dst, len);
289 }
290 }
291 #endif
292
293 #endif /* normal PIO */
294
295
296 /*-------------------------------------------------------------------------*/
297
298 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
299 static const u8 musb_test_packet[53] = {
300 /* implicit SYNC then DATA0 to start */
301
302 /* JKJKJKJK x9 */
303 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
304 /* JJKKJJKK x8 */
305 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
306 /* JJJJKKKK x8 */
307 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
308 /* JJJJJJJKKKKKKK x8 */
309 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
310 /* JJJJJJJK x8 */
311 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
312 /* JKKKKKKK x10, JK */
313 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
314
315 /* implicit CRC16 then EOP to end */
316 };
317
318 void musb_load_testpacket(struct musb *musb)
319 {
320 void __iomem *regs = musb->endpoints[0].regs;
321
322 musb_ep_select(musb->mregs, 0);
323 musb_write_fifo(musb->control_ep,
324 sizeof(musb_test_packet), musb_test_packet);
325 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
326 }
327
328 /*-------------------------------------------------------------------------*/
329
330 #ifdef CONFIG_USB_MUSB_OTG
331
332 /*
333 * Handles OTG hnp timeouts, such as b_ase0_brst
334 */
335 void musb_otg_timer_func(unsigned long data)
336 {
337 struct musb *musb = (struct musb *)data;
338 unsigned long flags;
339
340 spin_lock_irqsave(&musb->lock, flags);
341 switch (musb->xceiv->state) {
342 case OTG_STATE_B_WAIT_ACON:
343 dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
344 musb_g_disconnect(musb);
345 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
346 musb->is_active = 0;
347 break;
348 case OTG_STATE_A_SUSPEND:
349 case OTG_STATE_A_WAIT_BCON:
350 dev_dbg(musb->controller, "HNP: %s timeout\n",
351 otg_state_string(musb->xceiv->state));
352 musb_platform_set_vbus(musb, 0);
353 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
354 break;
355 default:
356 dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
357 otg_state_string(musb->xceiv->state));
358 }
359 musb->ignore_disconnect = 0;
360 spin_unlock_irqrestore(&musb->lock, flags);
361 }
362
363 /*
364 * Stops the HNP transition. Caller must take care of locking.
365 */
366 void musb_hnp_stop(struct musb *musb)
367 {
368 struct usb_hcd *hcd = musb_to_hcd(musb);
369 void __iomem *mbase = musb->mregs;
370 u8 reg;
371
372 dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
373
374 switch (musb->xceiv->state) {
375 case OTG_STATE_A_PERIPHERAL:
376 musb_g_disconnect(musb);
377 dev_dbg(musb->controller, "HNP: back to %s\n",
378 otg_state_string(musb->xceiv->state));
379 break;
380 case OTG_STATE_B_HOST:
381 dev_dbg(musb->controller, "HNP: Disabling HR\n");
382 hcd->self.is_b_host = 0;
383 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
384 MUSB_DEV_MODE(musb);
385 reg = musb_readb(mbase, MUSB_POWER);
386 reg |= MUSB_POWER_SUSPENDM;
387 musb_writeb(mbase, MUSB_POWER, reg);
388 /* REVISIT: Start SESSION_REQUEST here? */
389 break;
390 default:
391 dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
392 otg_state_string(musb->xceiv->state));
393 }
394
395 /*
396 * When returning to A state after HNP, avoid hub_port_rebounce(),
397 * which cause occasional OPT A "Did not receive reset after connect"
398 * errors.
399 */
400 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
401 }
402
403 #endif
404
405 /*
406 * Interrupt Service Routine to record USB "global" interrupts.
407 * Since these do not happen often and signify things of
408 * paramount importance, it seems OK to check them individually;
409 * the order of the tests is specified in the manual
410 *
411 * @param musb instance pointer
412 * @param int_usb register contents
413 * @param devctl
414 * @param power
415 */
416
417 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
418 u8 devctl, u8 power)
419 {
420 irqreturn_t handled = IRQ_NONE;
421
422 dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
423 int_usb);
424
425 /* in host mode, the peripheral may issue remote wakeup.
426 * in peripheral mode, the host may resume the link.
427 * spurious RESUME irqs happen too, paired with SUSPEND.
428 */
429 if (int_usb & MUSB_INTR_RESUME) {
430 handled = IRQ_HANDLED;
431 dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
432
433 if (devctl & MUSB_DEVCTL_HM) {
434 #ifdef CONFIG_USB_MUSB_HDRC_HCD
435 void __iomem *mbase = musb->mregs;
436
437 switch (musb->xceiv->state) {
438 case OTG_STATE_A_SUSPEND:
439 /* remote wakeup? later, GetPortStatus
440 * will stop RESUME signaling
441 */
442
443 if (power & MUSB_POWER_SUSPENDM) {
444 /* spurious */
445 musb->int_usb &= ~MUSB_INTR_SUSPEND;
446 dev_dbg(musb->controller, "Spurious SUSPENDM\n");
447 break;
448 }
449
450 power &= ~MUSB_POWER_SUSPENDM;
451 musb_writeb(mbase, MUSB_POWER,
452 power | MUSB_POWER_RESUME);
453
454 musb->port1_status |=
455 (USB_PORT_STAT_C_SUSPEND << 16)
456 | MUSB_PORT_STAT_RESUME;
457 musb->rh_timer = jiffies
458 + msecs_to_jiffies(20);
459
460 musb->xceiv->state = OTG_STATE_A_HOST;
461 musb->is_active = 1;
462 usb_hcd_resume_root_hub(musb_to_hcd(musb));
463 break;
464 case OTG_STATE_B_WAIT_ACON:
465 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
466 musb->is_active = 1;
467 MUSB_DEV_MODE(musb);
468 break;
469 default:
470 WARNING("bogus %s RESUME (%s)\n",
471 "host",
472 otg_state_string(musb->xceiv->state));
473 }
474 #endif
475 } else {
476 switch (musb->xceiv->state) {
477 #ifdef CONFIG_USB_MUSB_HDRC_HCD
478 case OTG_STATE_A_SUSPEND:
479 /* possibly DISCONNECT is upcoming */
480 musb->xceiv->state = OTG_STATE_A_HOST;
481 usb_hcd_resume_root_hub(musb_to_hcd(musb));
482 break;
483 #endif
484 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
485 case OTG_STATE_B_WAIT_ACON:
486 case OTG_STATE_B_PERIPHERAL:
487 /* disconnect while suspended? we may
488 * not get a disconnect irq...
489 */
490 if ((devctl & MUSB_DEVCTL_VBUS)
491 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
492 ) {
493 musb->int_usb |= MUSB_INTR_DISCONNECT;
494 musb->int_usb &= ~MUSB_INTR_SUSPEND;
495 break;
496 }
497 musb_g_resume(musb);
498 break;
499 case OTG_STATE_B_IDLE:
500 musb->int_usb &= ~MUSB_INTR_SUSPEND;
501 break;
502 #endif
503 default:
504 WARNING("bogus %s RESUME (%s)\n",
505 "peripheral",
506 otg_state_string(musb->xceiv->state));
507 }
508 }
509 }
510
511 #ifdef CONFIG_USB_MUSB_HDRC_HCD
512 /* see manual for the order of the tests */
513 if (int_usb & MUSB_INTR_SESSREQ) {
514 void __iomem *mbase = musb->mregs;
515
516 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
517 && (devctl & MUSB_DEVCTL_BDEVICE)) {
518 dev_dbg(musb->controller, "SessReq while on B state\n");
519 return IRQ_HANDLED;
520 }
521
522 dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
523 otg_state_string(musb->xceiv->state));
524
525 /* IRQ arrives from ID pin sense or (later, if VBUS power
526 * is removed) SRP. responses are time critical:
527 * - turn on VBUS (with silicon-specific mechanism)
528 * - go through A_WAIT_VRISE
529 * - ... to A_WAIT_BCON.
530 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
531 */
532 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
533 musb->ep0_stage = MUSB_EP0_START;
534 musb->xceiv->state = OTG_STATE_A_IDLE;
535 MUSB_HST_MODE(musb);
536 musb_platform_set_vbus(musb, 1);
537
538 handled = IRQ_HANDLED;
539 }
540
541 if (int_usb & MUSB_INTR_VBUSERROR) {
542 int ignore = 0;
543
544 /* During connection as an A-Device, we may see a short
545 * current spikes causing voltage drop, because of cable
546 * and peripheral capacitance combined with vbus draw.
547 * (So: less common with truly self-powered devices, where
548 * vbus doesn't act like a power supply.)
549 *
550 * Such spikes are short; usually less than ~500 usec, max
551 * of ~2 msec. That is, they're not sustained overcurrent
552 * errors, though they're reported using VBUSERROR irqs.
553 *
554 * Workarounds: (a) hardware: use self powered devices.
555 * (b) software: ignore non-repeated VBUS errors.
556 *
557 * REVISIT: do delays from lots of DEBUG_KERNEL checks
558 * make trouble here, keeping VBUS < 4.4V ?
559 */
560 switch (musb->xceiv->state) {
561 case OTG_STATE_A_HOST:
562 /* recovery is dicey once we've gotten past the
563 * initial stages of enumeration, but if VBUS
564 * stayed ok at the other end of the link, and
565 * another reset is due (at least for high speed,
566 * to redo the chirp etc), it might work OK...
567 */
568 case OTG_STATE_A_WAIT_BCON:
569 case OTG_STATE_A_WAIT_VRISE:
570 if (musb->vbuserr_retry) {
571 void __iomem *mbase = musb->mregs;
572
573 musb->vbuserr_retry--;
574 ignore = 1;
575 devctl |= MUSB_DEVCTL_SESSION;
576 musb_writeb(mbase, MUSB_DEVCTL, devctl);
577 } else {
578 musb->port1_status |=
579 USB_PORT_STAT_OVERCURRENT
580 | (USB_PORT_STAT_C_OVERCURRENT << 16);
581 }
582 break;
583 default:
584 break;
585 }
586
587 dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
588 otg_state_string(musb->xceiv->state),
589 devctl,
590 ({ char *s;
591 switch (devctl & MUSB_DEVCTL_VBUS) {
592 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
593 s = "<SessEnd"; break;
594 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
595 s = "<AValid"; break;
596 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
597 s = "<VBusValid"; break;
598 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
599 default:
600 s = "VALID"; break;
601 }; s; }),
602 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
603 musb->port1_status);
604
605 /* go through A_WAIT_VFALL then start a new session */
606 if (!ignore)
607 musb_platform_set_vbus(musb, 0);
608 handled = IRQ_HANDLED;
609 }
610
611 #endif
612 if (int_usb & MUSB_INTR_SUSPEND) {
613 dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
614 otg_state_string(musb->xceiv->state), devctl, power);
615 handled = IRQ_HANDLED;
616
617 switch (musb->xceiv->state) {
618 #ifdef CONFIG_USB_MUSB_OTG
619 case OTG_STATE_A_PERIPHERAL:
620 /* We also come here if the cable is removed, since
621 * this silicon doesn't report ID-no-longer-grounded.
622 *
623 * We depend on T(a_wait_bcon) to shut us down, and
624 * hope users don't do anything dicey during this
625 * undesired detour through A_WAIT_BCON.
626 */
627 musb_hnp_stop(musb);
628 usb_hcd_resume_root_hub(musb_to_hcd(musb));
629 musb_root_disconnect(musb);
630 musb_platform_try_idle(musb, jiffies
631 + msecs_to_jiffies(musb->a_wait_bcon
632 ? : OTG_TIME_A_WAIT_BCON));
633
634 break;
635 #endif
636 case OTG_STATE_B_IDLE:
637 if (!musb->is_active)
638 break;
639 case OTG_STATE_B_PERIPHERAL:
640 musb_g_suspend(musb);
641 musb->is_active = is_otg_enabled(musb)
642 && musb->xceiv->gadget->b_hnp_enable;
643 if (musb->is_active) {
644 #ifdef CONFIG_USB_MUSB_OTG
645 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
646 dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
647 mod_timer(&musb->otg_timer, jiffies
648 + msecs_to_jiffies(
649 OTG_TIME_B_ASE0_BRST));
650 #endif
651 }
652 break;
653 case OTG_STATE_A_WAIT_BCON:
654 if (musb->a_wait_bcon != 0)
655 musb_platform_try_idle(musb, jiffies
656 + msecs_to_jiffies(musb->a_wait_bcon));
657 break;
658 case OTG_STATE_A_HOST:
659 musb->xceiv->state = OTG_STATE_A_SUSPEND;
660 musb->is_active = is_otg_enabled(musb)
661 && musb->xceiv->host->b_hnp_enable;
662 break;
663 case OTG_STATE_B_HOST:
664 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
665 dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
666 break;
667 default:
668 /* "should not happen" */
669 musb->is_active = 0;
670 break;
671 }
672 }
673
674 #ifdef CONFIG_USB_MUSB_HDRC_HCD
675 if (int_usb & MUSB_INTR_CONNECT) {
676 struct usb_hcd *hcd = musb_to_hcd(musb);
677
678 handled = IRQ_HANDLED;
679 musb->is_active = 1;
680 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
681
682 musb->ep0_stage = MUSB_EP0_START;
683
684 #ifdef CONFIG_USB_MUSB_OTG
685 /* flush endpoints when transitioning from Device Mode */
686 if (is_peripheral_active(musb)) {
687 /* REVISIT HNP; just force disconnect */
688 }
689 musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
690 musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
691 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
692 #endif
693 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
694 |USB_PORT_STAT_HIGH_SPEED
695 |USB_PORT_STAT_ENABLE
696 );
697 musb->port1_status |= USB_PORT_STAT_CONNECTION
698 |(USB_PORT_STAT_C_CONNECTION << 16);
699
700 /* high vs full speed is just a guess until after reset */
701 if (devctl & MUSB_DEVCTL_LSDEV)
702 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
703
704 /* indicate new connection to OTG machine */
705 switch (musb->xceiv->state) {
706 case OTG_STATE_B_PERIPHERAL:
707 if (int_usb & MUSB_INTR_SUSPEND) {
708 dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
709 int_usb &= ~MUSB_INTR_SUSPEND;
710 goto b_host;
711 } else
712 dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
713 break;
714 case OTG_STATE_B_WAIT_ACON:
715 dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
716 b_host:
717 musb->xceiv->state = OTG_STATE_B_HOST;
718 hcd->self.is_b_host = 1;
719 musb->ignore_disconnect = 0;
720 del_timer(&musb->otg_timer);
721 break;
722 default:
723 if ((devctl & MUSB_DEVCTL_VBUS)
724 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
725 musb->xceiv->state = OTG_STATE_A_HOST;
726 hcd->self.is_b_host = 0;
727 }
728 break;
729 }
730
731 /* poke the root hub */
732 MUSB_HST_MODE(musb);
733 if (hcd->status_urb)
734 usb_hcd_poll_rh_status(hcd);
735 else
736 usb_hcd_resume_root_hub(hcd);
737
738 dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
739 otg_state_string(musb->xceiv->state), devctl);
740 }
741 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
742
743 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
744 dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
745 otg_state_string(musb->xceiv->state),
746 MUSB_MODE(musb), devctl);
747 handled = IRQ_HANDLED;
748
749 switch (musb->xceiv->state) {
750 #ifdef CONFIG_USB_MUSB_HDRC_HCD
751 case OTG_STATE_A_HOST:
752 case OTG_STATE_A_SUSPEND:
753 usb_hcd_resume_root_hub(musb_to_hcd(musb));
754 musb_root_disconnect(musb);
755 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
756 musb_platform_try_idle(musb, jiffies
757 + msecs_to_jiffies(musb->a_wait_bcon));
758 break;
759 #endif /* HOST */
760 #ifdef CONFIG_USB_MUSB_OTG
761 case OTG_STATE_B_HOST:
762 /* REVISIT this behaves for "real disconnect"
763 * cases; make sure the other transitions from
764 * from B_HOST act right too. The B_HOST code
765 * in hnp_stop() is currently not used...
766 */
767 musb_root_disconnect(musb);
768 musb_to_hcd(musb)->self.is_b_host = 0;
769 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
770 MUSB_DEV_MODE(musb);
771 musb_g_disconnect(musb);
772 break;
773 case OTG_STATE_A_PERIPHERAL:
774 musb_hnp_stop(musb);
775 musb_root_disconnect(musb);
776 /* FALLTHROUGH */
777 case OTG_STATE_B_WAIT_ACON:
778 /* FALLTHROUGH */
779 #endif /* OTG */
780 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
781 case OTG_STATE_B_PERIPHERAL:
782 case OTG_STATE_B_IDLE:
783 musb_g_disconnect(musb);
784 break;
785 #endif /* GADGET */
786 default:
787 WARNING("unhandled DISCONNECT transition (%s)\n",
788 otg_state_string(musb->xceiv->state));
789 break;
790 }
791 }
792
793 /* mentor saves a bit: bus reset and babble share the same irq.
794 * only host sees babble; only peripheral sees bus reset.
795 */
796 if (int_usb & MUSB_INTR_RESET) {
797 handled = IRQ_HANDLED;
798 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
799 /*
800 * Looks like non-HS BABBLE can be ignored, but
801 * HS BABBLE is an error condition. For HS the solution
802 * is to avoid babble in the first place and fix what
803 * caused BABBLE. When HS BABBLE happens we can only
804 * stop the session.
805 */
806 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
807 dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
808 else {
809 ERR("Stopping host session -- babble\n");
810 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
811 }
812 } else if (is_peripheral_capable()) {
813 dev_dbg(musb->controller, "BUS RESET as %s\n",
814 otg_state_string(musb->xceiv->state));
815 switch (musb->xceiv->state) {
816 #ifdef CONFIG_USB_OTG
817 case OTG_STATE_A_SUSPEND:
818 /* We need to ignore disconnect on suspend
819 * otherwise tusb 2.0 won't reconnect after a
820 * power cycle, which breaks otg compliance.
821 */
822 musb->ignore_disconnect = 1;
823 musb_g_reset(musb);
824 /* FALLTHROUGH */
825 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
826 /* never use invalid T(a_wait_bcon) */
827 dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
828 otg_state_string(musb->xceiv->state),
829 TA_WAIT_BCON(musb));
830 mod_timer(&musb->otg_timer, jiffies
831 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
832 break;
833 case OTG_STATE_A_PERIPHERAL:
834 musb->ignore_disconnect = 0;
835 del_timer(&musb->otg_timer);
836 musb_g_reset(musb);
837 break;
838 case OTG_STATE_B_WAIT_ACON:
839 dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
840 otg_state_string(musb->xceiv->state));
841 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
842 musb_g_reset(musb);
843 break;
844 #endif
845 case OTG_STATE_B_IDLE:
846 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
847 /* FALLTHROUGH */
848 case OTG_STATE_B_PERIPHERAL:
849 musb_g_reset(musb);
850 break;
851 default:
852 dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
853 otg_state_string(musb->xceiv->state));
854 }
855 }
856 }
857
858 #if 0
859 /* REVISIT ... this would be for multiplexing periodic endpoints, or
860 * supporting transfer phasing to prevent exceeding ISO bandwidth
861 * limits of a given frame or microframe.
862 *
863 * It's not needed for peripheral side, which dedicates endpoints;
864 * though it _might_ use SOF irqs for other purposes.
865 *
866 * And it's not currently needed for host side, which also dedicates
867 * endpoints, relies on TX/RX interval registers, and isn't claimed
868 * to support ISO transfers yet.
869 */
870 if (int_usb & MUSB_INTR_SOF) {
871 void __iomem *mbase = musb->mregs;
872 struct musb_hw_ep *ep;
873 u8 epnum;
874 u16 frame;
875
876 dev_dbg(musb->controller, "START_OF_FRAME\n");
877 handled = IRQ_HANDLED;
878
879 /* start any periodic Tx transfers waiting for current frame */
880 frame = musb_readw(mbase, MUSB_FRAME);
881 ep = musb->endpoints;
882 for (epnum = 1; (epnum < musb->nr_endpoints)
883 && (musb->epmask >= (1 << epnum));
884 epnum++, ep++) {
885 /*
886 * FIXME handle framecounter wraps (12 bits)
887 * eliminate duplicated StartUrb logic
888 */
889 if (ep->dwWaitFrame >= frame) {
890 ep->dwWaitFrame = 0;
891 pr_debug("SOF --> periodic TX%s on %d\n",
892 ep->tx_channel ? " DMA" : "",
893 epnum);
894 if (!ep->tx_channel)
895 musb_h_tx_start(musb, epnum);
896 else
897 cppi_hostdma_start(musb, epnum);
898 }
899 } /* end of for loop */
900 }
901 #endif
902
903 schedule_work(&musb->irq_work);
904
905 return handled;
906 }
907
908 /*-------------------------------------------------------------------------*/
909
910 /*
911 * Program the HDRC to start (enable interrupts, dma, etc.).
912 */
913 void musb_start(struct musb *musb)
914 {
915 void __iomem *regs = musb->mregs;
916 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
917
918 dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
919
920 /* Set INT enable registers, enable interrupts */
921 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
922 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
923 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
924
925 musb_writeb(regs, MUSB_TESTMODE, 0);
926
927 /* put into basic highspeed mode and start session */
928 musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
929 | MUSB_POWER_SOFTCONN
930 | MUSB_POWER_HSENAB
931 /* ENSUSPEND wedges tusb */
932 /* | MUSB_POWER_ENSUSPEND */
933 );
934
935 musb->is_active = 0;
936 devctl = musb_readb(regs, MUSB_DEVCTL);
937 devctl &= ~MUSB_DEVCTL_SESSION;
938
939 if (is_otg_enabled(musb)) {
940 /* session started after:
941 * (a) ID-grounded irq, host mode;
942 * (b) vbus present/connect IRQ, peripheral mode;
943 * (c) peripheral initiates, using SRP
944 */
945 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
946 musb->is_active = 1;
947 else
948 devctl |= MUSB_DEVCTL_SESSION;
949
950 } else if (is_host_enabled(musb)) {
951 /* assume ID pin is hard-wired to ground */
952 devctl |= MUSB_DEVCTL_SESSION;
953
954 } else /* peripheral is enabled */ {
955 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
956 musb->is_active = 1;
957 }
958 musb_platform_enable(musb);
959 musb_writeb(regs, MUSB_DEVCTL, devctl);
960 }
961
962
963 static void musb_generic_disable(struct musb *musb)
964 {
965 void __iomem *mbase = musb->mregs;
966 u16 temp;
967
968 /* disable interrupts */
969 musb_writeb(mbase, MUSB_INTRUSBE, 0);
970 musb_writew(mbase, MUSB_INTRTXE, 0);
971 musb_writew(mbase, MUSB_INTRRXE, 0);
972
973 /* off */
974 musb_writeb(mbase, MUSB_DEVCTL, 0);
975
976 /* flush pending interrupts */
977 temp = musb_readb(mbase, MUSB_INTRUSB);
978 temp = musb_readw(mbase, MUSB_INTRTX);
979 temp = musb_readw(mbase, MUSB_INTRRX);
980
981 }
982
983 /*
984 * Make the HDRC stop (disable interrupts, etc.);
985 * reversible by musb_start
986 * called on gadget driver unregister
987 * with controller locked, irqs blocked
988 * acts as a NOP unless some role activated the hardware
989 */
990 void musb_stop(struct musb *musb)
991 {
992 /* stop IRQs, timers, ... */
993 musb_platform_disable(musb);
994 musb_generic_disable(musb);
995 dev_dbg(musb->controller, "HDRC disabled\n");
996
997 /* FIXME
998 * - mark host and/or peripheral drivers unusable/inactive
999 * - disable DMA (and enable it in HdrcStart)
1000 * - make sure we can musb_start() after musb_stop(); with
1001 * OTG mode, gadget driver module rmmod/modprobe cycles that
1002 * - ...
1003 */
1004 musb_platform_try_idle(musb, 0);
1005 }
1006
1007 static void musb_shutdown(struct platform_device *pdev)
1008 {
1009 struct musb *musb = dev_to_musb(&pdev->dev);
1010 unsigned long flags;
1011
1012 pm_runtime_get_sync(musb->controller);
1013 spin_lock_irqsave(&musb->lock, flags);
1014 musb_platform_disable(musb);
1015 musb_generic_disable(musb);
1016 spin_unlock_irqrestore(&musb->lock, flags);
1017
1018 if (!is_otg_enabled(musb) && is_host_enabled(musb))
1019 usb_remove_hcd(musb_to_hcd(musb));
1020 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1021 musb_platform_exit(musb);
1022
1023 pm_runtime_put(musb->controller);
1024 /* FIXME power down */
1025 }
1026
1027
1028 /*-------------------------------------------------------------------------*/
1029
1030 /*
1031 * The silicon either has hard-wired endpoint configurations, or else
1032 * "dynamic fifo" sizing. The driver has support for both, though at this
1033 * writing only the dynamic sizing is very well tested. Since we switched
1034 * away from compile-time hardware parameters, we can no longer rely on
1035 * dead code elimination to leave only the relevant one in the object file.
1036 *
1037 * We don't currently use dynamic fifo setup capability to do anything
1038 * more than selecting one of a bunch of predefined configurations.
1039 */
1040 #if defined(CONFIG_USB_MUSB_TUSB6010) || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
1041 || defined(CONFIG_USB_MUSB_AM35X)
1042 static ushort __initdata fifo_mode = 4;
1043 #elif defined(CONFIG_USB_MUSB_UX500)
1044 static ushort __initdata fifo_mode = 5;
1045 #else
1046 static ushort __initdata fifo_mode = 2;
1047 #endif
1048
1049 /* "modprobe ... fifo_mode=1" etc */
1050 module_param(fifo_mode, ushort, 0);
1051 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1052
1053 /*
1054 * tables defining fifo_mode values. define more if you like.
1055 * for host side, make sure both halves of ep1 are set up.
1056 */
1057
1058 /* mode 0 - fits in 2KB */
1059 static struct musb_fifo_cfg __initdata mode_0_cfg[] = {
1060 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1061 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1062 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1063 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1064 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1065 };
1066
1067 /* mode 1 - fits in 4KB */
1068 static struct musb_fifo_cfg __initdata mode_1_cfg[] = {
1069 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1070 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1071 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1072 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1073 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1074 };
1075
1076 /* mode 2 - fits in 4KB */
1077 static struct musb_fifo_cfg __initdata mode_2_cfg[] = {
1078 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1079 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1080 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1081 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1082 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1083 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1084 };
1085
1086 /* mode 3 - fits in 4KB */
1087 static struct musb_fifo_cfg __initdata mode_3_cfg[] = {
1088 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1089 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1090 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1091 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1092 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1093 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1094 };
1095
1096 /* mode 4 - fits in 16KB */
1097 static struct musb_fifo_cfg __initdata mode_4_cfg[] = {
1098 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1099 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1100 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1101 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1102 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1103 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1104 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1105 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1106 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1107 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1108 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1109 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1110 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1111 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1112 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1113 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1114 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1115 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1116 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1117 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1118 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1119 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1120 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1121 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1122 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1123 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1124 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1125 };
1126
1127 /* mode 5 - fits in 8KB */
1128 static struct musb_fifo_cfg __initdata mode_5_cfg[] = {
1129 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1130 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1131 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1132 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1133 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1134 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1135 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1136 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1137 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1138 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1139 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1140 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1141 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1142 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1143 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1144 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1145 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1146 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1147 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1148 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1149 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1150 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1151 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1152 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1153 { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1154 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1155 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1156 };
1157
1158 /*
1159 * configure a fifo; for non-shared endpoints, this may be called
1160 * once for a tx fifo and once for an rx fifo.
1161 *
1162 * returns negative errno or offset for next fifo.
1163 */
1164 static int __init
1165 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1166 const struct musb_fifo_cfg *cfg, u16 offset)
1167 {
1168 void __iomem *mbase = musb->mregs;
1169 int size = 0;
1170 u16 maxpacket = cfg->maxpacket;
1171 u16 c_off = offset >> 3;
1172 u8 c_size;
1173
1174 /* expect hw_ep has already been zero-initialized */
1175
1176 size = ffs(max(maxpacket, (u16) 8)) - 1;
1177 maxpacket = 1 << size;
1178
1179 c_size = size - 3;
1180 if (cfg->mode == BUF_DOUBLE) {
1181 if ((offset + (maxpacket << 1)) >
1182 (1 << (musb->config->ram_bits + 2)))
1183 return -EMSGSIZE;
1184 c_size |= MUSB_FIFOSZ_DPB;
1185 } else {
1186 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1187 return -EMSGSIZE;
1188 }
1189
1190 /* configure the FIFO */
1191 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1192
1193 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1194 /* EP0 reserved endpoint for control, bidirectional;
1195 * EP1 reserved for bulk, two unidirection halves.
1196 */
1197 if (hw_ep->epnum == 1)
1198 musb->bulk_ep = hw_ep;
1199 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1200 #endif
1201 switch (cfg->style) {
1202 case FIFO_TX:
1203 musb_write_txfifosz(mbase, c_size);
1204 musb_write_txfifoadd(mbase, c_off);
1205 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1206 hw_ep->max_packet_sz_tx = maxpacket;
1207 break;
1208 case FIFO_RX:
1209 musb_write_rxfifosz(mbase, c_size);
1210 musb_write_rxfifoadd(mbase, c_off);
1211 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1212 hw_ep->max_packet_sz_rx = maxpacket;
1213 break;
1214 case FIFO_RXTX:
1215 musb_write_txfifosz(mbase, c_size);
1216 musb_write_txfifoadd(mbase, c_off);
1217 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1218 hw_ep->max_packet_sz_rx = maxpacket;
1219
1220 musb_write_rxfifosz(mbase, c_size);
1221 musb_write_rxfifoadd(mbase, c_off);
1222 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1223 hw_ep->max_packet_sz_tx = maxpacket;
1224
1225 hw_ep->is_shared_fifo = true;
1226 break;
1227 }
1228
1229 /* NOTE rx and tx endpoint irqs aren't managed separately,
1230 * which happens to be ok
1231 */
1232 musb->epmask |= (1 << hw_ep->epnum);
1233
1234 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1235 }
1236
1237 static struct musb_fifo_cfg __initdata ep0_cfg = {
1238 .style = FIFO_RXTX, .maxpacket = 64,
1239 };
1240
1241 static int __init ep_config_from_table(struct musb *musb)
1242 {
1243 const struct musb_fifo_cfg *cfg;
1244 unsigned i, n;
1245 int offset;
1246 struct musb_hw_ep *hw_ep = musb->endpoints;
1247
1248 if (musb->config->fifo_cfg) {
1249 cfg = musb->config->fifo_cfg;
1250 n = musb->config->fifo_cfg_size;
1251 goto done;
1252 }
1253
1254 switch (fifo_mode) {
1255 default:
1256 fifo_mode = 0;
1257 /* FALLTHROUGH */
1258 case 0:
1259 cfg = mode_0_cfg;
1260 n = ARRAY_SIZE(mode_0_cfg);
1261 break;
1262 case 1:
1263 cfg = mode_1_cfg;
1264 n = ARRAY_SIZE(mode_1_cfg);
1265 break;
1266 case 2:
1267 cfg = mode_2_cfg;
1268 n = ARRAY_SIZE(mode_2_cfg);
1269 break;
1270 case 3:
1271 cfg = mode_3_cfg;
1272 n = ARRAY_SIZE(mode_3_cfg);
1273 break;
1274 case 4:
1275 cfg = mode_4_cfg;
1276 n = ARRAY_SIZE(mode_4_cfg);
1277 break;
1278 case 5:
1279 cfg = mode_5_cfg;
1280 n = ARRAY_SIZE(mode_5_cfg);
1281 break;
1282 }
1283
1284 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1285 musb_driver_name, fifo_mode);
1286
1287
1288 done:
1289 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1290 /* assert(offset > 0) */
1291
1292 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1293 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1294 */
1295
1296 for (i = 0; i < n; i++) {
1297 u8 epn = cfg->hw_ep_num;
1298
1299 if (epn >= musb->config->num_eps) {
1300 pr_debug("%s: invalid ep %d\n",
1301 musb_driver_name, epn);
1302 return -EINVAL;
1303 }
1304 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1305 if (offset < 0) {
1306 pr_debug("%s: mem overrun, ep %d\n",
1307 musb_driver_name, epn);
1308 return -EINVAL;
1309 }
1310 epn++;
1311 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1312 }
1313
1314 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1315 musb_driver_name,
1316 n + 1, musb->config->num_eps * 2 - 1,
1317 offset, (1 << (musb->config->ram_bits + 2)));
1318
1319 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1320 if (!musb->bulk_ep) {
1321 pr_debug("%s: missing bulk\n", musb_driver_name);
1322 return -EINVAL;
1323 }
1324 #endif
1325
1326 return 0;
1327 }
1328
1329
1330 /*
1331 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1332 * @param musb the controller
1333 */
1334 static int __init ep_config_from_hw(struct musb *musb)
1335 {
1336 u8 epnum = 0;
1337 struct musb_hw_ep *hw_ep;
1338 void *mbase = musb->mregs;
1339 int ret = 0;
1340
1341 dev_dbg(musb->controller, "<== static silicon ep config\n");
1342
1343 /* FIXME pick up ep0 maxpacket size */
1344
1345 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1346 musb_ep_select(mbase, epnum);
1347 hw_ep = musb->endpoints + epnum;
1348
1349 ret = musb_read_fifosize(musb, hw_ep, epnum);
1350 if (ret < 0)
1351 break;
1352
1353 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1354
1355 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1356 /* pick an RX/TX endpoint for bulk */
1357 if (hw_ep->max_packet_sz_tx < 512
1358 || hw_ep->max_packet_sz_rx < 512)
1359 continue;
1360
1361 /* REVISIT: this algorithm is lazy, we should at least
1362 * try to pick a double buffered endpoint.
1363 */
1364 if (musb->bulk_ep)
1365 continue;
1366 musb->bulk_ep = hw_ep;
1367 #endif
1368 }
1369
1370 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1371 if (!musb->bulk_ep) {
1372 pr_debug("%s: missing bulk\n", musb_driver_name);
1373 return -EINVAL;
1374 }
1375 #endif
1376
1377 return 0;
1378 }
1379
1380 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1381
1382 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1383 * configure endpoints, or take their config from silicon
1384 */
1385 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1386 {
1387 u8 reg;
1388 char *type;
1389 char aInfo[90], aRevision[32], aDate[12];
1390 void __iomem *mbase = musb->mregs;
1391 int status = 0;
1392 int i;
1393
1394 /* log core options (read using indexed model) */
1395 reg = musb_read_configdata(mbase);
1396
1397 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1398 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1399 strcat(aInfo, ", dyn FIFOs");
1400 musb->dyn_fifo = true;
1401 }
1402 if (reg & MUSB_CONFIGDATA_MPRXE) {
1403 strcat(aInfo, ", bulk combine");
1404 musb->bulk_combine = true;
1405 }
1406 if (reg & MUSB_CONFIGDATA_MPTXE) {
1407 strcat(aInfo, ", bulk split");
1408 musb->bulk_split = true;
1409 }
1410 if (reg & MUSB_CONFIGDATA_HBRXE) {
1411 strcat(aInfo, ", HB-ISO Rx");
1412 musb->hb_iso_rx = true;
1413 }
1414 if (reg & MUSB_CONFIGDATA_HBTXE) {
1415 strcat(aInfo, ", HB-ISO Tx");
1416 musb->hb_iso_tx = true;
1417 }
1418 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1419 strcat(aInfo, ", SoftConn");
1420
1421 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1422 musb_driver_name, reg, aInfo);
1423
1424 aDate[0] = 0;
1425 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1426 musb->is_multipoint = 1;
1427 type = "M";
1428 } else {
1429 musb->is_multipoint = 0;
1430 type = "";
1431 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1432 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1433 printk(KERN_ERR
1434 "%s: kernel must blacklist external hubs\n",
1435 musb_driver_name);
1436 #endif
1437 #endif
1438 }
1439
1440 /* log release info */
1441 musb->hwvers = musb_read_hwvers(mbase);
1442 snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
1443 MUSB_HWVERS_MINOR(musb->hwvers),
1444 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1445 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1446 musb_driver_name, type, aRevision, aDate);
1447
1448 /* configure ep0 */
1449 musb_configure_ep0(musb);
1450
1451 /* discover endpoint configuration */
1452 musb->nr_endpoints = 1;
1453 musb->epmask = 1;
1454
1455 if (musb->dyn_fifo)
1456 status = ep_config_from_table(musb);
1457 else
1458 status = ep_config_from_hw(musb);
1459
1460 if (status < 0)
1461 return status;
1462
1463 /* finish init, and print endpoint config */
1464 for (i = 0; i < musb->nr_endpoints; i++) {
1465 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1466
1467 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1468 #ifdef CONFIG_USB_MUSB_TUSB6010
1469 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1470 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1471 hw_ep->fifo_sync_va =
1472 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1473
1474 if (i == 0)
1475 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1476 else
1477 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1478 #endif
1479
1480 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1481 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1482 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1483 hw_ep->rx_reinit = 1;
1484 hw_ep->tx_reinit = 1;
1485 #endif
1486
1487 if (hw_ep->max_packet_sz_tx) {
1488 dev_dbg(musb->controller,
1489 "%s: hw_ep %d%s, %smax %d\n",
1490 musb_driver_name, i,
1491 hw_ep->is_shared_fifo ? "shared" : "tx",
1492 hw_ep->tx_double_buffered
1493 ? "doublebuffer, " : "",
1494 hw_ep->max_packet_sz_tx);
1495 }
1496 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1497 dev_dbg(musb->controller,
1498 "%s: hw_ep %d%s, %smax %d\n",
1499 musb_driver_name, i,
1500 "rx",
1501 hw_ep->rx_double_buffered
1502 ? "doublebuffer, " : "",
1503 hw_ep->max_packet_sz_rx);
1504 }
1505 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1506 dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
1507 }
1508
1509 return 0;
1510 }
1511
1512 /*-------------------------------------------------------------------------*/
1513
1514 #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
1515 defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500) || \
1516 defined(CONFIG_ARCH_U5500)
1517
1518 static irqreturn_t generic_interrupt(int irq, void *__hci)
1519 {
1520 unsigned long flags;
1521 irqreturn_t retval = IRQ_NONE;
1522 struct musb *musb = __hci;
1523
1524 spin_lock_irqsave(&musb->lock, flags);
1525
1526 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1527 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1528 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1529
1530 if (musb->int_usb || musb->int_tx || musb->int_rx)
1531 retval = musb_interrupt(musb);
1532
1533 spin_unlock_irqrestore(&musb->lock, flags);
1534
1535 return retval;
1536 }
1537
1538 #else
1539 #define generic_interrupt NULL
1540 #endif
1541
1542 /*
1543 * handle all the irqs defined by the HDRC core. for now we expect: other
1544 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1545 * will be assigned, and the irq will already have been acked.
1546 *
1547 * called in irq context with spinlock held, irqs blocked
1548 */
1549 irqreturn_t musb_interrupt(struct musb *musb)
1550 {
1551 irqreturn_t retval = IRQ_NONE;
1552 u8 devctl, power;
1553 int ep_num;
1554 u32 reg;
1555
1556 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1557 power = musb_readb(musb->mregs, MUSB_POWER);
1558
1559 dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
1560 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1561 musb->int_usb, musb->int_tx, musb->int_rx);
1562
1563 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1564 if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
1565 if (!musb->gadget_driver) {
1566 dev_dbg(musb->controller, "No gadget driver loaded\n");
1567 return IRQ_HANDLED;
1568 }
1569 #endif
1570
1571 /* the core can interrupt us for multiple reasons; docs have
1572 * a generic interrupt flowchart to follow
1573 */
1574 if (musb->int_usb)
1575 retval |= musb_stage0_irq(musb, musb->int_usb,
1576 devctl, power);
1577
1578 /* "stage 1" is handling endpoint irqs */
1579
1580 /* handle endpoint 0 first */
1581 if (musb->int_tx & 1) {
1582 if (devctl & MUSB_DEVCTL_HM)
1583 retval |= musb_h_ep0_irq(musb);
1584 else
1585 retval |= musb_g_ep0_irq(musb);
1586 }
1587
1588 /* RX on endpoints 1-15 */
1589 reg = musb->int_rx >> 1;
1590 ep_num = 1;
1591 while (reg) {
1592 if (reg & 1) {
1593 /* musb_ep_select(musb->mregs, ep_num); */
1594 /* REVISIT just retval = ep->rx_irq(...) */
1595 retval = IRQ_HANDLED;
1596 if (devctl & MUSB_DEVCTL_HM) {
1597 if (is_host_capable())
1598 musb_host_rx(musb, ep_num);
1599 } else {
1600 if (is_peripheral_capable())
1601 musb_g_rx(musb, ep_num);
1602 }
1603 }
1604
1605 reg >>= 1;
1606 ep_num++;
1607 }
1608
1609 /* TX on endpoints 1-15 */
1610 reg = musb->int_tx >> 1;
1611 ep_num = 1;
1612 while (reg) {
1613 if (reg & 1) {
1614 /* musb_ep_select(musb->mregs, ep_num); */
1615 /* REVISIT just retval |= ep->tx_irq(...) */
1616 retval = IRQ_HANDLED;
1617 if (devctl & MUSB_DEVCTL_HM) {
1618 if (is_host_capable())
1619 musb_host_tx(musb, ep_num);
1620 } else {
1621 if (is_peripheral_capable())
1622 musb_g_tx(musb, ep_num);
1623 }
1624 }
1625 reg >>= 1;
1626 ep_num++;
1627 }
1628
1629 return retval;
1630 }
1631 EXPORT_SYMBOL_GPL(musb_interrupt);
1632
1633 #ifndef CONFIG_MUSB_PIO_ONLY
1634 static int __initdata use_dma = 1;
1635
1636 /* "modprobe ... use_dma=0" etc */
1637 module_param(use_dma, bool, 0);
1638 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1639
1640 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1641 {
1642 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1643
1644 /* called with controller lock already held */
1645
1646 if (!epnum) {
1647 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1648 if (!is_cppi_enabled()) {
1649 /* endpoint 0 */
1650 if (devctl & MUSB_DEVCTL_HM)
1651 musb_h_ep0_irq(musb);
1652 else
1653 musb_g_ep0_irq(musb);
1654 }
1655 #endif
1656 } else {
1657 /* endpoints 1..15 */
1658 if (transmit) {
1659 if (devctl & MUSB_DEVCTL_HM) {
1660 if (is_host_capable())
1661 musb_host_tx(musb, epnum);
1662 } else {
1663 if (is_peripheral_capable())
1664 musb_g_tx(musb, epnum);
1665 }
1666 } else {
1667 /* receive */
1668 if (devctl & MUSB_DEVCTL_HM) {
1669 if (is_host_capable())
1670 musb_host_rx(musb, epnum);
1671 } else {
1672 if (is_peripheral_capable())
1673 musb_g_rx(musb, epnum);
1674 }
1675 }
1676 }
1677 }
1678
1679 #else
1680 #define use_dma 0
1681 #endif
1682
1683 /*-------------------------------------------------------------------------*/
1684
1685 #ifdef CONFIG_SYSFS
1686
1687 static ssize_t
1688 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1689 {
1690 struct musb *musb = dev_to_musb(dev);
1691 unsigned long flags;
1692 int ret = -EINVAL;
1693
1694 spin_lock_irqsave(&musb->lock, flags);
1695 ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
1696 spin_unlock_irqrestore(&musb->lock, flags);
1697
1698 return ret;
1699 }
1700
1701 static ssize_t
1702 musb_mode_store(struct device *dev, struct device_attribute *attr,
1703 const char *buf, size_t n)
1704 {
1705 struct musb *musb = dev_to_musb(dev);
1706 unsigned long flags;
1707 int status;
1708
1709 spin_lock_irqsave(&musb->lock, flags);
1710 if (sysfs_streq(buf, "host"))
1711 status = musb_platform_set_mode(musb, MUSB_HOST);
1712 else if (sysfs_streq(buf, "peripheral"))
1713 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1714 else if (sysfs_streq(buf, "otg"))
1715 status = musb_platform_set_mode(musb, MUSB_OTG);
1716 else
1717 status = -EINVAL;
1718 spin_unlock_irqrestore(&musb->lock, flags);
1719
1720 return (status == 0) ? n : status;
1721 }
1722 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
1723
1724 static ssize_t
1725 musb_vbus_store(struct device *dev, struct device_attribute *attr,
1726 const char *buf, size_t n)
1727 {
1728 struct musb *musb = dev_to_musb(dev);
1729 unsigned long flags;
1730 unsigned long val;
1731
1732 if (sscanf(buf, "%lu", &val) < 1) {
1733 dev_err(dev, "Invalid VBUS timeout ms value\n");
1734 return -EINVAL;
1735 }
1736
1737 spin_lock_irqsave(&musb->lock, flags);
1738 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1739 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1740 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
1741 musb->is_active = 0;
1742 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1743 spin_unlock_irqrestore(&musb->lock, flags);
1744
1745 return n;
1746 }
1747
1748 static ssize_t
1749 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1750 {
1751 struct musb *musb = dev_to_musb(dev);
1752 unsigned long flags;
1753 unsigned long val;
1754 int vbus;
1755
1756 spin_lock_irqsave(&musb->lock, flags);
1757 val = musb->a_wait_bcon;
1758 /* FIXME get_vbus_status() is normally #defined as false...
1759 * and is effectively TUSB-specific.
1760 */
1761 vbus = musb_platform_get_vbus_status(musb);
1762 spin_unlock_irqrestore(&musb->lock, flags);
1763
1764 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1765 vbus ? "on" : "off", val);
1766 }
1767 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
1768
1769 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1770
1771 /* Gadget drivers can't know that a host is connected so they might want
1772 * to start SRP, but users can. This allows userspace to trigger SRP.
1773 */
1774 static ssize_t
1775 musb_srp_store(struct device *dev, struct device_attribute *attr,
1776 const char *buf, size_t n)
1777 {
1778 struct musb *musb = dev_to_musb(dev);
1779 unsigned short srp;
1780
1781 if (sscanf(buf, "%hu", &srp) != 1
1782 || (srp != 1)) {
1783 dev_err(dev, "SRP: Value must be 1\n");
1784 return -EINVAL;
1785 }
1786
1787 if (srp == 1)
1788 musb_g_wakeup(musb);
1789
1790 return n;
1791 }
1792 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
1793
1794 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
1795
1796 static struct attribute *musb_attributes[] = {
1797 &dev_attr_mode.attr,
1798 &dev_attr_vbus.attr,
1799 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1800 &dev_attr_srp.attr,
1801 #endif
1802 NULL
1803 };
1804
1805 static const struct attribute_group musb_attr_group = {
1806 .attrs = musb_attributes,
1807 };
1808
1809 #endif /* sysfs */
1810
1811 /* Only used to provide driver mode change events */
1812 static void musb_irq_work(struct work_struct *data)
1813 {
1814 struct musb *musb = container_of(data, struct musb, irq_work);
1815 static int old_state;
1816
1817 if (musb->xceiv->state != old_state) {
1818 old_state = musb->xceiv->state;
1819 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1820 }
1821 }
1822
1823 /* --------------------------------------------------------------------------
1824 * Init support
1825 */
1826
1827 static struct musb *__init
1828 allocate_instance(struct device *dev,
1829 struct musb_hdrc_config *config, void __iomem *mbase)
1830 {
1831 struct musb *musb;
1832 struct musb_hw_ep *ep;
1833 int epnum;
1834 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1835 struct usb_hcd *hcd;
1836
1837 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
1838 if (!hcd)
1839 return NULL;
1840 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
1841
1842 musb = hcd_to_musb(hcd);
1843 INIT_LIST_HEAD(&musb->control);
1844 INIT_LIST_HEAD(&musb->in_bulk);
1845 INIT_LIST_HEAD(&musb->out_bulk);
1846
1847 hcd->uses_new_polling = 1;
1848 hcd->has_tt = 1;
1849
1850 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1851 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1852 #else
1853 musb = kzalloc(sizeof *musb, GFP_KERNEL);
1854 if (!musb)
1855 return NULL;
1856
1857 #endif
1858 dev_set_drvdata(dev, musb);
1859 musb->mregs = mbase;
1860 musb->ctrl_base = mbase;
1861 musb->nIrq = -ENODEV;
1862 musb->config = config;
1863 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1864 for (epnum = 0, ep = musb->endpoints;
1865 epnum < musb->config->num_eps;
1866 epnum++, ep++) {
1867 ep->musb = musb;
1868 ep->epnum = epnum;
1869 }
1870
1871 musb->controller = dev;
1872
1873 return musb;
1874 }
1875
1876 static void musb_free(struct musb *musb)
1877 {
1878 /* this has multiple entry modes. it handles fault cleanup after
1879 * probe(), where things may be partially set up, as well as rmmod
1880 * cleanup after everything's been de-activated.
1881 */
1882
1883 #ifdef CONFIG_SYSFS
1884 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
1885 #endif
1886
1887 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1888 musb_gadget_cleanup(musb);
1889 #endif
1890
1891 if (musb->nIrq >= 0) {
1892 if (musb->irq_wake)
1893 disable_irq_wake(musb->nIrq);
1894 free_irq(musb->nIrq, musb);
1895 }
1896 if (is_dma_capable() && musb->dma_controller) {
1897 struct dma_controller *c = musb->dma_controller;
1898
1899 (void) c->stop(c);
1900 dma_controller_destroy(c);
1901 }
1902
1903 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1904 usb_put_hcd(musb_to_hcd(musb));
1905 #else
1906 kfree(musb);
1907 #endif
1908 }
1909
1910 /*
1911 * Perform generic per-controller initialization.
1912 *
1913 * @pDevice: the controller (already clocked, etc)
1914 * @nIrq: irq
1915 * @mregs: virtual address of controller registers,
1916 * not yet corrected for platform-specific offsets
1917 */
1918 static int __init
1919 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
1920 {
1921 int status;
1922 struct musb *musb;
1923 struct musb_hdrc_platform_data *plat = dev->platform_data;
1924
1925 /* The driver might handle more features than the board; OK.
1926 * Fail when the board needs a feature that's not enabled.
1927 */
1928 if (!plat) {
1929 dev_dbg(dev, "no platform_data?\n");
1930 status = -ENODEV;
1931 goto fail0;
1932 }
1933
1934 /* allocate */
1935 musb = allocate_instance(dev, plat->config, ctrl);
1936 if (!musb) {
1937 status = -ENOMEM;
1938 goto fail0;
1939 }
1940
1941 pm_runtime_use_autosuspend(musb->controller);
1942 pm_runtime_set_autosuspend_delay(musb->controller, 200);
1943 pm_runtime_enable(musb->controller);
1944
1945 spin_lock_init(&musb->lock);
1946 musb->board_mode = plat->mode;
1947 musb->board_set_power = plat->set_power;
1948 musb->min_power = plat->min_power;
1949 musb->ops = plat->platform_ops;
1950
1951 /* The musb_platform_init() call:
1952 * - adjusts musb->mregs and musb->isr if needed,
1953 * - may initialize an integrated tranceiver
1954 * - initializes musb->xceiv, usually by otg_get_transceiver()
1955 * - stops powering VBUS
1956 *
1957 * There are various transciever configurations. Blackfin,
1958 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
1959 * external/discrete ones in various flavors (twl4030 family,
1960 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
1961 */
1962 musb->isr = generic_interrupt;
1963 status = musb_platform_init(musb);
1964 if (status < 0)
1965 goto fail1;
1966
1967 if (!musb->isr) {
1968 status = -ENODEV;
1969 goto fail3;
1970 }
1971
1972 if (!musb->xceiv->io_ops) {
1973 musb->xceiv->io_priv = musb->mregs;
1974 musb->xceiv->io_ops = &musb_ulpi_access;
1975 }
1976
1977 #ifndef CONFIG_MUSB_PIO_ONLY
1978 if (use_dma && dev->dma_mask) {
1979 struct dma_controller *c;
1980
1981 c = dma_controller_create(musb, musb->mregs);
1982 musb->dma_controller = c;
1983 if (c)
1984 (void) c->start(c);
1985 }
1986 #endif
1987 /* ideally this would be abstracted in platform setup */
1988 if (!is_dma_capable() || !musb->dma_controller)
1989 dev->dma_mask = NULL;
1990
1991 /* be sure interrupts are disabled before connecting ISR */
1992 musb_platform_disable(musb);
1993 musb_generic_disable(musb);
1994
1995 /* setup musb parts of the core (especially endpoints) */
1996 status = musb_core_init(plat->config->multipoint
1997 ? MUSB_CONTROLLER_MHDRC
1998 : MUSB_CONTROLLER_HDRC, musb);
1999 if (status < 0)
2000 goto fail3;
2001
2002 #ifdef CONFIG_USB_MUSB_OTG
2003 setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
2004 #endif
2005
2006 /* Init IRQ workqueue before request_irq */
2007 INIT_WORK(&musb->irq_work, musb_irq_work);
2008
2009 /* attach to the IRQ */
2010 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2011 dev_err(dev, "request_irq %d failed!\n", nIrq);
2012 status = -ENODEV;
2013 goto fail3;
2014 }
2015 musb->nIrq = nIrq;
2016 /* FIXME this handles wakeup irqs wrong */
2017 if (enable_irq_wake(nIrq) == 0) {
2018 musb->irq_wake = 1;
2019 device_init_wakeup(dev, 1);
2020 } else {
2021 musb->irq_wake = 0;
2022 }
2023
2024 /* host side needs more setup */
2025 if (is_host_enabled(musb)) {
2026 struct usb_hcd *hcd = musb_to_hcd(musb);
2027
2028 otg_set_host(musb->xceiv, &hcd->self);
2029
2030 if (is_otg_enabled(musb))
2031 hcd->self.otg_port = 1;
2032 musb->xceiv->host = &hcd->self;
2033 hcd->power_budget = 2 * (plat->power ? : 250);
2034
2035 /* program PHY to use external vBus if required */
2036 if (plat->extvbus) {
2037 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2038 busctl |= MUSB_ULPI_USE_EXTVBUS;
2039 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2040 }
2041 }
2042
2043 /* For the host-only role, we can activate right away.
2044 * (We expect the ID pin to be forcibly grounded!!)
2045 * Otherwise, wait till the gadget driver hooks up.
2046 */
2047 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2048 struct usb_hcd *hcd = musb_to_hcd(musb);
2049
2050 MUSB_HST_MODE(musb);
2051 musb->xceiv->default_a = 1;
2052 musb->xceiv->state = OTG_STATE_A_IDLE;
2053
2054 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2055
2056 hcd->self.uses_pio_for_control = 1;
2057 dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
2058 "HOST", status,
2059 musb_readb(musb->mregs, MUSB_DEVCTL),
2060 (musb_readb(musb->mregs, MUSB_DEVCTL)
2061 & MUSB_DEVCTL_BDEVICE
2062 ? 'B' : 'A'));
2063
2064 } else /* peripheral is enabled */ {
2065 MUSB_DEV_MODE(musb);
2066 musb->xceiv->default_a = 0;
2067 musb->xceiv->state = OTG_STATE_B_IDLE;
2068
2069 status = musb_gadget_setup(musb);
2070
2071 dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
2072 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2073 status,
2074 musb_readb(musb->mregs, MUSB_DEVCTL));
2075
2076 }
2077 if (status < 0)
2078 goto fail3;
2079
2080 pm_runtime_put(musb->controller);
2081
2082 status = musb_init_debugfs(musb);
2083 if (status < 0)
2084 goto fail4;
2085
2086 #ifdef CONFIG_SYSFS
2087 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2088 if (status)
2089 goto fail5;
2090 #endif
2091
2092 dev_info(dev, "USB %s mode controller at %p using %s, IRQ %d\n",
2093 ({char *s;
2094 switch (musb->board_mode) {
2095 case MUSB_HOST: s = "Host"; break;
2096 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2097 default: s = "OTG"; break;
2098 }; s; }),
2099 ctrl,
2100 (is_dma_capable() && musb->dma_controller)
2101 ? "DMA" : "PIO",
2102 musb->nIrq);
2103
2104 return 0;
2105
2106 fail5:
2107 musb_exit_debugfs(musb);
2108
2109 fail4:
2110 if (!is_otg_enabled(musb) && is_host_enabled(musb))
2111 usb_remove_hcd(musb_to_hcd(musb));
2112 else
2113 musb_gadget_cleanup(musb);
2114
2115 fail3:
2116 if (musb->irq_wake)
2117 device_init_wakeup(dev, 0);
2118 musb_platform_exit(musb);
2119
2120 fail1:
2121 dev_err(musb->controller,
2122 "musb_init_controller failed with status %d\n", status);
2123
2124 musb_free(musb);
2125
2126 fail0:
2127
2128 return status;
2129
2130 }
2131
2132 /*-------------------------------------------------------------------------*/
2133
2134 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2135 * bridge to a platform device; this driver then suffices.
2136 */
2137
2138 #ifndef CONFIG_MUSB_PIO_ONLY
2139 static u64 *orig_dma_mask;
2140 #endif
2141
2142 static int __init musb_probe(struct platform_device *pdev)
2143 {
2144 struct device *dev = &pdev->dev;
2145 int irq = platform_get_irq_byname(pdev, "mc");
2146 int status;
2147 struct resource *iomem;
2148 void __iomem *base;
2149
2150 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2151 if (!iomem || irq <= 0)
2152 return -ENODEV;
2153
2154 base = ioremap(iomem->start, resource_size(iomem));
2155 if (!base) {
2156 dev_err(dev, "ioremap failed\n");
2157 return -ENOMEM;
2158 }
2159
2160 #ifndef CONFIG_MUSB_PIO_ONLY
2161 /* clobbered by use_dma=n */
2162 orig_dma_mask = dev->dma_mask;
2163 #endif
2164 status = musb_init_controller(dev, irq, base);
2165 if (status < 0)
2166 iounmap(base);
2167
2168 return status;
2169 }
2170
2171 static int __exit musb_remove(struct platform_device *pdev)
2172 {
2173 struct musb *musb = dev_to_musb(&pdev->dev);
2174 void __iomem *ctrl_base = musb->ctrl_base;
2175
2176 /* this gets called on rmmod.
2177 * - Host mode: host may still be active
2178 * - Peripheral mode: peripheral is deactivated (or never-activated)
2179 * - OTG mode: both roles are deactivated (or never-activated)
2180 */
2181 pm_runtime_get_sync(musb->controller);
2182 musb_exit_debugfs(musb);
2183 musb_shutdown(pdev);
2184
2185 pm_runtime_put(musb->controller);
2186 musb_free(musb);
2187 iounmap(ctrl_base);
2188 device_init_wakeup(&pdev->dev, 0);
2189 #ifndef CONFIG_MUSB_PIO_ONLY
2190 pdev->dev.dma_mask = orig_dma_mask;
2191 #endif
2192 return 0;
2193 }
2194
2195 #ifdef CONFIG_PM
2196
2197 static void musb_save_context(struct musb *musb)
2198 {
2199 int i;
2200 void __iomem *musb_base = musb->mregs;
2201 void __iomem *epio;
2202
2203 if (is_host_enabled(musb)) {
2204 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2205 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2206 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2207 }
2208 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2209 musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
2210 musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
2211 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2212 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2213 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2214
2215 for (i = 0; i < musb->config->num_eps; ++i) {
2216 epio = musb->endpoints[i].regs;
2217 musb->context.index_regs[i].txmaxp =
2218 musb_readw(epio, MUSB_TXMAXP);
2219 musb->context.index_regs[i].txcsr =
2220 musb_readw(epio, MUSB_TXCSR);
2221 musb->context.index_regs[i].rxmaxp =
2222 musb_readw(epio, MUSB_RXMAXP);
2223 musb->context.index_regs[i].rxcsr =
2224 musb_readw(epio, MUSB_RXCSR);
2225
2226 if (musb->dyn_fifo) {
2227 musb->context.index_regs[i].txfifoadd =
2228 musb_read_txfifoadd(musb_base);
2229 musb->context.index_regs[i].rxfifoadd =
2230 musb_read_rxfifoadd(musb_base);
2231 musb->context.index_regs[i].txfifosz =
2232 musb_read_txfifosz(musb_base);
2233 musb->context.index_regs[i].rxfifosz =
2234 musb_read_rxfifosz(musb_base);
2235 }
2236 if (is_host_enabled(musb)) {
2237 musb->context.index_regs[i].txtype =
2238 musb_readb(epio, MUSB_TXTYPE);
2239 musb->context.index_regs[i].txinterval =
2240 musb_readb(epio, MUSB_TXINTERVAL);
2241 musb->context.index_regs[i].rxtype =
2242 musb_readb(epio, MUSB_RXTYPE);
2243 musb->context.index_regs[i].rxinterval =
2244 musb_readb(epio, MUSB_RXINTERVAL);
2245
2246 musb->context.index_regs[i].txfunaddr =
2247 musb_read_txfunaddr(musb_base, i);
2248 musb->context.index_regs[i].txhubaddr =
2249 musb_read_txhubaddr(musb_base, i);
2250 musb->context.index_regs[i].txhubport =
2251 musb_read_txhubport(musb_base, i);
2252
2253 musb->context.index_regs[i].rxfunaddr =
2254 musb_read_rxfunaddr(musb_base, i);
2255 musb->context.index_regs[i].rxhubaddr =
2256 musb_read_rxhubaddr(musb_base, i);
2257 musb->context.index_regs[i].rxhubport =
2258 musb_read_rxhubport(musb_base, i);
2259 }
2260 }
2261 }
2262
2263 static void musb_restore_context(struct musb *musb)
2264 {
2265 int i;
2266 void __iomem *musb_base = musb->mregs;
2267 void __iomem *ep_target_regs;
2268 void __iomem *epio;
2269
2270 if (is_host_enabled(musb)) {
2271 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2272 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2273 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2274 }
2275 musb_writeb(musb_base, MUSB_POWER, musb->context.power);
2276 musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
2277 musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
2278 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2279 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2280
2281 for (i = 0; i < musb->config->num_eps; ++i) {
2282 epio = musb->endpoints[i].regs;
2283 musb_writew(epio, MUSB_TXMAXP,
2284 musb->context.index_regs[i].txmaxp);
2285 musb_writew(epio, MUSB_TXCSR,
2286 musb->context.index_regs[i].txcsr);
2287 musb_writew(epio, MUSB_RXMAXP,
2288 musb->context.index_regs[i].rxmaxp);
2289 musb_writew(epio, MUSB_RXCSR,
2290 musb->context.index_regs[i].rxcsr);
2291
2292 if (musb->dyn_fifo) {
2293 musb_write_txfifosz(musb_base,
2294 musb->context.index_regs[i].txfifosz);
2295 musb_write_rxfifosz(musb_base,
2296 musb->context.index_regs[i].rxfifosz);
2297 musb_write_txfifoadd(musb_base,
2298 musb->context.index_regs[i].txfifoadd);
2299 musb_write_rxfifoadd(musb_base,
2300 musb->context.index_regs[i].rxfifoadd);
2301 }
2302
2303 if (is_host_enabled(musb)) {
2304 musb_writeb(epio, MUSB_TXTYPE,
2305 musb->context.index_regs[i].txtype);
2306 musb_writeb(epio, MUSB_TXINTERVAL,
2307 musb->context.index_regs[i].txinterval);
2308 musb_writeb(epio, MUSB_RXTYPE,
2309 musb->context.index_regs[i].rxtype);
2310 musb_writeb(epio, MUSB_RXINTERVAL,
2311
2312 musb->context.index_regs[i].rxinterval);
2313 musb_write_txfunaddr(musb_base, i,
2314 musb->context.index_regs[i].txfunaddr);
2315 musb_write_txhubaddr(musb_base, i,
2316 musb->context.index_regs[i].txhubaddr);
2317 musb_write_txhubport(musb_base, i,
2318 musb->context.index_regs[i].txhubport);
2319
2320 ep_target_regs =
2321 musb_read_target_reg_base(i, musb_base);
2322
2323 musb_write_rxfunaddr(ep_target_regs,
2324 musb->context.index_regs[i].rxfunaddr);
2325 musb_write_rxhubaddr(ep_target_regs,
2326 musb->context.index_regs[i].rxhubaddr);
2327 musb_write_rxhubport(ep_target_regs,
2328 musb->context.index_regs[i].rxhubport);
2329 }
2330 }
2331 }
2332
2333 static int musb_suspend(struct device *dev)
2334 {
2335 struct platform_device *pdev = to_platform_device(dev);
2336 unsigned long flags;
2337 struct musb *musb = dev_to_musb(&pdev->dev);
2338
2339 spin_lock_irqsave(&musb->lock, flags);
2340
2341 if (is_peripheral_active(musb)) {
2342 /* FIXME force disconnect unless we know USB will wake
2343 * the system up quickly enough to respond ...
2344 */
2345 } else if (is_host_active(musb)) {
2346 /* we know all the children are suspended; sometimes
2347 * they will even be wakeup-enabled.
2348 */
2349 }
2350
2351 musb_save_context(musb);
2352
2353 spin_unlock_irqrestore(&musb->lock, flags);
2354 return 0;
2355 }
2356
2357 static int musb_resume_noirq(struct device *dev)
2358 {
2359 struct platform_device *pdev = to_platform_device(dev);
2360 struct musb *musb = dev_to_musb(&pdev->dev);
2361
2362 musb_restore_context(musb);
2363
2364 /* for static cmos like DaVinci, register values were preserved
2365 * unless for some reason the whole soc powered down or the USB
2366 * module got reset through the PSC (vs just being disabled).
2367 */
2368 return 0;
2369 }
2370
2371 static int musb_runtime_suspend(struct device *dev)
2372 {
2373 struct musb *musb = dev_to_musb(dev);
2374
2375 musb_save_context(musb);
2376
2377 return 0;
2378 }
2379
2380 static int musb_runtime_resume(struct device *dev)
2381 {
2382 struct musb *musb = dev_to_musb(dev);
2383 static int first = 1;
2384
2385 /*
2386 * When pm_runtime_get_sync called for the first time in driver
2387 * init, some of the structure is still not initialized which is
2388 * used in restore function. But clock needs to be
2389 * enabled before any register access, so
2390 * pm_runtime_get_sync has to be called.
2391 * Also context restore without save does not make
2392 * any sense
2393 */
2394 if (!first)
2395 musb_restore_context(musb);
2396 first = 0;
2397
2398 return 0;
2399 }
2400
2401 static const struct dev_pm_ops musb_dev_pm_ops = {
2402 .suspend = musb_suspend,
2403 .resume_noirq = musb_resume_noirq,
2404 .runtime_suspend = musb_runtime_suspend,
2405 .runtime_resume = musb_runtime_resume,
2406 };
2407
2408 #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2409 #else
2410 #define MUSB_DEV_PM_OPS NULL
2411 #endif
2412
2413 static struct platform_driver musb_driver = {
2414 .driver = {
2415 .name = (char *)musb_driver_name,
2416 .bus = &platform_bus_type,
2417 .owner = THIS_MODULE,
2418 .pm = MUSB_DEV_PM_OPS,
2419 },
2420 .remove = __exit_p(musb_remove),
2421 .shutdown = musb_shutdown,
2422 };
2423
2424 /*-------------------------------------------------------------------------*/
2425
2426 static int __init musb_init(void)
2427 {
2428 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2429 if (usb_disabled())
2430 return 0;
2431 #endif
2432
2433 pr_info("%s: version " MUSB_VERSION ", "
2434 #ifdef CONFIG_MUSB_PIO_ONLY
2435 "pio"
2436 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2437 "cppi-dma"
2438 #elif defined(CONFIG_USB_INVENTRA_DMA)
2439 "musb-dma"
2440 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2441 "tusb-omap-dma"
2442 #elif defined(CONFIG_USB_UX500_DMA)
2443 "ux500-dma"
2444 #else
2445 "?dma?"
2446 #endif
2447 ", "
2448 #ifdef CONFIG_USB_MUSB_OTG
2449 "otg (peripheral+host)"
2450 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2451 "peripheral"
2452 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2453 "host"
2454 #endif
2455 ,
2456 musb_driver_name);
2457 return platform_driver_probe(&musb_driver, musb_probe);
2458 }
2459
2460 /* make us init after usbcore and i2c (transceivers, regulators, etc)
2461 * and before usb gadget and host-side drivers start to register
2462 */
2463 fs_initcall(musb_init);
2464
2465 static void __exit musb_cleanup(void)
2466 {
2467 platform_driver_unregister(&musb_driver);
2468 }
2469 module_exit(musb_cleanup);
Linux with added FPC-III support