ARM: mm: Recreate kernel mappings in early_paging_init()
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-of-esdhc.c
blobe328252ebf2a7f684d0756dbfe1c1b20935d05ab
1 /*
2 * Freescale eSDHC controller driver.
4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/of.h>
19 #include <linux/delay.h>
20 #include <linux/module.h>
21 #include <linux/mmc/host.h>
22 #include "sdhci-pltfm.h"
23 #include "sdhci-esdhc.h"
25 #define VENDOR_V_22 0x12
26 #define VENDOR_V_23 0x13
27 static u32 esdhc_readl(struct sdhci_host *host, int reg)
29 u32 ret;
31 ret = in_be32(host->ioaddr + reg);
33 * The bit of ADMA flag in eSDHC is not compatible with standard
34 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
35 * supported by eSDHC.
36 * And for many FSL eSDHC controller, the reset value of field
37 * SDHCI_CAN_DO_ADMA1 is one, but some of them can't support ADMA,
38 * only these vendor version is greater than 2.2/0x12 support ADMA.
39 * For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the
40 * the verdor version number, oxFE is SDHCI_HOST_VERSION.
42 if ((reg == SDHCI_CAPABILITIES) && (ret & SDHCI_CAN_DO_ADMA1)) {
43 u32 tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
44 tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
45 if (tmp > VENDOR_V_22)
46 ret |= SDHCI_CAN_DO_ADMA2;
49 return ret;
52 static u16 esdhc_readw(struct sdhci_host *host, int reg)
54 u16 ret;
55 int base = reg & ~0x3;
56 int shift = (reg & 0x2) * 8;
58 if (unlikely(reg == SDHCI_HOST_VERSION))
59 ret = in_be32(host->ioaddr + base) & 0xffff;
60 else
61 ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
62 return ret;
65 static u8 esdhc_readb(struct sdhci_host *host, int reg)
67 int base = reg & ~0x3;
68 int shift = (reg & 0x3) * 8;
69 u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
72 * "DMA select" locates at offset 0x28 in SD specification, but on
73 * P5020 or P3041, it locates at 0x29.
75 if (reg == SDHCI_HOST_CONTROL) {
76 u32 dma_bits;
78 dma_bits = in_be32(host->ioaddr + reg);
79 /* DMA select is 22,23 bits in Protocol Control Register */
80 dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK;
82 /* fixup the result */
83 ret &= ~SDHCI_CTRL_DMA_MASK;
84 ret |= dma_bits;
87 return ret;
90 static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
93 * Enable IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
94 * when SYSCTL[RSTD]) is set for some special operations.
95 * No any impact other operation.
97 if (reg == SDHCI_INT_ENABLE)
98 val |= SDHCI_INT_BLK_GAP;
99 sdhci_be32bs_writel(host, val, reg);
102 static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
104 if (reg == SDHCI_BLOCK_SIZE) {
106 * Two last DMA bits are reserved, and first one is used for
107 * non-standard blksz of 4096 bytes that we don't support
108 * yet. So clear the DMA boundary bits.
110 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
112 sdhci_be32bs_writew(host, val, reg);
115 static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
118 * "DMA select" location is offset 0x28 in SD specification, but on
119 * P5020 or P3041, it's located at 0x29.
121 if (reg == SDHCI_HOST_CONTROL) {
122 u32 dma_bits;
125 * If host control register is not standard, exit
126 * this function
128 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL)
129 return;
131 /* DMA select is 22,23 bits in Protocol Control Register */
132 dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
133 clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
134 dma_bits);
135 val &= ~SDHCI_CTRL_DMA_MASK;
136 val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
139 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
140 if (reg == SDHCI_HOST_CONTROL)
141 val &= ~ESDHC_HOST_CONTROL_RES;
142 sdhci_be32bs_writeb(host, val, reg);
146 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
147 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
148 * and Block Gap Event(IRQSTAT[BGE]) are also set.
149 * For Continue, apply soft reset for data(SYSCTL[RSTD]);
150 * and re-issue the entire read transaction from beginning.
152 static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask)
154 u32 tmp;
155 bool applicable;
156 dma_addr_t dmastart;
157 dma_addr_t dmanow;
159 tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
160 tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
162 applicable = (intmask & SDHCI_INT_DATA_END) &&
163 (intmask & SDHCI_INT_BLK_GAP) &&
164 (tmp == VENDOR_V_23);
165 if (!applicable)
166 return;
168 host->data->error = 0;
169 dmastart = sg_dma_address(host->data->sg);
170 dmanow = dmastart + host->data->bytes_xfered;
172 * Force update to the next DMA block boundary.
174 dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
175 SDHCI_DEFAULT_BOUNDARY_SIZE;
176 host->data->bytes_xfered = dmanow - dmastart;
177 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
180 static int esdhc_of_enable_dma(struct sdhci_host *host)
182 setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
183 return 0;
186 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
188 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
190 return pltfm_host->clock;
193 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
195 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
197 return pltfm_host->clock / 256 / 16;
200 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
202 /* Workaround to reduce the clock frequency for p1010 esdhc */
203 if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
204 if (clock > 20000000)
205 clock -= 5000000;
206 if (clock > 40000000)
207 clock -= 5000000;
210 /* Set the clock */
211 esdhc_set_clock(host, clock, host->max_clk);
214 #ifdef CONFIG_PM
215 static u32 esdhc_proctl;
216 static void esdhc_of_suspend(struct sdhci_host *host)
218 esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
221 static void esdhc_of_resume(struct sdhci_host *host)
223 esdhc_of_enable_dma(host);
224 sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
226 #endif
228 static void esdhc_of_platform_init(struct sdhci_host *host)
230 u32 vvn;
232 vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
233 vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
234 if (vvn == VENDOR_V_22)
235 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
237 if (vvn > VENDOR_V_22)
238 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
241 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
243 u32 ctrl;
245 switch (width) {
246 case MMC_BUS_WIDTH_8:
247 ctrl = ESDHC_CTRL_8BITBUS;
248 break;
250 case MMC_BUS_WIDTH_4:
251 ctrl = ESDHC_CTRL_4BITBUS;
252 break;
254 default:
255 ctrl = 0;
256 break;
259 clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL,
260 ESDHC_CTRL_BUSWIDTH_MASK, ctrl);
262 return 0;
265 static const struct sdhci_ops sdhci_esdhc_ops = {
266 .read_l = esdhc_readl,
267 .read_w = esdhc_readw,
268 .read_b = esdhc_readb,
269 .write_l = esdhc_writel,
270 .write_w = esdhc_writew,
271 .write_b = esdhc_writeb,
272 .set_clock = esdhc_of_set_clock,
273 .enable_dma = esdhc_of_enable_dma,
274 .get_max_clock = esdhc_of_get_max_clock,
275 .get_min_clock = esdhc_of_get_min_clock,
276 .platform_init = esdhc_of_platform_init,
277 #ifdef CONFIG_PM
278 .platform_suspend = esdhc_of_suspend,
279 .platform_resume = esdhc_of_resume,
280 #endif
281 .adma_workaround = esdhci_of_adma_workaround,
282 .platform_bus_width = esdhc_pltfm_bus_width,
285 static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
287 * card detection could be handled via GPIO
288 * eSDHC cannot support End Attribute in NOP ADMA descriptor
290 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
291 | SDHCI_QUIRK_NO_CARD_NO_RESET
292 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
293 .ops = &sdhci_esdhc_ops,
296 static int sdhci_esdhc_probe(struct platform_device *pdev)
298 struct sdhci_host *host;
299 struct device_node *np;
300 int ret;
302 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_pdata, 0);
303 if (IS_ERR(host))
304 return PTR_ERR(host);
306 sdhci_get_of_property(pdev);
308 np = pdev->dev.of_node;
309 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) {
311 * Freescale messed up with P2020 as it has a non-standard
312 * host control register
314 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL;
317 /* call to generic mmc_of_parse to support additional capabilities */
318 mmc_of_parse(host->mmc);
319 mmc_of_parse_voltage(np, &host->ocr_mask);
321 ret = sdhci_add_host(host);
322 if (ret)
323 sdhci_pltfm_free(pdev);
325 return ret;
328 static int sdhci_esdhc_remove(struct platform_device *pdev)
330 return sdhci_pltfm_unregister(pdev);
333 static const struct of_device_id sdhci_esdhc_of_match[] = {
334 { .compatible = "fsl,mpc8379-esdhc" },
335 { .compatible = "fsl,mpc8536-esdhc" },
336 { .compatible = "fsl,esdhc" },
339 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
341 static struct platform_driver sdhci_esdhc_driver = {
342 .driver = {
343 .name = "sdhci-esdhc",
344 .owner = THIS_MODULE,
345 .of_match_table = sdhci_esdhc_of_match,
346 .pm = SDHCI_PLTFM_PMOPS,
348 .probe = sdhci_esdhc_probe,
349 .remove = sdhci_esdhc_remove,
352 module_platform_driver(sdhci_esdhc_driver);
354 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
355 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
356 "Anton Vorontsov <avorontsov@ru.mvista.com>");
357 MODULE_LICENSE("GPL v2");