drivers/mmc/host/sdhci.h

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
   3  *
   4  * Header file for Host Controller registers and I/O accessors.
   5  *
   6  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or (at
  11  * your option) any later version.
  12  */
  13 #ifndef __SDHCI_HW_H
  14 #define __SDHCI_HW_H
  15
  16 #include <linux/scatterlist.h>
  17 #include <linux/compiler.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20
  21 #include <linux/mmc/sdhci.h>
  22
  23 /*
  24  * Controller registers
  25  */
  26
  27 #define SDHCI_DMA_ADDRESS       0x00
  28 #define SDHCI_ARGUMENT2         SDHCI_DMA_ADDRESS
  29
  30 #define SDHCI_BLOCK_SIZE        0x04
  31 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  32
  33 #define SDHCI_BLOCK_COUNT       0x06
  34
  35 #define SDHCI_ARGUMENT          0x08
  36
  37 #define SDHCI_TRANSFER_MODE     0x0C
  38 #define  SDHCI_TRNS_DMA         0x01
  39 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  40 #define  SDHCI_TRNS_AUTO_CMD12  0x04
  41 #define  SDHCI_TRNS_AUTO_CMD23  0x08
  42 #define  SDHCI_TRNS_READ        0x10
  43 #define  SDHCI_TRNS_MULTI       0x20
  44
  45 #define SDHCI_COMMAND           0x0E
  46 #define  SDHCI_CMD_RESP_MASK    0x03
  47 #define  SDHCI_CMD_CRC          0x08
  48 #define  SDHCI_CMD_INDEX        0x10
  49 #define  SDHCI_CMD_DATA         0x20
  50 #define  SDHCI_CMD_ABORTCMD     0xC0
  51
  52 #define  SDHCI_CMD_RESP_NONE    0x00
  53 #define  SDHCI_CMD_RESP_LONG    0x01
  54 #define  SDHCI_CMD_RESP_SHORT   0x02
  55 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  56
  57 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  58 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  59
  60 #define SDHCI_RESPONSE          0x10
  61
  62 #define SDHCI_BUFFER            0x20
  63
  64 #define SDHCI_PRESENT_STATE     0x24
  65 #define  SDHCI_CMD_INHIBIT      0x00000001
  66 #define  SDHCI_DATA_INHIBIT     0x00000002
  67 #define  SDHCI_DOING_WRITE      0x00000100
  68 #define  SDHCI_DOING_READ       0x00000200
  69 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  70 #define  SDHCI_DATA_AVAILABLE   0x00000800
  71 #define  SDHCI_CARD_PRESENT     0x00010000
  72 #define  SDHCI_WRITE_PROTECT    0x00080000
  73 #define  SDHCI_DATA_LVL_MASK    0x00F00000
  74 #define   SDHCI_DATA_LVL_SHIFT  20
  75
  76 #define SDHCI_HOST_CONTROL      0x28
  77 #define  SDHCI_CTRL_LED         0x01
  78 #define  SDHCI_CTRL_4BITBUS     0x02
  79 #define  SDHCI_CTRL_HISPD       0x04
  80 #define  SDHCI_CTRL_DMA_MASK    0x18
  81 #define   SDHCI_CTRL_SDMA       0x00
  82 #define   SDHCI_CTRL_ADMA1      0x08
  83 #define   SDHCI_CTRL_ADMA32     0x10
  84 #define   SDHCI_CTRL_ADMA64     0x18
  85 #define   SDHCI_CTRL_8BITBUS    0x20
  86
  87 #define SDHCI_POWER_CONTROL     0x29
  88 #define  SDHCI_POWER_ON         0x01
  89 #define  SDHCI_POWER_180        0x0A
  90 #define  SDHCI_POWER_300        0x0C
  91 #define  SDHCI_POWER_330        0x0E
  92
  93 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  94
  95 #define SDHCI_WAKE_UP_CONTROL   0x2B
  96 #define  SDHCI_WAKE_ON_INT      0x01
  97 #define  SDHCI_WAKE_ON_INSERT   0x02
  98 #define  SDHCI_WAKE_ON_REMOVE   0x04
  99
 100 #define SDHCI_CLOCK_CONTROL     0x2C
 101 #define  SDHCI_DIVIDER_SHIFT    8
 102 #define  SDHCI_DIVIDER_HI_SHIFT 6
 103 #define  SDHCI_DIV_MASK 0xFF
 104 #define  SDHCI_DIV_MASK_LEN     8
 105 #define  SDHCI_DIV_HI_MASK      0x300
 106 #define  SDHCI_PROG_CLOCK_MODE  0x0020
 107 #define  SDHCI_CLOCK_CARD_EN    0x0004
 108 #define  SDHCI_CLOCK_INT_STABLE 0x0002
 109 #define  SDHCI_CLOCK_INT_EN     0x0001
 110
 111 #define SDHCI_TIMEOUT_CONTROL   0x2E
 112
 113 #define SDHCI_SOFTWARE_RESET    0x2F
 114 #define  SDHCI_RESET_ALL        0x01
 115 #define  SDHCI_RESET_CMD        0x02
 116 #define  SDHCI_RESET_DATA       0x04
 117
 118 #define SDHCI_INT_STATUS        0x30
 119 #define SDHCI_INT_ENABLE        0x34
 120 #define SDHCI_SIGNAL_ENABLE     0x38
 121 #define  SDHCI_INT_RESPONSE     0x00000001
 122 #define  SDHCI_INT_DATA_END     0x00000002
 123 #define  SDHCI_INT_BLK_GAP      0x00000004
 124 #define  SDHCI_INT_DMA_END      0x00000008
 125 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 126 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 127 #define  SDHCI_INT_CARD_INSERT  0x00000040
 128 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 129 #define  SDHCI_INT_CARD_INT     0x00000100
 130 #define  SDHCI_INT_ERROR        0x00008000
 131 #define  SDHCI_INT_TIMEOUT      0x00010000
 132 #define  SDHCI_INT_CRC          0x00020000
 133 #define  SDHCI_INT_END_BIT      0x00040000
 134 #define  SDHCI_INT_INDEX        0x00080000
 135 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 136 #define  SDHCI_INT_DATA_CRC     0x00200000
 137 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 138 #define  SDHCI_INT_BUS_POWER    0x00800000
 139 #define  SDHCI_INT_ACMD12ERR    0x01000000
 140 #define  SDHCI_INT_ADMA_ERROR   0x02000000
 141
 142 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 143 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 144
 145 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 146                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 147 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 148                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 149                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 150                 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR | \
 151                 SDHCI_INT_BLK_GAP)
 152 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 153
 154 #define SDHCI_ACMD12_ERR        0x3C
 155
 156 #define SDHCI_HOST_CONTROL2             0x3E
 157 #define  SDHCI_CTRL_UHS_MASK            0x0007
 158 #define   SDHCI_CTRL_UHS_SDR12          0x0000
 159 #define   SDHCI_CTRL_UHS_SDR25          0x0001
 160 #define   SDHCI_CTRL_UHS_SDR50          0x0002
 161 #define   SDHCI_CTRL_UHS_SDR104         0x0003
 162 #define   SDHCI_CTRL_UHS_DDR50          0x0004
 163 #define   SDHCI_CTRL_HS_SDR200          0x0005 /* reserved value in SDIO spec */
 164 #define  SDHCI_CTRL_VDD_180             0x0008
 165 #define  SDHCI_CTRL_DRV_TYPE_MASK       0x0030
 166 #define   SDHCI_CTRL_DRV_TYPE_B         0x0000
 167 #define   SDHCI_CTRL_DRV_TYPE_A         0x0010
 168 #define   SDHCI_CTRL_DRV_TYPE_C         0x0020
 169 #define   SDHCI_CTRL_DRV_TYPE_D         0x0030
 170 #define  SDHCI_CTRL_EXEC_TUNING         0x0040
 171 #define  SDHCI_CTRL_TUNED_CLK           0x0080
 172 #define  SDHCI_CTRL_PRESET_VAL_ENABLE   0x8000
 173
 174 #define SDHCI_CAPABILITIES      0x40
 175 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 176 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 177 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 178 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 179 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 180 #define  SDHCI_CLOCK_BASE_SHIFT 8
 181 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 182 #define  SDHCI_MAX_BLOCK_SHIFT  16
 183 #define  SDHCI_CAN_DO_8BIT      0x00040000
 184 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 185 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 186 #define  SDHCI_CAN_DO_HISPD     0x00200000
 187 #define  SDHCI_CAN_DO_SDMA      0x00400000
 188 #define  SDHCI_CAN_VDD_330      0x01000000
 189 #define  SDHCI_CAN_VDD_300      0x02000000
 190 #define  SDHCI_CAN_VDD_180      0x04000000
 191 #define  SDHCI_CAN_64BIT        0x10000000
 192
 193 #define  SDHCI_SUPPORT_SDR50    0x00000001
 194 #define  SDHCI_SUPPORT_SDR104   0x00000002
 195 #define  SDHCI_SUPPORT_DDR50    0x00000004
 196 #define  SDHCI_DRIVER_TYPE_A    0x00000010
 197 #define  SDHCI_DRIVER_TYPE_C    0x00000020
 198 #define  SDHCI_DRIVER_TYPE_D    0x00000040
 199 #define  SDHCI_RETUNING_TIMER_COUNT_MASK        0x00000F00
 200 #define  SDHCI_RETUNING_TIMER_COUNT_SHIFT       8
 201 #define  SDHCI_USE_SDR50_TUNING                 0x00002000
 202 #define  SDHCI_RETUNING_MODE_MASK               0x0000C000
 203 #define  SDHCI_RETUNING_MODE_SHIFT              14
 204 #define  SDHCI_CLOCK_MUL_MASK   0x00FF0000
 205 #define  SDHCI_CLOCK_MUL_SHIFT  16
 206
 207 #define SDHCI_CAPABILITIES_1    0x44
 208
 209 #define SDHCI_MAX_CURRENT               0x48
 210 #define  SDHCI_MAX_CURRENT_LIMIT        0xFF
 211 #define  SDHCI_MAX_CURRENT_330_MASK     0x0000FF
 212 #define  SDHCI_MAX_CURRENT_330_SHIFT    0
 213 #define  SDHCI_MAX_CURRENT_300_MASK     0x00FF00
 214 #define  SDHCI_MAX_CURRENT_300_SHIFT    8
 215 #define  SDHCI_MAX_CURRENT_180_MASK     0xFF0000
 216 #define  SDHCI_MAX_CURRENT_180_SHIFT    16
 217 #define   SDHCI_MAX_CURRENT_MULTIPLIER  4
 218
 219 /* 4C-4F reserved for more max current */
 220
 221 #define SDHCI_SET_ACMD12_ERROR  0x50
 222 #define SDHCI_SET_INT_ERROR     0x52
 223
 224 #define SDHCI_ADMA_ERROR        0x54
 225
 226 /* 55-57 reserved */
 227
 228 #define SDHCI_ADMA_ADDRESS      0x58
 229
 230 /* 60-FB reserved */
 231
 232 #define SDHCI_PRESET_FOR_SDR12 0x66
 233 #define SDHCI_PRESET_FOR_SDR25 0x68
 234 #define SDHCI_PRESET_FOR_SDR50 0x6A
 235 #define SDHCI_PRESET_FOR_SDR104        0x6C
 236 #define SDHCI_PRESET_FOR_DDR50 0x6E
 237 #define SDHCI_PRESET_DRV_MASK  0xC000
 238 #define SDHCI_PRESET_DRV_SHIFT  14
 239 #define SDHCI_PRESET_CLKGEN_SEL_MASK   0x400
 240 #define SDHCI_PRESET_CLKGEN_SEL_SHIFT   10
 241 #define SDHCI_PRESET_SDCLK_FREQ_MASK   0x3FF
 242 #define SDHCI_PRESET_SDCLK_FREQ_SHIFT   0
 243
 244 #define SDHCI_SLOT_INT_STATUS   0xFC
 245
 246 #define SDHCI_HOST_VERSION      0xFE
 247 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 248 #define  SDHCI_VENDOR_VER_SHIFT 8
 249 #define  SDHCI_SPEC_VER_MASK    0x00FF
 250 #define  SDHCI_SPEC_VER_SHIFT   0
 251 #define   SDHCI_SPEC_100        0
 252 #define   SDHCI_SPEC_200        1
 253 #define   SDHCI_SPEC_300        2
 254
 255 /*
 256  * End of controller registers.
 257  */
 258
 259 #define SDHCI_MAX_DIV_SPEC_200  256
 260 #define SDHCI_MAX_DIV_SPEC_300  2046
 261
 262 /*
 263  * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
 264  */
 265 #define SDHCI_DEFAULT_BOUNDARY_SIZE  (512 * 1024)
 266 #define SDHCI_DEFAULT_BOUNDARY_ARG   (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
 267
 268 struct sdhci_ops {
 269 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 270         u32             (*read_l)(struct sdhci_host *host, int reg);
 271         u16             (*read_w)(struct sdhci_host *host, int reg);
 272         u8              (*read_b)(struct sdhci_host *host, int reg);
 273         void            (*write_l)(struct sdhci_host *host, u32 val, int reg);
 274         void            (*write_w)(struct sdhci_host *host, u16 val, int reg);
 275         void            (*write_b)(struct sdhci_host *host, u8 val, int reg);
 276 #endif
 277
 278         void    (*set_clock)(struct sdhci_host *host, unsigned int clock);
 279
 280         int             (*enable_dma)(struct sdhci_host *host);
 281         unsigned int    (*get_max_clock)(struct sdhci_host *host);
 282         unsigned int    (*get_min_clock)(struct sdhci_host *host);
 283         unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
 284         int             (*platform_bus_width)(struct sdhci_host *host,
 285                                                int width);
 286         void (*platform_send_init_74_clocks)(struct sdhci_host *host,
 287                                              u8 power_mode);
 288         unsigned int    (*get_ro)(struct sdhci_host *host);
 289         void    (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
 290         void    (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
 291         int     (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
 292         void    (*hw_reset)(struct sdhci_host *host);
 293         void    (*platform_suspend)(struct sdhci_host *host);
 294         void    (*platform_resume)(struct sdhci_host *host);
 295         void    (*adma_workaround)(struct sdhci_host *host, u32 intmask);
 296         void    (*platform_init)(struct sdhci_host *host);
 297         void    (*card_event)(struct sdhci_host *host);
 298 };
 299
 300 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 301
 302 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 303 {
 304         if (unlikely(host->ops->write_l))
 305                 host->ops->write_l(host, val, reg);
 306         else
 307                 writel(val, host->ioaddr + reg);
 308 }
 309
 310 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 311 {
 312         if (unlikely(host->ops->write_w))
 313                 host->ops->write_w(host, val, reg);
 314         else
 315                 writew(val, host->ioaddr + reg);
 316 }
 317
 318 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 319 {
 320         if (unlikely(host->ops->write_b))
 321                 host->ops->write_b(host, val, reg);
 322         else
 323                 writeb(val, host->ioaddr + reg);
 324 }
 325
 326 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 327 {
 328         if (unlikely(host->ops->read_l))
 329                 return host->ops->read_l(host, reg);
 330         else
 331                 return readl(host->ioaddr + reg);
 332 }
 333
 334 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 335 {
 336         if (unlikely(host->ops->read_w))
 337                 return host->ops->read_w(host, reg);
 338         else
 339                 return readw(host->ioaddr + reg);
 340 }
 341
 342 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 343 {
 344         if (unlikely(host->ops->read_b))
 345                 return host->ops->read_b(host, reg);
 346         else
 347                 return readb(host->ioaddr + reg);
 348 }
 349
 350 #else
 351
 352 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 353 {
 354         writel(val, host->ioaddr + reg);
 355 }
 356
 357 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 358 {
 359         writew(val, host->ioaddr + reg);
 360 }
 361
 362 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 363 {
 364         writeb(val, host->ioaddr + reg);
 365 }
 366
 367 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 368 {
 369         return readl(host->ioaddr + reg);
 370 }
 371
 372 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 373 {
 374         return readw(host->ioaddr + reg);
 375 }
 376
 377 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 378 {
 379         return readb(host->ioaddr + reg);
 380 }
 381
 382 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 383
 384 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
 385         size_t priv_size);
 386 extern void sdhci_free_host(struct sdhci_host *host);
 387
 388 static inline void *sdhci_priv(struct sdhci_host *host)
 389 {
 390         return (void *)host->private;
 391 }
 392
 393 extern void sdhci_card_detect(struct sdhci_host *host);
 394 extern int sdhci_add_host(struct sdhci_host *host);
 395 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
 396
 397 #ifdef CONFIG_PM
 398 extern int sdhci_suspend_host(struct sdhci_host *host);
 399 extern int sdhci_resume_host(struct sdhci_host *host);
 400 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
 401 #endif
 402
 403 #ifdef CONFIG_PM_RUNTIME
 404 extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
 405 extern int sdhci_runtime_resume_host(struct sdhci_host *host);
 406 #endif
 407
 408 #endif /* __SDHCI_HW_H */