drivers/net/wireless/ath/wil6210/txrx.h

   1 /*
   2  * Copyright (c) 2012 Qualcomm Atheros, Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef WIL6210_TXRX_H
  18 #define WIL6210_TXRX_H
  19
  20 #define BUF_SW_OWNED    (1)
  21 #define BUF_HW_OWNED    (0)
  22
  23 /* size of max. Rx packet */
  24 #define RX_BUF_LEN      (2048)
  25 #define TX_BUF_LEN      (2048)
  26 /* how many bytes to reserve for rtap header? */
  27 #define WIL6210_RTAP_SIZE (128)
  28
  29 /* Tx/Rx path */
  30
  31 /*
  32  * Common representation of physical address in Vring
  33  */
  34 struct vring_dma_addr {
  35         __le32 addr_low;
  36         __le16 addr_high;
  37 } __packed;
  38
  39 static inline dma_addr_t wil_desc_addr(struct vring_dma_addr *addr)
  40 {
  41         return le32_to_cpu(addr->addr_low) |
  42                            ((u64)le16_to_cpu(addr->addr_high) << 32);
  43 }
  44
  45 static inline void wil_desc_addr_set(struct vring_dma_addr *addr,
  46                                      dma_addr_t pa)
  47 {
  48         addr->addr_low = cpu_to_le32(lower_32_bits(pa));
  49         addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa));
  50 }
  51
  52 /*
  53  * Tx descriptor - MAC part
  54  * [dword 0]
  55  * bit  0.. 9 : lifetime_expiry_value:10
  56  * bit     10 : interrup_en:1
  57  * bit     11 : status_en:1
  58  * bit 12..13 : txss_override:2
  59  * bit     14 : timestamp_insertion:1
  60  * bit     15 : duration_preserve:1
  61  * bit 16..21 : reserved0:6
  62  * bit 22..26 : mcs_index:5
  63  * bit     27 : mcs_en:1
  64  * bit 28..29 : reserved1:2
  65  * bit     30 : reserved2:1
  66  * bit     31 : sn_preserved:1
  67  * [dword 1]
  68  * bit  0.. 3 : pkt_mode:4
  69  * bit      4 : pkt_mode_en:1
  70  * bit  5.. 7 : reserved0:3
  71  * bit  8..13 : reserved1:6
  72  * bit     14 : reserved2:1
  73  * bit     15 : ack_policy_en:1
  74  * bit 16..19 : dst_index:4
  75  * bit     20 : dst_index_en:1
  76  * bit 21..22 : ack_policy:2
  77  * bit     23 : lifetime_en:1
  78  * bit 24..30 : max_retry:7
  79  * bit     31 : max_retry_en:1
  80  * [dword 2]
  81  * bit  0.. 7 : num_of_descriptors:8
  82  * bit  8..17 : reserved:10
  83  * bit 18..19 : l2_translation_type:2
  84  * bit     20 : snap_hdr_insertion_en:1
  85  * bit     21 : vlan_removal_en:1
  86  * bit 22..31 : reserved0:10
  87  * [dword 3]
  88  * bit  0.. 31: ucode_cmd:32
  89  */
  90 struct vring_tx_mac {
  91         u32 d[3];
  92         u32 ucode_cmd;
  93 } __packed;
  94
  95 /* TX MAC Dword 0 */
  96 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_POS 0
  97 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_LEN 10
  98 #define MAC_CFG_DESC_TX_0_LIFETIME_EXPIRY_VALUE_MSK 0x3FF
  99
 100 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_POS 10
 101 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1
 102 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_MSK 0x400
 103
 104 #define MAC_CFG_DESC_TX_0_STATUS_EN_POS 11
 105 #define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1
 106 #define MAC_CFG_DESC_TX_0_STATUS_EN_MSK 0x800
 107
 108 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_POS 12
 109 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_LEN 2
 110 #define MAC_CFG_DESC_TX_0_TXSS_OVERRIDE_MSK 0x3000
 111
 112 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_POS 14
 113 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1
 114 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_MSK 0x4000
 115
 116 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_POS 15
 117 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1
 118 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_MSK 0x8000
 119
 120 #define MAC_CFG_DESC_TX_0_MCS_INDEX_POS 22
 121 #define MAC_CFG_DESC_TX_0_MCS_INDEX_LEN 5
 122 #define MAC_CFG_DESC_TX_0_MCS_INDEX_MSK 0x7C00000
 123
 124 #define MAC_CFG_DESC_TX_0_MCS_EN_POS 27
 125 #define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1
 126 #define MAC_CFG_DESC_TX_0_MCS_EN_MSK 0x8000000
 127
 128 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_POS 31
 129 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1
 130 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_MSK 0x80000000
 131
 132 /* TX MAC Dword 1 */
 133 #define MAC_CFG_DESC_TX_1_PKT_MODE_POS 0
 134 #define MAC_CFG_DESC_TX_1_PKT_MODE_LEN 4
 135 #define MAC_CFG_DESC_TX_1_PKT_MODE_MSK 0xF
 136
 137 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_POS 4
 138 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1
 139 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_MSK 0x10
 140
 141 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_POS 15
 142 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1
 143 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_MSK 0x8000
 144
 145 #define MAC_CFG_DESC_TX_1_DST_INDEX_POS 16
 146 #define MAC_CFG_DESC_TX_1_DST_INDEX_LEN 4
 147 #define MAC_CFG_DESC_TX_1_DST_INDEX_MSK 0xF0000
 148
 149 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_POS 20
 150 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1
 151 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_MSK 0x100000
 152
 153 #define MAC_CFG_DESC_TX_1_ACK_POLICY_POS 21
 154 #define MAC_CFG_DESC_TX_1_ACK_POLICY_LEN 2
 155 #define MAC_CFG_DESC_TX_1_ACK_POLICY_MSK 0x600000
 156
 157 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_POS 23
 158 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1
 159 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_MSK 0x800000
 160
 161 #define MAC_CFG_DESC_TX_1_MAX_RETRY_POS 24
 162 #define MAC_CFG_DESC_TX_1_MAX_RETRY_LEN 7
 163 #define MAC_CFG_DESC_TX_1_MAX_RETRY_MSK 0x7F000000
 164
 165 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_POS 31
 166 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1
 167 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_MSK 0x80000000
 168
 169 /* TX MAC Dword 2 */
 170 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS 0
 171 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_LEN 8
 172 #define MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_MSK 0xFF
 173
 174 #define MAC_CFG_DESC_TX_2_RESERVED_POS 8
 175 #define MAC_CFG_DESC_TX_2_RESERVED_LEN 10
 176 #define MAC_CFG_DESC_TX_2_RESERVED_MSK 0x3FF00
 177
 178 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS 18
 179 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_LEN 2
 180 #define MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_MSK 0xC0000
 181
 182 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS 20
 183 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1
 184 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_MSK 0x100000
 185
 186 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_POS 21
 187 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1
 188 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_MSK 0x200000
 189
 190 /* TX MAC Dword 3 */
 191 #define MAC_CFG_DESC_TX_3_UCODE_CMD_POS 0
 192 #define MAC_CFG_DESC_TX_3_UCODE_CMD_LEN 32
 193 #define MAC_CFG_DESC_TX_3_UCODE_CMD_MSK 0xFFFFFFFF
 194
 195 /* TX DMA Dword 0 */
 196 #define DMA_CFG_DESC_TX_0_L4_LENGTH_POS 0
 197 #define DMA_CFG_DESC_TX_0_L4_LENGTH_LEN 8
 198 #define DMA_CFG_DESC_TX_0_L4_LENGTH_MSK 0xFF
 199
 200 #define DMA_CFG_DESC_TX_0_CMD_EOP_POS 8
 201 #define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1
 202 #define DMA_CFG_DESC_TX_0_CMD_EOP_MSK 0x100
 203
 204 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS 9
 205 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN 1
 206 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_MSK 0x200
 207
 208 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS 10
 209 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1
 210 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_MSK 0x400
 211
 212 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS 11
 213 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_LEN 2
 214 #define DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_MSK 0x1800
 215
 216 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS 13
 217 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1
 218 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_MSK 0x2000
 219
 220 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS 14
 221 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1
 222 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_MSK 0x4000
 223
 224 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS 15
 225 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1
 226 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_MSK 0x8000
 227
 228 #define DMA_CFG_DESC_TX_0_QID_POS 16
 229 #define DMA_CFG_DESC_TX_0_QID_LEN 5
 230 #define DMA_CFG_DESC_TX_0_QID_MSK 0x1F0000
 231
 232 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS 21
 233 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1
 234 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_MSK 0x200000
 235
 236 #define DMA_CFG_DESC_TX_0_L4_TYPE_POS 30
 237 #define DMA_CFG_DESC_TX_0_L4_TYPE_LEN 2
 238 #define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000 /* L4 type: 0-UDP, 2-TCP */
 239
 240
 241 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_POS 0
 242 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_LEN 7
 243 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_MAC_LEN_MSK 0x7F /* MAC hdr len */
 244
 245 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS 7
 246 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN 1
 247 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK 0x80 /* 1-IPv4, 0-IPv6 */
 248
 249
 250 #define TX_DMA_STATUS_DU         BIT(0)
 251
 252 struct vring_tx_dma {
 253         u32 d0;
 254         struct vring_dma_addr addr;
 255         u8  ip_length;
 256         u8  b11;       /* 0..6: mac_length; 7:ip_version */
 257         u8  error;     /* 0..2: err; 3..7: reserved; */
 258         u8  status;    /* 0: used; 1..7; reserved */
 259         __le16 length;
 260 } __packed;
 261
 262 /*
 263  * Rx descriptor - MAC part
 264  * [dword 0]
 265  * bit  0.. 3 : tid:4 The QoS (b3-0) TID Field
 266  * bit  4.. 6 : connection_id:3 :The Source index that  was found during
 267  *  Parsing the TA.  This field is used to  define the source of the packet
 268  * bit      7 : reserved:1
 269  * bit  8.. 9 : mac_id:2 : The MAC virtual  Ring number (always zero)
 270  * bit 10..11 : frame_type:2 : The FC Control  (b3-2) -  MPDU Type
 271  *              (management, data, control  and extension)
 272  * bit 12..15 : frame_subtype:4 : The FC Control  (b7-4) -  Frame Subtype
 273  * bit 16..27 : seq_number:12 The received Sequence number field
 274  * bit 28..31 : extended:4 extended subtype
 275  * [dword 1]
 276  * bit  0.. 3 : reserved
 277  * bit  4.. 5 : key_id:2
 278  * bit      6 : decrypt_bypass:1
 279  * bit      7 : security:1
 280  * bit  8.. 9 : ds_bits:2
 281  * bit     10 : a_msdu_present:1  from qos header
 282  * bit     11 : a_msdu_type:1  from qos header
 283  * bit     12 : a_mpdu:1  part of AMPDU aggregation
 284  * bit     13 : broadcast:1
 285  * bit     14 : mutlicast:1
 286  * bit     15 : reserved:1
 287  * bit 16..20 : rx_mac_qid:5   The Queue Identifier that the packet
 288  *                             is received from
 289  * bit 21..24 : mcs:4
 290  * bit 25..28 : mic_icr:4
 291  * bit 29..31 : reserved:3
 292  * [dword 2]
 293  * bit  0.. 2 : time_slot:3 The timeslot that the MPDU is received
 294  * bit      3 : fc_protocol_ver:1 The FC Control  (b0) - Protocol  Version
 295  * bit      4 : fc_order:1 The FC Control (b15) -Order
 296  * bit  5.. 7 : qos_ack_policy:3  The QoS (b6-5) ack policy Field
 297  * bit      8 : esop:1 The QoS (b4) ESOP field
 298  * bit      9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG  field
 299  * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved  field
 300  * bit     15 : qos_ac_constraint:1
 301  * bit 16..31 : pn_15_0:16 low 2 bytes of PN
 302  * [dword 3]
 303  * bit  0..31 : pn_47_16:32 high 4 bytes of PN
 304  */
 305 struct vring_rx_mac {
 306         u32 d0;
 307         u32 d1;
 308         u16 w4;
 309         u16 pn_15_0;
 310         u32 pn_47_16;
 311 } __packed;
 312
 313 /*
 314  * Rx descriptor - DMA part
 315  * [dword 0]
 316  * bit  0.. 7 : l4_length:8 layer 4 length
 317  * bit  8.. 9 : reserved:2
 318  * bit     10 : cmd_dma_it:1
 319  * bit 11..15 : reserved:5
 320  * bit 16..29 : phy_info_length:14
 321  * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field
 322  * [dword 1]
 323  * bit  0..31 : addr_low:32 The payload buffer low address
 324  * [dword 2]
 325  * bit  0..15 : addr_high:16 The payload buffer high address
 326  * bit 16..23 : ip_length:8
 327  * bit 24..30 : mac_length:7
 328  * bit     31 : ip_version:1
 329  * [dword 3]
 330  *  [byte 12] error
 331  *  [byte 13] status
 332  * bit      0 : du:1
 333  * bit      1 : eop:1
 334  * bit      2 : error:1
 335  * bit      3 : mi:1
 336  * bit      4 : l3_identified:1
 337  * bit      5 : l4_identified:1
 338  * bit      6 : phy_info_included:1
 339  * bit      7 : reserved:1
 340  *  [word 7] length
 341  *
 342  */
 343
 344 #define RX_DMA_D0_CMD_DMA_IT     BIT(10)
 345
 346 /* Error field, offload bits */
 347 #define RX_DMA_ERROR_L3_ERR   BIT(4)
 348 #define RX_DMA_ERROR_L4_ERR   BIT(5)
 349
 350
 351 /* Status field */
 352 #define RX_DMA_STATUS_DU         BIT(0)
 353 #define RX_DMA_STATUS_ERROR      BIT(2)
 354
 355 #define RX_DMA_STATUS_L3_IDENT   BIT(4)
 356 #define RX_DMA_STATUS_L4_IDENT   BIT(5)
 357 #define RX_DMA_STATUS_PHY_INFO   BIT(6)
 358
 359 struct vring_rx_dma {
 360         u32 d0;
 361         struct vring_dma_addr addr;
 362         u8  ip_length;
 363         u8  b11;
 364         u8  error;
 365         u8  status;
 366         __le16 length;
 367 } __packed;
 368
 369 struct vring_tx_desc {
 370         struct vring_tx_mac mac;
 371         struct vring_tx_dma dma;
 372 } __packed;
 373
 374 struct vring_rx_desc {
 375         struct vring_rx_mac mac;
 376         struct vring_rx_dma dma;
 377 } __packed;
 378
 379 union vring_desc {
 380         struct vring_tx_desc tx;
 381         struct vring_rx_desc rx;
 382 } __packed;
 383
 384 static inline int wil_rxdesc_tid(struct vring_rx_desc *d)
 385 {
 386         return WIL_GET_BITS(d->mac.d0, 0, 3);
 387 }
 388
 389 static inline int wil_rxdesc_cid(struct vring_rx_desc *d)
 390 {
 391         return WIL_GET_BITS(d->mac.d0, 4, 6);
 392 }
 393
 394 static inline int wil_rxdesc_mid(struct vring_rx_desc *d)
 395 {
 396         return WIL_GET_BITS(d->mac.d0, 8, 9);
 397 }
 398
 399 static inline int wil_rxdesc_ftype(struct vring_rx_desc *d)
 400 {
 401         return WIL_GET_BITS(d->mac.d0, 10, 11);
 402 }
 403
 404 static inline int wil_rxdesc_subtype(struct vring_rx_desc *d)
 405 {
 406         return WIL_GET_BITS(d->mac.d0, 12, 15);
 407 }
 408
 409 static inline int wil_rxdesc_seq(struct vring_rx_desc *d)
 410 {
 411         return WIL_GET_BITS(d->mac.d0, 16, 27);
 412 }
 413
 414 static inline int wil_rxdesc_ext_subtype(struct vring_rx_desc *d)
 415 {
 416         return WIL_GET_BITS(d->mac.d0, 28, 31);
 417 }
 418
 419 static inline int wil_rxdesc_ds_bits(struct vring_rx_desc *d)
 420 {
 421         return WIL_GET_BITS(d->mac.d1, 8, 9);
 422 }
 423
 424 static inline int wil_rxdesc_mcs(struct vring_rx_desc *d)
 425 {
 426         return WIL_GET_BITS(d->mac.d1, 21, 24);
 427 }
 428
 429 static inline int wil_rxdesc_phy_length(struct vring_rx_desc *d)
 430 {
 431         return WIL_GET_BITS(d->dma.d0, 16, 29);
 432 }
 433
 434 static inline struct vring_rx_desc *wil_skb_rxdesc(struct sk_buff *skb)
 435 {
 436         return (void *)skb->cb;
 437 }
 438
 439 #endif /* WIL6210_TXRX_H */