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ARM: mm: Recreate kernel mappings in early_paging_init()
[linux/fpc-iii.git] / drivers / net / wireless / ti / wl18xx / main.c
blob7aa0eb848c5a2c83cc93f120f96567cd04d5d0fa
1 /*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/ip.h>
25 #include <linux/firmware.h>
26 #include <linux/etherdevice.h>
27
28 #include "../wlcore/wlcore.h"
29 #include "../wlcore/debug.h"
30 #include "../wlcore/io.h"
31 #include "../wlcore/acx.h"
32 #include "../wlcore/tx.h"
33 #include "../wlcore/rx.h"
34 #include "../wlcore/boot.h"
35
36 #include "reg.h"
37 #include "conf.h"
38 #include "cmd.h"
39 #include "acx.h"
40 #include "tx.h"
41 #include "wl18xx.h"
42 #include "io.h"
43 #include "scan.h"
44 #include "event.h"
45 #include "debugfs.h"
46
47 #define WL18XX_RX_CHECKSUM_MASK 0x40
48
49 static char *ht_mode_param = NULL;
50 static char *board_type_param = NULL;
51 static bool checksum_param = false;
52 static int num_rx_desc_param = -1;
53
54 /* phy paramters */
55 static int dc2dc_param = -1;
56 static int n_antennas_2_param = -1;
57 static int n_antennas_5_param = -1;
58 static int low_band_component_param = -1;
59 static int low_band_component_type_param = -1;
60 static int high_band_component_param = -1;
61 static int high_band_component_type_param = -1;
62 static int pwr_limit_reference_11_abg_param = -1;
63
64 static const u8 wl18xx_rate_to_idx_2ghz[] = {
65 /* MCS rates are used only with 11n */
66 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
67 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
68 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
69 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
70 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
71 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
72 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
73 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
74 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
75 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
76 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
77 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
78 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
79 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
80 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
81 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
82
83 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
84 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
85 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
86 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
87
88 /* TI-specific rate */
89 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
90
91 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
92 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
93 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
94 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
95 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
96 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
97 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
98 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
99 };
100
101 static const u8 wl18xx_rate_to_idx_5ghz[] = {
102 /* MCS rates are used only with 11n */
103 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
104 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
105 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
106 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
107 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
108 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
109 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
110 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
111 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
112 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
113 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
114 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
115 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
116 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
117 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
118 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
119
120 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
121 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
122 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
123 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
124
125 /* TI-specific rate */
126 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
127
128 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
129 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
130 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
131 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
132 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
133 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
134 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
135 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
136 };
137
138 static const u8 *wl18xx_band_rate_to_idx[] = {
139 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
140 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
141 };
142
143 enum wl18xx_hw_rates {
144 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
145 WL18XX_CONF_HW_RXTX_RATE_MCS14,
146 WL18XX_CONF_HW_RXTX_RATE_MCS13,
147 WL18XX_CONF_HW_RXTX_RATE_MCS12,
148 WL18XX_CONF_HW_RXTX_RATE_MCS11,
149 WL18XX_CONF_HW_RXTX_RATE_MCS10,
150 WL18XX_CONF_HW_RXTX_RATE_MCS9,
151 WL18XX_CONF_HW_RXTX_RATE_MCS8,
152 WL18XX_CONF_HW_RXTX_RATE_MCS7,
153 WL18XX_CONF_HW_RXTX_RATE_MCS6,
154 WL18XX_CONF_HW_RXTX_RATE_MCS5,
155 WL18XX_CONF_HW_RXTX_RATE_MCS4,
156 WL18XX_CONF_HW_RXTX_RATE_MCS3,
157 WL18XX_CONF_HW_RXTX_RATE_MCS2,
158 WL18XX_CONF_HW_RXTX_RATE_MCS1,
159 WL18XX_CONF_HW_RXTX_RATE_MCS0,
160 WL18XX_CONF_HW_RXTX_RATE_54,
161 WL18XX_CONF_HW_RXTX_RATE_48,
162 WL18XX_CONF_HW_RXTX_RATE_36,
163 WL18XX_CONF_HW_RXTX_RATE_24,
164 WL18XX_CONF_HW_RXTX_RATE_22,
165 WL18XX_CONF_HW_RXTX_RATE_18,
166 WL18XX_CONF_HW_RXTX_RATE_12,
167 WL18XX_CONF_HW_RXTX_RATE_11,
168 WL18XX_CONF_HW_RXTX_RATE_9,
169 WL18XX_CONF_HW_RXTX_RATE_6,
170 WL18XX_CONF_HW_RXTX_RATE_5_5,
171 WL18XX_CONF_HW_RXTX_RATE_2,
172 WL18XX_CONF_HW_RXTX_RATE_1,
173 WL18XX_CONF_HW_RXTX_RATE_MAX,
174 };
175
176 static struct wlcore_conf wl18xx_conf = {
177 .sg = {
178 .params = {
179 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
180 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
181 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
182 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
183 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
184 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
185 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
186 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
187 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
188 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
189 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
190 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
191 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
192 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
193 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
194 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
195 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
196 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
197 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
198 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
199 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
200 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
201 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
202 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
203 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
204 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
205 /* active scan params */
206 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
207 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
208 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
209 /* passive scan params */
210 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
211 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
212 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
213 /* passive scan in dual antenna params */
214 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
215 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
216 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
217 /* general params */
218 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
219 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
220 [CONF_SG_BEACON_MISS_PERCENT] = 60,
221 [CONF_SG_DHCP_TIME] = 5000,
222 [CONF_SG_RXT] = 1200,
223 [CONF_SG_TXT] = 1000,
224 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
225 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
226 [CONF_SG_HV3_MAX_SERVED] = 6,
227 [CONF_SG_PS_POLL_TIMEOUT] = 10,
228 [CONF_SG_UPSD_TIMEOUT] = 10,
229 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
230 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
231 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
232 /* AP params */
233 [CONF_AP_BEACON_MISS_TX] = 3,
234 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
235 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
236 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
237 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
238 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
239 /* CTS Diluting params */
240 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
241 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
242 },
243 .state = CONF_SG_PROTECTIVE,
244 },
245 .rx = {
246 .rx_msdu_life_time = 512000,
247 .packet_detection_threshold = 0,
248 .ps_poll_timeout = 15,
249 .upsd_timeout = 15,
250 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
251 .rx_cca_threshold = 0,
252 .irq_blk_threshold = 0xFFFF,
253 .irq_pkt_threshold = 0,
254 .irq_timeout = 600,
255 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
256 },
257 .tx = {
258 .tx_energy_detection = 0,
259 .sta_rc_conf = {
260 .enabled_rates = 0,
261 .short_retry_limit = 10,
262 .long_retry_limit = 10,
263 .aflags = 0,
264 },
265 .ac_conf_count = 4,
266 .ac_conf = {
267 [CONF_TX_AC_BE] = {
268 .ac = CONF_TX_AC_BE,
269 .cw_min = 15,
270 .cw_max = 63,
271 .aifsn = 3,
272 .tx_op_limit = 0,
273 },
274 [CONF_TX_AC_BK] = {
275 .ac = CONF_TX_AC_BK,
276 .cw_min = 15,
277 .cw_max = 63,
278 .aifsn = 7,
279 .tx_op_limit = 0,
280 },
281 [CONF_TX_AC_VI] = {
282 .ac = CONF_TX_AC_VI,
283 .cw_min = 15,
284 .cw_max = 63,
285 .aifsn = CONF_TX_AIFS_PIFS,
286 .tx_op_limit = 3008,
287 },
288 [CONF_TX_AC_VO] = {
289 .ac = CONF_TX_AC_VO,
290 .cw_min = 15,
291 .cw_max = 63,
292 .aifsn = CONF_TX_AIFS_PIFS,
293 .tx_op_limit = 1504,
294 },
295 },
296 .max_tx_retries = 100,
297 .ap_aging_period = 300,
298 .tid_conf_count = 4,
299 .tid_conf = {
300 [CONF_TX_AC_BE] = {
301 .queue_id = CONF_TX_AC_BE,
302 .channel_type = CONF_CHANNEL_TYPE_EDCF,
303 .tsid = CONF_TX_AC_BE,
304 .ps_scheme = CONF_PS_SCHEME_LEGACY,
305 .ack_policy = CONF_ACK_POLICY_LEGACY,
306 .apsd_conf = {0, 0},
307 },
308 [CONF_TX_AC_BK] = {
309 .queue_id = CONF_TX_AC_BK,
310 .channel_type = CONF_CHANNEL_TYPE_EDCF,
311 .tsid = CONF_TX_AC_BK,
312 .ps_scheme = CONF_PS_SCHEME_LEGACY,
313 .ack_policy = CONF_ACK_POLICY_LEGACY,
314 .apsd_conf = {0, 0},
315 },
316 [CONF_TX_AC_VI] = {
317 .queue_id = CONF_TX_AC_VI,
318 .channel_type = CONF_CHANNEL_TYPE_EDCF,
319 .tsid = CONF_TX_AC_VI,
320 .ps_scheme = CONF_PS_SCHEME_LEGACY,
321 .ack_policy = CONF_ACK_POLICY_LEGACY,
322 .apsd_conf = {0, 0},
323 },
324 [CONF_TX_AC_VO] = {
325 .queue_id = CONF_TX_AC_VO,
326 .channel_type = CONF_CHANNEL_TYPE_EDCF,
327 .tsid = CONF_TX_AC_VO,
328 .ps_scheme = CONF_PS_SCHEME_LEGACY,
329 .ack_policy = CONF_ACK_POLICY_LEGACY,
330 .apsd_conf = {0, 0},
331 },
332 },
333 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
334 .tx_compl_timeout = 350,
335 .tx_compl_threshold = 10,
336 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
337 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
338 .tmpl_short_retry_limit = 10,
339 .tmpl_long_retry_limit = 10,
340 .tx_watchdog_timeout = 5000,
341 .slow_link_thold = 3,
342 .fast_link_thold = 30,
343 },
344 .conn = {
345 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
346 .listen_interval = 1,
347 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
348 .suspend_listen_interval = 3,
349 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
350 .bcn_filt_ie_count = 3,
351 .bcn_filt_ie = {
352 [0] = {
353 .ie = WLAN_EID_CHANNEL_SWITCH,
354 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
355 },
356 [1] = {
357 .ie = WLAN_EID_HT_OPERATION,
358 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
359 },
360 [2] = {
361 .ie = WLAN_EID_ERP_INFO,
362 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
363 },
364 },
365 .synch_fail_thold = 12,
366 .bss_lose_timeout = 400,
367 .beacon_rx_timeout = 10000,
368 .broadcast_timeout = 20000,
369 .rx_broadcast_in_ps = 1,
370 .ps_poll_threshold = 10,
371 .bet_enable = CONF_BET_MODE_ENABLE,
372 .bet_max_consecutive = 50,
373 .psm_entry_retries = 8,
374 .psm_exit_retries = 16,
375 .psm_entry_nullfunc_retries = 3,
376 .dynamic_ps_timeout = 1500,
377 .forced_ps = false,
378 .keep_alive_interval = 55000,
379 .max_listen_interval = 20,
380 .sta_sleep_auth = WL1271_PSM_ILLEGAL,
381 },
382 .itrim = {
383 .enable = false,
384 .timeout = 50000,
385 },
386 .pm_config = {
387 .host_clk_settling_time = 5000,
388 .host_fast_wakeup_support = CONF_FAST_WAKEUP_DISABLE,
389 },
390 .roam_trigger = {
391 .trigger_pacing = 1,
392 .avg_weight_rssi_beacon = 20,
393 .avg_weight_rssi_data = 10,
394 .avg_weight_snr_beacon = 20,
395 .avg_weight_snr_data = 10,
396 },
397 .scan = {
398 .min_dwell_time_active = 7500,
399 .max_dwell_time_active = 30000,
400 .min_dwell_time_active_long = 25000,
401 .max_dwell_time_active_long = 50000,
402 .dwell_time_passive = 100000,
403 .dwell_time_dfs = 150000,
404 .num_probe_reqs = 2,
405 .split_scan_timeout = 50000,
406 },
407 .sched_scan = {
408 /*
409 * Values are in TU/1000 but since sched scan FW command
410 * params are in TUs rounding up may occur.
411 */
412 .base_dwell_time = 7500,
413 .max_dwell_time_delta = 22500,
414 /* based on 250bits per probe @1Mbps */
415 .dwell_time_delta_per_probe = 2000,
416 /* based on 250bits per probe @6Mbps (plus a bit more) */
417 .dwell_time_delta_per_probe_5 = 350,
418 .dwell_time_passive = 100000,
419 .dwell_time_dfs = 150000,
420 .num_probe_reqs = 2,
421 .rssi_threshold = -90,
422 .snr_threshold = 0,
423 },
424 .ht = {
425 .rx_ba_win_size = 32,
426 .tx_ba_win_size = 64,
427 .inactivity_timeout = 10000,
428 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
429 },
430 .mem = {
431 .num_stations = 1,
432 .ssid_profiles = 1,
433 .rx_block_num = 40,
434 .tx_min_block_num = 40,
435 .dynamic_memory = 1,
436 .min_req_tx_blocks = 45,
437 .min_req_rx_blocks = 22,
438 .tx_min = 27,
439 },
440 .fm_coex = {
441 .enable = true,
442 .swallow_period = 5,
443 .n_divider_fref_set_1 = 0xff, /* default */
444 .n_divider_fref_set_2 = 12,
445 .m_divider_fref_set_1 = 0xffff,
446 .m_divider_fref_set_2 = 148, /* default */
447 .coex_pll_stabilization_time = 0xffffffff, /* default */
448 .ldo_stabilization_time = 0xffff, /* default */
449 .fm_disturbed_band_margin = 0xff, /* default */
450 .swallow_clk_diff = 0xff, /* default */
451 },
452 .rx_streaming = {
453 .duration = 150,
454 .queues = 0x1,
455 .interval = 20,
456 .always = 0,
457 },
458 .fwlog = {
459 .mode = WL12XX_FWLOG_ON_DEMAND,
460 .mem_blocks = 2,
461 .severity = 0,
462 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
463 .output = WL12XX_FWLOG_OUTPUT_HOST,
464 .threshold = 0,
465 },
466 .rate = {
467 .rate_retry_score = 32000,
468 .per_add = 8192,
469 .per_th1 = 2048,
470 .per_th2 = 4096,
471 .max_per = 8100,
472 .inverse_curiosity_factor = 5,
473 .tx_fail_low_th = 4,
474 .tx_fail_high_th = 10,
475 .per_alpha_shift = 4,
476 .per_add_shift = 13,
477 .per_beta1_shift = 10,
478 .per_beta2_shift = 8,
479 .rate_check_up = 2,
480 .rate_check_down = 12,
481 .rate_retry_policy = {
482 0x00, 0x00, 0x00, 0x00, 0x00,
483 0x00, 0x00, 0x00, 0x00, 0x00,
484 0x00, 0x00, 0x00,
485 },
486 },
487 .hangover = {
488 .recover_time = 0,
489 .hangover_period = 20,
490 .dynamic_mode = 1,
491 .early_termination_mode = 1,
492 .max_period = 20,
493 .min_period = 1,
494 .increase_delta = 1,
495 .decrease_delta = 2,
496 .quiet_time = 4,
497 .increase_time = 1,
498 .window_size = 16,
499 },
500 .recovery = {
501 .bug_on_recovery = 0,
502 .no_recovery = 0,
503 },
504 };
505
506 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
507 .ht = {
508 .mode = HT_MODE_DEFAULT,
509 },
510 .phy = {
511 .phy_standalone = 0x00,
512 .primary_clock_setting_time = 0x05,
513 .clock_valid_on_wake_up = 0x00,
514 .secondary_clock_setting_time = 0x05,
515 .board_type = BOARD_TYPE_HDK_18XX,
516 .auto_detect = 0x00,
517 .dedicated_fem = FEM_NONE,
518 .low_band_component = COMPONENT_3_WAY_SWITCH,
519 .low_band_component_type = 0x04,
520 .high_band_component = COMPONENT_2_WAY_SWITCH,
521 .high_band_component_type = 0x09,
522 .tcxo_ldo_voltage = 0x00,
523 .xtal_itrim_val = 0x04,
524 .srf_state = 0x00,
525 .io_configuration = 0x01,
526 .sdio_configuration = 0x00,
527 .settings = 0x00,
528 .enable_clpc = 0x00,
529 .enable_tx_low_pwr_on_siso_rdl = 0x00,
530 .rx_profile = 0x00,
531 .pwr_limit_reference_11_abg = 0x64,
532 .per_chan_pwr_limit_arr_11abg = {
533 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
534 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
535 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
536 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
537 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
538 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
539 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
540 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
541 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
542 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
543 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
544 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
545 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
546 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
547 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
548 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
549 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
550 .pwr_limit_reference_11p = 0x64,
551 .per_chan_bo_mode_11_abg = { 0x00, 0x00, 0x00, 0x00,
552 0x00, 0x00, 0x00, 0x00,
553 0x00, 0x00, 0x00, 0x00,
554 0x00 },
555 .per_chan_bo_mode_11_p = { 0x00, 0x00, 0x00, 0x00 },
556 .per_chan_pwr_limit_arr_11p = { 0xff, 0xff, 0xff, 0xff,
557 0xff, 0xff, 0xff },
558 .psat = 0,
559 .low_power_val = 0x08,
560 .med_power_val = 0x12,
561 .high_power_val = 0x18,
562 .low_power_val_2nd = 0x05,
563 .med_power_val_2nd = 0x0a,
564 .high_power_val_2nd = 0x14,
565 .external_pa_dc2dc = 0,
566 .number_of_assembled_ant2_4 = 2,
567 .number_of_assembled_ant5 = 1,
568 .tx_rf_margin = 1,
569 },
570 };
571
572 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
573 [PART_TOP_PRCM_ELP_SOC] = {
574 .mem = { .start = 0x00A02000, .size = 0x00010000 },
575 .reg = { .start = 0x00807000, .size = 0x00005000 },
576 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
577 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
578 },
579 [PART_DOWN] = {
580 .mem = { .start = 0x00000000, .size = 0x00014000 },
581 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
582 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
583 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
584 },
585 [PART_BOOT] = {
586 .mem = { .start = 0x00700000, .size = 0x0000030c },
587 .reg = { .start = 0x00802000, .size = 0x00014578 },
588 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
589 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
590 },
591 [PART_WORK] = {
592 .mem = { .start = 0x00800000, .size = 0x000050FC },
593 .reg = { .start = 0x00B00404, .size = 0x00001000 },
594 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
595 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
596 },
597 [PART_PHY_INIT] = {
598 .mem = { .start = WL18XX_PHY_INIT_MEM_ADDR,
599 .size = WL18XX_PHY_INIT_MEM_SIZE },
600 .reg = { .start = 0x00000000, .size = 0x00000000 },
601 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
602 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
603 },
604 };
605
606 static const int wl18xx_rtable[REG_TABLE_LEN] = {
607 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
608 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
609 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
610 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
611 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
612 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
613 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
614 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
615 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
616 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
617
618 /* data access memory addresses, used with partition translation */
619 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
620 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
621
622 /* raw data access memory addresses */
623 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
624 };
625
626 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
627 [CLOCK_CONFIG_16_2_M] = { 7, 104, 801, 4, true },
628 [CLOCK_CONFIG_16_368_M] = { 9, 132, 3751, 4, true },
629 [CLOCK_CONFIG_16_8_M] = { 7, 100, 0, 0, false },
630 [CLOCK_CONFIG_19_2_M] = { 8, 100, 0, 0, false },
631 [CLOCK_CONFIG_26_M] = { 13, 120, 0, 0, false },
632 [CLOCK_CONFIG_32_736_M] = { 9, 132, 3751, 4, true },
633 [CLOCK_CONFIG_33_6_M] = { 7, 100, 0, 0, false },
634 [CLOCK_CONFIG_38_468_M] = { 8, 100, 0, 0, false },
635 [CLOCK_CONFIG_52_M] = { 13, 120, 0, 0, false },
636 };
637
638 /* TODO: maybe move to a new header file? */
639 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw-2.bin"
640
641 static int wl18xx_identify_chip(struct wl1271 *wl)
642 {
643 int ret = 0;
644
645 switch (wl->chip.id) {
646 case CHIP_ID_185x_PG20:
647 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG20)",
648 wl->chip.id);
649 wl->sr_fw_name = WL18XX_FW_NAME;
650 /* wl18xx uses the same firmware for PLT */
651 wl->plt_fw_name = WL18XX_FW_NAME;
652 wl->quirks |= WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN |
653 WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN |
654 WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN |
655 WLCORE_QUIRK_TX_PAD_LAST_FRAME |
656 WLCORE_QUIRK_REGDOMAIN_CONF |
657 WLCORE_QUIRK_DUAL_PROBE_TMPL;
658
659 wlcore_set_min_fw_ver(wl, WL18XX_CHIP_VER,
660 WL18XX_IFTYPE_VER, WL18XX_MAJOR_VER,
661 WL18XX_SUBTYPE_VER, WL18XX_MINOR_VER,
662 /* there's no separate multi-role FW */
663 0, 0, 0, 0);
664 break;
665 case CHIP_ID_185x_PG10:
666 wl1271_warning("chip id 0x%x (185x PG10) is deprecated",
667 wl->chip.id);
668 ret = -ENODEV;
669 goto out;
670
671 default:
672 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
673 ret = -ENODEV;
674 goto out;
675 }
676
677 wl->scan_templ_id_2_4 = CMD_TEMPL_CFG_PROBE_REQ_2_4;
678 wl->scan_templ_id_5 = CMD_TEMPL_CFG_PROBE_REQ_5;
679 wl->sched_scan_templ_id_2_4 = CMD_TEMPL_PROBE_REQ_2_4_PERIODIC;
680 wl->sched_scan_templ_id_5 = CMD_TEMPL_PROBE_REQ_5_PERIODIC;
681 wl->max_channels_5 = WL18XX_MAX_CHANNELS_5GHZ;
682 wl->ba_rx_session_count_max = WL18XX_RX_BA_MAX_SESSIONS;
683 out:
684 return ret;
685 }
686
687 static int wl18xx_set_clk(struct wl1271 *wl)
688 {
689 u16 clk_freq;
690 int ret;
691
692 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
693 if (ret < 0)
694 goto out;
695
696 /* TODO: PG2: apparently we need to read the clk type */
697
698 ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
699 if (ret < 0)
700 goto out;
701
702 wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
703 wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
704 wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
705 wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
706
707 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
708 wl18xx_clk_table[clk_freq].n);
709 if (ret < 0)
710 goto out;
711
712 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
713 wl18xx_clk_table[clk_freq].m);
714 if (ret < 0)
715 goto out;
716
717 if (wl18xx_clk_table[clk_freq].swallow) {
718 /* first the 16 lower bits */
719 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
720 wl18xx_clk_table[clk_freq].q &
721 PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
722 if (ret < 0)
723 goto out;
724
725 /* then the 16 higher bits, masked out */
726 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
727 (wl18xx_clk_table[clk_freq].q >> 16) &
728 PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
729 if (ret < 0)
730 goto out;
731
732 /* first the 16 lower bits */
733 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
734 wl18xx_clk_table[clk_freq].p &
735 PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
736 if (ret < 0)
737 goto out;
738
739 /* then the 16 higher bits, masked out */
740 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
741 (wl18xx_clk_table[clk_freq].p >> 16) &
742 PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
743 } else {
744 ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
745 PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
746 }
747
748 out:
749 return ret;
750 }
751
752 static int wl18xx_boot_soft_reset(struct wl1271 *wl)
753 {
754 int ret;
755
756 /* disable Rx/Tx */
757 ret = wlcore_write32(wl, WL18XX_ENABLE, 0x0);
758 if (ret < 0)
759 goto out;
760
761 /* disable auto calibration on start*/
762 ret = wlcore_write32(wl, WL18XX_SPARE_A2, 0xffff);
763
764 out:
765 return ret;
766 }
767
768 static int wl18xx_pre_boot(struct wl1271 *wl)
769 {
770 int ret;
771
772 ret = wl18xx_set_clk(wl);
773 if (ret < 0)
774 goto out;
775
776 /* Continue the ELP wake up sequence */
777 ret = wlcore_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
778 if (ret < 0)
779 goto out;
780
781 udelay(500);
782
783 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
784 if (ret < 0)
785 goto out;
786
787 /* Disable interrupts */
788 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
789 if (ret < 0)
790 goto out;
791
792 ret = wl18xx_boot_soft_reset(wl);
793
794 out:
795 return ret;
796 }
797
798 static int wl18xx_pre_upload(struct wl1271 *wl)
799 {
800 u32 tmp;
801 int ret;
802
803 BUILD_BUG_ON(sizeof(struct wl18xx_mac_and_phy_params) >
804 WL18XX_PHY_INIT_MEM_SIZE);
805
806 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
807 if (ret < 0)
808 goto out;
809
810 /* TODO: check if this is all needed */
811 ret = wlcore_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
812 if (ret < 0)
813 goto out;
814
815 ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
816 if (ret < 0)
817 goto out;
818
819 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
820
821 ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
822 if (ret < 0)
823 goto out;
824
825 /*
826 * Workaround for FDSP code RAM corruption (needed for PG2.1
827 * and newer; for older chips it's a NOP). Change FDSP clock
828 * settings so that it's muxed to the ATGP clock instead of
829 * its own clock.
830 */
831
832 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
833 if (ret < 0)
834 goto out;
835
836 /* disable FDSP clock */
837 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
838 MEM_FDSP_CLK_120_DISABLE);
839 if (ret < 0)
840 goto out;
841
842 /* set ATPG clock toward FDSP Code RAM rather than its own clock */
843 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
844 MEM_FDSP_CODERAM_FUNC_CLK_SEL);
845 if (ret < 0)
846 goto out;
847
848 /* re-enable FDSP clock */
849 ret = wlcore_write32(wl, WL18XX_PHY_FPGA_SPARE_1,
850 MEM_FDSP_CLK_120_ENABLE);
851
852 out:
853 return ret;
854 }
855
856 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
857 {
858 struct wl18xx_priv *priv = wl->priv;
859 struct wl18xx_mac_and_phy_params *params;
860 int ret;
861
862 params = kmemdup(&priv->conf.phy, sizeof(*params), GFP_KERNEL);
863 if (!params) {
864 ret = -ENOMEM;
865 goto out;
866 }
867
868 ret = wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
869 if (ret < 0)
870 goto out;
871
872 ret = wlcore_write(wl, WL18XX_PHY_INIT_MEM_ADDR, params,
873 sizeof(*params), false);
874
875 out:
876 kfree(params);
877 return ret;
878 }
879
880 static int wl18xx_enable_interrupts(struct wl1271 *wl)
881 {
882 u32 event_mask, intr_mask;
883 int ret;
884
885 event_mask = WL18XX_ACX_EVENTS_VECTOR;
886 intr_mask = WL18XX_INTR_MASK;
887
888 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK, event_mask);
889 if (ret < 0)
890 goto out;
891
892 wlcore_enable_interrupts(wl);
893
894 ret = wlcore_write_reg(wl, REG_INTERRUPT_MASK,
895 WL1271_ACX_INTR_ALL & ~intr_mask);
896 if (ret < 0)
897 goto disable_interrupts;
898
899 return ret;
900
901 disable_interrupts:
902 wlcore_disable_interrupts(wl);
903
904 out:
905 return ret;
906 }
907
908 static int wl18xx_boot(struct wl1271 *wl)
909 {
910 int ret;
911
912 ret = wl18xx_pre_boot(wl);
913 if (ret < 0)
914 goto out;
915
916 ret = wl18xx_pre_upload(wl);
917 if (ret < 0)
918 goto out;
919
920 ret = wlcore_boot_upload_firmware(wl);
921 if (ret < 0)
922 goto out;
923
924 ret = wl18xx_set_mac_and_phy(wl);
925 if (ret < 0)
926 goto out;
927
928 wl->event_mask = BSS_LOSS_EVENT_ID |
929 SCAN_COMPLETE_EVENT_ID |
930 RSSI_SNR_TRIGGER_0_EVENT_ID |
931 PERIODIC_SCAN_COMPLETE_EVENT_ID |
932 PERIODIC_SCAN_REPORT_EVENT_ID |
933 DUMMY_PACKET_EVENT_ID |
934 PEER_REMOVE_COMPLETE_EVENT_ID |
935 BA_SESSION_RX_CONSTRAINT_EVENT_ID |
936 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID |
937 INACTIVE_STA_EVENT_ID |
938 MAX_TX_FAILURE_EVENT_ID |
939 CHANNEL_SWITCH_COMPLETE_EVENT_ID |
940 DFS_CHANNELS_CONFIG_COMPLETE_EVENT;
941
942 ret = wlcore_boot_run_firmware(wl);
943 if (ret < 0)
944 goto out;
945
946 ret = wl18xx_enable_interrupts(wl);
947
948 out:
949 return ret;
950 }
951
952 static int wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
953 void *buf, size_t len)
954 {
955 struct wl18xx_priv *priv = wl->priv;
956
957 memcpy(priv->cmd_buf, buf, len);
958 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
959
960 return wlcore_write(wl, cmd_box_addr, priv->cmd_buf,
961 WL18XX_CMD_MAX_SIZE, false);
962 }
963
964 static int wl18xx_ack_event(struct wl1271 *wl)
965 {
966 return wlcore_write_reg(wl, REG_INTERRUPT_TRIG,
967 WL18XX_INTR_TRIG_EVENT_ACK);
968 }
969
970 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
971 {
972 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
973 return (len + blk_size - 1) / blk_size + spare_blks;
974 }
975
976 static void
977 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
978 u32 blks, u32 spare_blks)
979 {
980 desc->wl18xx_mem.total_mem_blocks = blks;
981 }
982
983 static void
984 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
985 struct sk_buff *skb)
986 {
987 desc->length = cpu_to_le16(skb->len);
988
989 /* if only the last frame is to be padded, we unset this bit on Tx */
990 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME)
991 desc->wl18xx_mem.ctrl = WL18XX_TX_CTRL_NOT_PADDED;
992 else
993 desc->wl18xx_mem.ctrl = 0;
994
995 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
996 "len: %d life: %d mem: %d", desc->hlid,
997 le16_to_cpu(desc->length),
998 le16_to_cpu(desc->life_time),
999 desc->wl18xx_mem.total_mem_blocks);
1000 }
1001
1002 static enum wl_rx_buf_align
1003 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
1004 {
1005 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
1006 return WLCORE_RX_BUF_PADDED;
1007
1008 return WLCORE_RX_BUF_ALIGNED;
1009 }
1010
1011 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
1012 u32 data_len)
1013 {
1014 struct wl1271_rx_descriptor *desc = rx_data;
1015
1016 /* invalid packet */
1017 if (data_len < sizeof(*desc))
1018 return 0;
1019
1020 return data_len - sizeof(*desc);
1021 }
1022
1023 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
1024 {
1025 wl18xx_tx_immediate_complete(wl);
1026 }
1027
1028 static int wl18xx_set_host_cfg_bitmap(struct wl1271 *wl, u32 extra_mem_blk)
1029 {
1030 int ret;
1031 u32 sdio_align_size = 0;
1032 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
1033 HOST_IF_CFG_ADD_RX_ALIGNMENT;
1034
1035 /* Enable Tx SDIO padding */
1036 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
1037 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
1038 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1039 }
1040
1041 /* Enable Rx SDIO padding */
1042 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
1043 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
1044 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
1045 }
1046
1047 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
1048 sdio_align_size, extra_mem_blk,
1049 WL18XX_HOST_IF_LEN_SIZE_FIELD);
1050 if (ret < 0)
1051 return ret;
1052
1053 return 0;
1054 }
1055
1056 static int wl18xx_hw_init(struct wl1271 *wl)
1057 {
1058 int ret;
1059 struct wl18xx_priv *priv = wl->priv;
1060
1061 /* (re)init private structures. Relevant on recovery as well. */
1062 priv->last_fw_rls_idx = 0;
1063 priv->extra_spare_key_count = 0;
1064
1065 /* set the default amount of spare blocks in the bitmap */
1066 ret = wl18xx_set_host_cfg_bitmap(wl, WL18XX_TX_HW_BLOCK_SPARE);
1067 if (ret < 0)
1068 return ret;
1069
1070 if (checksum_param) {
1071 ret = wl18xx_acx_set_checksum_state(wl);
1072 if (ret != 0)
1073 return ret;
1074 }
1075
1076 return ret;
1077 }
1078
1079 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
1080 struct wl1271_tx_hw_descr *desc,
1081 struct sk_buff *skb)
1082 {
1083 u32 ip_hdr_offset;
1084 struct iphdr *ip_hdr;
1085
1086 if (!checksum_param) {
1087 desc->wl18xx_checksum_data = 0;
1088 return;
1089 }
1090
1091 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1092 desc->wl18xx_checksum_data = 0;
1093 return;
1094 }
1095
1096 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
1097 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
1098 desc->wl18xx_checksum_data = 0;
1099 return;
1100 }
1101
1102 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
1103
1104 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
1105 ip_hdr = (void *)skb_network_header(skb);
1106 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
1107 }
1108
1109 static void wl18xx_set_rx_csum(struct wl1271 *wl,
1110 struct wl1271_rx_descriptor *desc,
1111 struct sk_buff *skb)
1112 {
1113 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
1114 skb->ip_summed = CHECKSUM_UNNECESSARY;
1115 }
1116
1117 static bool wl18xx_is_mimo_supported(struct wl1271 *wl)
1118 {
1119 struct wl18xx_priv *priv = wl->priv;
1120
1121 /* only support MIMO with multiple antennas, and when SISO
1122 * is not forced through config
1123 */
1124 return (priv->conf.phy.number_of_assembled_ant2_4 >= 2) &&
1125 (priv->conf.ht.mode != HT_MODE_WIDE) &&
1126 (priv->conf.ht.mode != HT_MODE_SISO20);
1127 }
1128
1129 /*
1130 * TODO: instead of having these two functions to get the rate mask,
1131 * we should modify the wlvif->rate_set instead
1132 */
1133 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
1134 struct wl12xx_vif *wlvif)
1135 {
1136 u32 hw_rate_set = wlvif->rate_set;
1137
1138 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1139 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1140 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1141 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
1142
1143 /* we don't support MIMO in wide-channel mode */
1144 hw_rate_set &= ~CONF_TX_MIMO_RATES;
1145 } else if (wl18xx_is_mimo_supported(wl)) {
1146 wl1271_debug(DEBUG_ACX, "using MIMO channel rate mask");
1147 hw_rate_set |= CONF_TX_MIMO_RATES;
1148 }
1149
1150 return hw_rate_set;
1151 }
1152
1153 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
1154 struct wl12xx_vif *wlvif)
1155 {
1156 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
1157 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
1158 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
1159
1160 /* sanity check - we don't support this */
1161 if (WARN_ON(wlvif->band != IEEE80211_BAND_5GHZ))
1162 return 0;
1163
1164 return CONF_TX_RATE_USE_WIDE_CHAN;
1165 } else if (wl18xx_is_mimo_supported(wl) &&
1166 wlvif->band == IEEE80211_BAND_2GHZ) {
1167 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
1168 /*
1169 * we don't care about HT channel here - if a peer doesn't
1170 * support MIMO, we won't enable it in its rates
1171 */
1172 return CONF_TX_MIMO_RATES;
1173 } else {
1174 return 0;
1175 }
1176 }
1177
1178 static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
1179 {
1180 u32 fuse;
1181 s8 rom = 0, metal = 0, pg_ver = 0, rdl_ver = 0;
1182 int ret;
1183
1184 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1185 if (ret < 0)
1186 goto out;
1187
1188 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
1189 if (ret < 0)
1190 goto out;
1191
1192 pg_ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
1193 rom = (fuse & WL18XX_ROM_VER_MASK) >> WL18XX_ROM_VER_OFFSET;
1194
1195 if (rom <= 0xE)
1196 metal = (fuse & WL18XX_METAL_VER_MASK) >>
1197 WL18XX_METAL_VER_OFFSET;
1198 else
1199 metal = (fuse & WL18XX_NEW_METAL_VER_MASK) >>
1200 WL18XX_NEW_METAL_VER_OFFSET;
1201
1202 ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_2_3, &fuse);
1203 if (ret < 0)
1204 goto out;
1205
1206 rdl_ver = (fuse & WL18XX_RDL_VER_MASK) >> WL18XX_RDL_VER_OFFSET;
1207 if (rdl_ver > RDL_MAX)
1208 rdl_ver = RDL_NONE;
1209
1210 wl1271_info("wl18xx HW: RDL %d, %s, PG %x.%x (ROM %x)",
1211 rdl_ver, rdl_names[rdl_ver], pg_ver, metal, rom);
1212
1213 if (ver)
1214 *ver = pg_ver;
1215
1216 ret = wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
1217
1218 out:
1219 return ret;
1220 }
1221
1222 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
1223 static int wl18xx_conf_init(struct wl1271 *wl, struct device *dev)
1224 {
1225 struct wl18xx_priv *priv = wl->priv;
1226 struct wlcore_conf_file *conf_file;
1227 const struct firmware *fw;
1228 int ret;
1229
1230 ret = request_firmware(&fw, WL18XX_CONF_FILE_NAME, dev);
1231 if (ret < 0) {
1232 wl1271_error("could not get configuration binary %s: %d",
1233 WL18XX_CONF_FILE_NAME, ret);
1234 goto out_fallback;
1235 }
1236
1237 if (fw->size != WL18XX_CONF_SIZE) {
1238 wl1271_error("configuration binary file size is wrong, expected %zu got %zu",
1239 WL18XX_CONF_SIZE, fw->size);
1240 ret = -EINVAL;
1241 goto out;
1242 }
1243
1244 conf_file = (struct wlcore_conf_file *) fw->data;
1245
1246 if (conf_file->header.magic != cpu_to_le32(WL18XX_CONF_MAGIC)) {
1247 wl1271_error("configuration binary file magic number mismatch, "
1248 "expected 0x%0x got 0x%0x", WL18XX_CONF_MAGIC,
1249 conf_file->header.magic);
1250 ret = -EINVAL;
1251 goto out;
1252 }
1253
1254 if (conf_file->header.version != cpu_to_le32(WL18XX_CONF_VERSION)) {
1255 wl1271_error("configuration binary file version not supported, "
1256 "expected 0x%08x got 0x%08x",
1257 WL18XX_CONF_VERSION, conf_file->header.version);
1258 ret = -EINVAL;
1259 goto out;
1260 }
1261
1262 memcpy(&wl->conf, &conf_file->core, sizeof(wl18xx_conf));
1263 memcpy(&priv->conf, &conf_file->priv, sizeof(priv->conf));
1264
1265 goto out;
1266
1267 out_fallback:
1268 wl1271_warning("falling back to default config");
1269
1270 /* apply driver default configuration */
1271 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
1272 /* apply default private configuration */
1273 memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
1274
1275 /* For now we just fallback */
1276 return 0;
1277
1278 out:
1279 release_firmware(fw);
1280 return ret;
1281 }
1282
1283 static int wl18xx_plt_init(struct wl1271 *wl)
1284 {
1285 int ret;
1286
1287 /* calibrator based auto/fem detect not supported for 18xx */
1288 if (wl->plt_mode == PLT_FEM_DETECT) {
1289 wl1271_error("wl18xx_plt_init: PLT FEM_DETECT not supported");
1290 return -EINVAL;
1291 }
1292
1293 ret = wlcore_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
1294 if (ret < 0)
1295 return ret;
1296
1297 return wl->ops->boot(wl);
1298 }
1299
1300 static int wl18xx_get_mac(struct wl1271 *wl)
1301 {
1302 u32 mac1, mac2;
1303 int ret;
1304
1305 ret = wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
1306 if (ret < 0)
1307 goto out;
1308
1309 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
1310 if (ret < 0)
1311 goto out;
1312
1313 ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
1314 if (ret < 0)
1315 goto out;
1316
1317 /* these are the two parts of the BD_ADDR */
1318 wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
1319 ((mac1 & 0xff000000) >> 24);
1320 wl->fuse_nic_addr = (mac1 & 0xffffff);
1321
1322 if (!wl->fuse_oui_addr && !wl->fuse_nic_addr) {
1323 u8 mac[ETH_ALEN];
1324
1325 eth_random_addr(mac);
1326
1327 wl->fuse_oui_addr = (mac[0] << 16) + (mac[1] << 8) + mac[2];
1328 wl->fuse_nic_addr = (mac[3] << 16) + (mac[4] << 8) + mac[5];
1329 wl1271_warning("MAC address from fuse not available, using random locally administered addresses.");
1330 }
1331
1332 ret = wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
1333
1334 out:
1335 return ret;
1336 }
1337
1338 static int wl18xx_handle_static_data(struct wl1271 *wl,
1339 struct wl1271_static_data *static_data)
1340 {
1341 struct wl18xx_static_data_priv *static_data_priv =
1342 (struct wl18xx_static_data_priv *) static_data->priv;
1343
1344 strncpy(wl->chip.phy_fw_ver_str, static_data_priv->phy_version,
1345 sizeof(wl->chip.phy_fw_ver_str));
1346
1347 /* make sure the string is NULL-terminated */
1348 wl->chip.phy_fw_ver_str[sizeof(wl->chip.phy_fw_ver_str) - 1] = '\0';
1349
1350 wl1271_info("PHY firmware version: %s", static_data_priv->phy_version);
1351
1352 return 0;
1353 }
1354
1355 static int wl18xx_get_spare_blocks(struct wl1271 *wl, bool is_gem)
1356 {
1357 struct wl18xx_priv *priv = wl->priv;
1358
1359 /* If we have keys requiring extra spare, indulge them */
1360 if (priv->extra_spare_key_count)
1361 return WL18XX_TX_HW_EXTRA_BLOCK_SPARE;
1362
1363 return WL18XX_TX_HW_BLOCK_SPARE;
1364 }
1365
1366 static int wl18xx_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
1367 struct ieee80211_vif *vif,
1368 struct ieee80211_sta *sta,
1369 struct ieee80211_key_conf *key_conf)
1370 {
1371 struct wl18xx_priv *priv = wl->priv;
1372 bool change_spare = false, special_enc;
1373 int ret;
1374
1375 wl1271_debug(DEBUG_CRYPT, "extra spare keys before: %d",
1376 priv->extra_spare_key_count);
1377
1378 special_enc = key_conf->cipher == WL1271_CIPHER_SUITE_GEM ||
1379 key_conf->cipher == WLAN_CIPHER_SUITE_TKIP;
1380
1381 ret = wlcore_set_key(wl, cmd, vif, sta, key_conf);
1382 if (ret < 0)
1383 goto out;
1384
1385 /*
1386 * when adding the first or removing the last GEM/TKIP key,
1387 * we have to adjust the number of spare blocks.
1388 */
1389 if (special_enc) {
1390 if (cmd == SET_KEY) {
1391 /* first key */
1392 change_spare = (priv->extra_spare_key_count == 0);
1393 priv->extra_spare_key_count++;
1394 } else if (cmd == DISABLE_KEY) {
1395 /* last key */
1396 change_spare = (priv->extra_spare_key_count == 1);
1397 priv->extra_spare_key_count--;
1398 }
1399 }
1400
1401 wl1271_debug(DEBUG_CRYPT, "extra spare keys after: %d",
1402 priv->extra_spare_key_count);
1403
1404 if (!change_spare)
1405 goto out;
1406
1407 /* key is now set, change the spare blocks */
1408 if (priv->extra_spare_key_count)
1409 ret = wl18xx_set_host_cfg_bitmap(wl,
1410 WL18XX_TX_HW_EXTRA_BLOCK_SPARE);
1411 else
1412 ret = wl18xx_set_host_cfg_bitmap(wl,
1413 WL18XX_TX_HW_BLOCK_SPARE);
1414
1415 out:
1416 return ret;
1417 }
1418
1419 static u32 wl18xx_pre_pkt_send(struct wl1271 *wl,
1420 u32 buf_offset, u32 last_len)
1421 {
1422 if (wl->quirks & WLCORE_QUIRK_TX_PAD_LAST_FRAME) {
1423 struct wl1271_tx_hw_descr *last_desc;
1424
1425 /* get the last TX HW descriptor written to the aggr buf */
1426 last_desc = (struct wl1271_tx_hw_descr *)(wl->aggr_buf +
1427 buf_offset - last_len);
1428
1429 /* the last frame is padded up to an SDIO block */
1430 last_desc->wl18xx_mem.ctrl &= ~WL18XX_TX_CTRL_NOT_PADDED;
1431 return ALIGN(buf_offset, WL12XX_BUS_BLOCK_SIZE);
1432 }
1433
1434 /* no modifications */
1435 return buf_offset;
1436 }
1437
1438 static void wl18xx_sta_rc_update(struct wl1271 *wl,
1439 struct wl12xx_vif *wlvif,
1440 struct ieee80211_sta *sta,
1441 u32 changed)
1442 {
1443 bool wide = sta->bandwidth >= IEEE80211_STA_RX_BW_40;
1444
1445 wl1271_debug(DEBUG_MAC80211, "mac80211 sta_rc_update wide %d", wide);
1446
1447 if (!(changed & IEEE80211_RC_BW_CHANGED))
1448 return;
1449
1450 mutex_lock(&wl->mutex);
1451
1452 /* sanity */
1453 if (WARN_ON(wlvif->bss_type != BSS_TYPE_STA_BSS))
1454 goto out;
1455
1456 /* ignore the change before association */
1457 if (!test_bit(WLVIF_FLAG_STA_ASSOCIATED, &wlvif->flags))
1458 goto out;
1459
1460 /*
1461 * If we started out as wide, we can change the operation mode. If we
1462 * thought this was a 20mhz AP, we have to reconnect
1463 */
1464 if (wlvif->sta.role_chan_type == NL80211_CHAN_HT40MINUS ||
1465 wlvif->sta.role_chan_type == NL80211_CHAN_HT40PLUS)
1466 wl18xx_acx_peer_ht_operation_mode(wl, wlvif->sta.hlid, wide);
1467 else
1468 ieee80211_connection_loss(wl12xx_wlvif_to_vif(wlvif));
1469
1470 out:
1471 mutex_unlock(&wl->mutex);
1472 }
1473
1474 static int wl18xx_set_peer_cap(struct wl1271 *wl,
1475 struct ieee80211_sta_ht_cap *ht_cap,
1476 bool allow_ht_operation,
1477 u32 rate_set, u8 hlid)
1478 {
1479 return wl18xx_acx_set_peer_cap(wl, ht_cap, allow_ht_operation,
1480 rate_set, hlid);
1481 }
1482
1483 static bool wl18xx_lnk_high_prio(struct wl1271 *wl, u8 hlid,
1484 struct wl1271_link *lnk)
1485 {
1486 u8 thold;
1487 struct wl18xx_fw_status_priv *status_priv =
1488 (struct wl18xx_fw_status_priv *)wl->fw_status_2->priv;
1489 u32 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1490
1491 /* suspended links are never high priority */
1492 if (test_bit(hlid, (unsigned long *)&suspend_bitmap))
1493 return false;
1494
1495 /* the priority thresholds are taken from FW */
1496 if (test_bit(hlid, (unsigned long *)&wl->fw_fast_lnk_map) &&
1497 !test_bit(hlid, (unsigned long *)&wl->ap_fw_ps_map))
1498 thold = status_priv->tx_fast_link_prio_threshold;
1499 else
1500 thold = status_priv->tx_slow_link_prio_threshold;
1501
1502 return lnk->allocated_pkts < thold;
1503 }
1504
1505 static bool wl18xx_lnk_low_prio(struct wl1271 *wl, u8 hlid,
1506 struct wl1271_link *lnk)
1507 {
1508 u8 thold;
1509 struct wl18xx_fw_status_priv *status_priv =
1510 (struct wl18xx_fw_status_priv *)wl->fw_status_2->priv;
1511 u32 suspend_bitmap = le32_to_cpu(status_priv->link_suspend_bitmap);
1512
1513 if (test_bit(hlid, (unsigned long *)&suspend_bitmap))
1514 thold = status_priv->tx_suspend_threshold;
1515 else if (test_bit(hlid, (unsigned long *)&wl->fw_fast_lnk_map) &&
1516 !test_bit(hlid, (unsigned long *)&wl->ap_fw_ps_map))
1517 thold = status_priv->tx_fast_stop_threshold;
1518 else
1519 thold = status_priv->tx_slow_stop_threshold;
1520
1521 return lnk->allocated_pkts < thold;
1522 }
1523
1524 static int wl18xx_setup(struct wl1271 *wl);
1525
1526 static struct wlcore_ops wl18xx_ops = {
1527 .setup = wl18xx_setup,
1528 .identify_chip = wl18xx_identify_chip,
1529 .boot = wl18xx_boot,
1530 .plt_init = wl18xx_plt_init,
1531 .trigger_cmd = wl18xx_trigger_cmd,
1532 .ack_event = wl18xx_ack_event,
1533 .wait_for_event = wl18xx_wait_for_event,
1534 .process_mailbox_events = wl18xx_process_mailbox_events,
1535 .calc_tx_blocks = wl18xx_calc_tx_blocks,
1536 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1537 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1538 .get_rx_buf_align = wl18xx_get_rx_buf_align,
1539 .get_rx_packet_len = wl18xx_get_rx_packet_len,
1540 .tx_immediate_compl = wl18xx_tx_immediate_completion,
1541 .tx_delayed_compl = NULL,
1542 .hw_init = wl18xx_hw_init,
1543 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1544 .get_pg_ver = wl18xx_get_pg_ver,
1545 .set_rx_csum = wl18xx_set_rx_csum,
1546 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1547 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1548 .get_mac = wl18xx_get_mac,
1549 .debugfs_init = wl18xx_debugfs_add_files,
1550 .scan_start = wl18xx_scan_start,
1551 .scan_stop = wl18xx_scan_stop,
1552 .sched_scan_start = wl18xx_sched_scan_start,
1553 .sched_scan_stop = wl18xx_scan_sched_scan_stop,
1554 .handle_static_data = wl18xx_handle_static_data,
1555 .get_spare_blocks = wl18xx_get_spare_blocks,
1556 .set_key = wl18xx_set_key,
1557 .channel_switch = wl18xx_cmd_channel_switch,
1558 .pre_pkt_send = wl18xx_pre_pkt_send,
1559 .sta_rc_update = wl18xx_sta_rc_update,
1560 .set_peer_cap = wl18xx_set_peer_cap,
1561 .lnk_high_prio = wl18xx_lnk_high_prio,
1562 .lnk_low_prio = wl18xx_lnk_low_prio,
1563 };
1564
1565 /* HT cap appropriate for wide channels in 2Ghz */
1566 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_2ghz = {
1567 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1568 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40 |
1569 IEEE80211_HT_CAP_GRN_FLD,
1570 .ht_supported = true,
1571 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1572 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1573 .mcs = {
1574 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1575 .rx_highest = cpu_to_le16(150),
1576 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1577 },
1578 };
1579
1580 /* HT cap appropriate for wide channels in 5Ghz */
1581 static struct ieee80211_sta_ht_cap wl18xx_siso40_ht_cap_5ghz = {
1582 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1583 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
1584 IEEE80211_HT_CAP_GRN_FLD,
1585 .ht_supported = true,
1586 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1587 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1588 .mcs = {
1589 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1590 .rx_highest = cpu_to_le16(150),
1591 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1592 },
1593 };
1594
1595 /* HT cap appropriate for SISO 20 */
1596 static struct ieee80211_sta_ht_cap wl18xx_siso20_ht_cap = {
1597 .cap = IEEE80211_HT_CAP_SGI_20 |
1598 IEEE80211_HT_CAP_GRN_FLD,
1599 .ht_supported = true,
1600 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1601 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1602 .mcs = {
1603 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1604 .rx_highest = cpu_to_le16(72),
1605 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1606 },
1607 };
1608
1609 /* HT cap appropriate for MIMO rates in 20mhz channel */
1610 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap_2ghz = {
1611 .cap = IEEE80211_HT_CAP_SGI_20 |
1612 IEEE80211_HT_CAP_GRN_FLD,
1613 .ht_supported = true,
1614 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1615 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1616 .mcs = {
1617 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1618 .rx_highest = cpu_to_le16(144),
1619 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1620 },
1621 };
1622
1623 static int wl18xx_setup(struct wl1271 *wl)
1624 {
1625 struct wl18xx_priv *priv = wl->priv;
1626 int ret;
1627
1628 wl->rtable = wl18xx_rtable;
1629 wl->num_tx_desc = WL18XX_NUM_TX_DESCRIPTORS;
1630 wl->num_rx_desc = WL18XX_NUM_RX_DESCRIPTORS;
1631 wl->num_channels = 2;
1632 wl->num_mac_addr = WL18XX_NUM_MAC_ADDRESSES;
1633 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1634 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1635 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1636 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1637 wl->stats.fw_stats_len = sizeof(struct wl18xx_acx_statistics);
1638 wl->static_data_priv_len = sizeof(struct wl18xx_static_data_priv);
1639
1640 if (num_rx_desc_param != -1)
1641 wl->num_rx_desc = num_rx_desc_param;
1642
1643 ret = wl18xx_conf_init(wl, wl->dev);
1644 if (ret < 0)
1645 return ret;
1646
1647 /* If the module param is set, update it in conf */
1648 if (board_type_param) {
1649 if (!strcmp(board_type_param, "fpga")) {
1650 priv->conf.phy.board_type = BOARD_TYPE_FPGA_18XX;
1651 } else if (!strcmp(board_type_param, "hdk")) {
1652 priv->conf.phy.board_type = BOARD_TYPE_HDK_18XX;
1653 } else if (!strcmp(board_type_param, "dvp")) {
1654 priv->conf.phy.board_type = BOARD_TYPE_DVP_18XX;
1655 } else if (!strcmp(board_type_param, "evb")) {
1656 priv->conf.phy.board_type = BOARD_TYPE_EVB_18XX;
1657 } else if (!strcmp(board_type_param, "com8")) {
1658 priv->conf.phy.board_type = BOARD_TYPE_COM8_18XX;
1659 } else {
1660 wl1271_error("invalid board type '%s'",
1661 board_type_param);
1662 return -EINVAL;
1663 }
1664 }
1665
1666 if (priv->conf.phy.board_type >= NUM_BOARD_TYPES) {
1667 wl1271_error("invalid board type '%d'",
1668 priv->conf.phy.board_type);
1669 return -EINVAL;
1670 }
1671
1672 if (low_band_component_param != -1)
1673 priv->conf.phy.low_band_component = low_band_component_param;
1674 if (low_band_component_type_param != -1)
1675 priv->conf.phy.low_band_component_type =
1676 low_band_component_type_param;
1677 if (high_band_component_param != -1)
1678 priv->conf.phy.high_band_component = high_band_component_param;
1679 if (high_band_component_type_param != -1)
1680 priv->conf.phy.high_band_component_type =
1681 high_band_component_type_param;
1682 if (pwr_limit_reference_11_abg_param != -1)
1683 priv->conf.phy.pwr_limit_reference_11_abg =
1684 pwr_limit_reference_11_abg_param;
1685 if (n_antennas_2_param != -1)
1686 priv->conf.phy.number_of_assembled_ant2_4 = n_antennas_2_param;
1687 if (n_antennas_5_param != -1)
1688 priv->conf.phy.number_of_assembled_ant5 = n_antennas_5_param;
1689 if (dc2dc_param != -1)
1690 priv->conf.phy.external_pa_dc2dc = dc2dc_param;
1691
1692 if (ht_mode_param) {
1693 if (!strcmp(ht_mode_param, "default"))
1694 priv->conf.ht.mode = HT_MODE_DEFAULT;
1695 else if (!strcmp(ht_mode_param, "wide"))
1696 priv->conf.ht.mode = HT_MODE_WIDE;
1697 else if (!strcmp(ht_mode_param, "siso20"))
1698 priv->conf.ht.mode = HT_MODE_SISO20;
1699 else {
1700 wl1271_error("invalid ht_mode '%s'", ht_mode_param);
1701 return -EINVAL;
1702 }
1703 }
1704
1705 if (priv->conf.ht.mode == HT_MODE_DEFAULT) {
1706 /*
1707 * Only support mimo with multiple antennas. Fall back to
1708 * siso40.
1709 */
1710 if (wl18xx_is_mimo_supported(wl))
1711 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1712 &wl18xx_mimo_ht_cap_2ghz);
1713 else
1714 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1715 &wl18xx_siso40_ht_cap_2ghz);
1716
1717 /* 5Ghz is always wide */
1718 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1719 &wl18xx_siso40_ht_cap_5ghz);
1720 } else if (priv->conf.ht.mode == HT_MODE_WIDE) {
1721 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1722 &wl18xx_siso40_ht_cap_2ghz);
1723 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1724 &wl18xx_siso40_ht_cap_5ghz);
1725 } else if (priv->conf.ht.mode == HT_MODE_SISO20) {
1726 wlcore_set_ht_cap(wl, IEEE80211_BAND_2GHZ,
1727 &wl18xx_siso20_ht_cap);
1728 wlcore_set_ht_cap(wl, IEEE80211_BAND_5GHZ,
1729 &wl18xx_siso20_ht_cap);
1730 }
1731
1732 if (!checksum_param) {
1733 wl18xx_ops.set_rx_csum = NULL;
1734 wl18xx_ops.init_vif = NULL;
1735 }
1736
1737 /* Enable 11a Band only if we have 5G antennas */
1738 wl->enable_11a = (priv->conf.phy.number_of_assembled_ant5 != 0);
1739
1740 return 0;
1741 }
1742
1743 static int wl18xx_probe(struct platform_device *pdev)
1744 {
1745 struct wl1271 *wl;
1746 struct ieee80211_hw *hw;
1747 int ret;
1748
1749 hw = wlcore_alloc_hw(sizeof(struct wl18xx_priv),
1750 WL18XX_AGGR_BUFFER_SIZE,
1751 sizeof(struct wl18xx_event_mailbox));
1752 if (IS_ERR(hw)) {
1753 wl1271_error("can't allocate hw");
1754 ret = PTR_ERR(hw);
1755 goto out;
1756 }
1757
1758 wl = hw->priv;
1759 wl->ops = &wl18xx_ops;
1760 wl->ptable = wl18xx_ptable;
1761 ret = wlcore_probe(wl, pdev);
1762 if (ret)
1763 goto out_free;
1764
1765 return ret;
1766
1767 out_free:
1768 wlcore_free_hw(wl);
1769 out:
1770 return ret;
1771 }
1772
1773 static const struct platform_device_id wl18xx_id_table[] = {
1774 { "wl18xx", 0 },
1775 { } /* Terminating Entry */
1776 };
1777 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1778
1779 static struct platform_driver wl18xx_driver = {
1780 .probe = wl18xx_probe,
1781 .remove = wlcore_remove,
1782 .id_table = wl18xx_id_table,
1783 .driver = {
1784 .name = "wl18xx_driver",
1785 .owner = THIS_MODULE,
1786 }
1787 };
1788
1789 module_platform_driver(wl18xx_driver);
1790 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1791 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or siso20");
1792
1793 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1794 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk (default), evb, com8 or "
1795 "dvp");
1796
1797 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1798 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to false)");
1799
1800 module_param_named(dc2dc, dc2dc_param, int, S_IRUSR);
1801 MODULE_PARM_DESC(dc2dc, "External DC2DC: u8 (defaults to 0)");
1802
1803 module_param_named(n_antennas_2, n_antennas_2_param, int, S_IRUSR);
1804 MODULE_PARM_DESC(n_antennas_2,
1805 "Number of installed 2.4GHz antennas: 1 (default) or 2");
1806
1807 module_param_named(n_antennas_5, n_antennas_5_param, int, S_IRUSR);
1808 MODULE_PARM_DESC(n_antennas_5,
1809 "Number of installed 5GHz antennas: 1 (default) or 2");
1810
1811 module_param_named(low_band_component, low_band_component_param, int,
1812 S_IRUSR);
1813 MODULE_PARM_DESC(low_band_component, "Low band component: u8 "
1814 "(default is 0x01)");
1815
1816 module_param_named(low_band_component_type, low_band_component_type_param,
1817 int, S_IRUSR);
1818 MODULE_PARM_DESC(low_band_component_type, "Low band component type: u8 "
1819 "(default is 0x05 or 0x06 depending on the board_type)");
1820
1821 module_param_named(high_band_component, high_band_component_param, int,
1822 S_IRUSR);
1823 MODULE_PARM_DESC(high_band_component, "High band component: u8, "
1824 "(default is 0x01)");
1825
1826 module_param_named(high_band_component_type, high_band_component_type_param,
1827 int, S_IRUSR);
1828 MODULE_PARM_DESC(high_band_component_type, "High band component type: u8 "
1829 "(default is 0x09)");
1830
1831 module_param_named(pwr_limit_reference_11_abg,
1832 pwr_limit_reference_11_abg_param, int, S_IRUSR);
1833 MODULE_PARM_DESC(pwr_limit_reference_11_abg, "Power limit reference: u8 "
1834 "(default is 0xc8)");
1835
1836 module_param_named(num_rx_desc,
1837 num_rx_desc_param, int, S_IRUSR);
1838 MODULE_PARM_DESC(num_rx_desc_param,
1839 "Number of Rx descriptors: u8 (default is 32)");
1840
1841 MODULE_LICENSE("GPL v2");
1842 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1843 MODULE_FIRMWARE(WL18XX_FW_NAME);
Linux with added FPC-III support