2 * ARM Ltd. Juno Platform
4 * Copyright (c) 2013-2014 ARM Ltd.
6 * This file is licensed under a dual GPLv2 or BSD license.
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 model = "ARM Juno development board (r0)";
15 compatible = "arm,juno", "arm,vexpress";
16 interrupt-parent = <&gic>;
25 stdout-path = "serial0:115200n8";
29 compatible = "arm,psci-0.2";
64 compatible = "arm,cortex-a57","arm,armv8";
67 enable-method = "psci";
68 next-level-cache = <&A57_L2>;
69 clocks = <&scpi_dvfs 0>;
73 compatible = "arm,cortex-a57","arm,armv8";
76 enable-method = "psci";
77 next-level-cache = <&A57_L2>;
78 clocks = <&scpi_dvfs 0>;
82 compatible = "arm,cortex-a53","arm,armv8";
85 enable-method = "psci";
86 next-level-cache = <&A53_L2>;
87 clocks = <&scpi_dvfs 1>;
91 compatible = "arm,cortex-a53","arm,armv8";
94 enable-method = "psci";
95 next-level-cache = <&A53_L2>;
96 clocks = <&scpi_dvfs 1>;
100 compatible = "arm,cortex-a53","arm,armv8";
103 enable-method = "psci";
104 next-level-cache = <&A53_L2>;
105 clocks = <&scpi_dvfs 1>;
109 compatible = "arm,cortex-a53","arm,armv8";
112 enable-method = "psci";
113 next-level-cache = <&A53_L2>;
114 clocks = <&scpi_dvfs 1>;
118 compatible = "cache";
122 compatible = "cache";
127 compatible = "arm,cortex-a57-pmu";
128 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-affinity = <&A57_0>,
135 compatible = "arm,cortex-a53-pmu";
136 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
140 interrupt-affinity = <&A53_0>,
146 #include "juno-base.dtsi"