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mm: hugetlb: fix hugepage memory leak caused by wrong reserve count
[linux/fpc-iii.git] / arch / sparc / kernel / pci.c
blobbadf0951d73c8f2d875aa5cbc093caef04616aeb
1 /* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11 #include <linux/export.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
21 #include <linux/of.h>
22 #include <linux/of_device.h>
23
24 #include <asm/uaccess.h>
25 #include <asm/pgtable.h>
26 #include <asm/irq.h>
27 #include <asm/prom.h>
28 #include <asm/apb.h>
29
30 #include "pci_impl.h"
31 #include "kernel.h"
32
33 /* List of all PCI controllers found in the system. */
34 struct pci_pbm_info *pci_pbm_root = NULL;
35
36 /* Each PBM found gets a unique index. */
37 int pci_num_pbms = 0;
38
39 volatile int pci_poke_in_progress;
40 volatile int pci_poke_cpu = -1;
41 volatile int pci_poke_faulted;
42
43 static DEFINE_SPINLOCK(pci_poke_lock);
44
45 void pci_config_read8(u8 *addr, u8 *ret)
46 {
47 unsigned long flags;
48 u8 byte;
49
50 spin_lock_irqsave(&pci_poke_lock, flags);
51 pci_poke_cpu = smp_processor_id();
52 pci_poke_in_progress = 1;
53 pci_poke_faulted = 0;
54 __asm__ __volatile__("membar #Sync\n\t"
55 "lduba [%1] %2, %0\n\t"
56 "membar #Sync"
57 : "=r" (byte)
58 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
59 : "memory");
60 pci_poke_in_progress = 0;
61 pci_poke_cpu = -1;
62 if (!pci_poke_faulted)
63 *ret = byte;
64 spin_unlock_irqrestore(&pci_poke_lock, flags);
65 }
66
67 void pci_config_read16(u16 *addr, u16 *ret)
68 {
69 unsigned long flags;
70 u16 word;
71
72 spin_lock_irqsave(&pci_poke_lock, flags);
73 pci_poke_cpu = smp_processor_id();
74 pci_poke_in_progress = 1;
75 pci_poke_faulted = 0;
76 __asm__ __volatile__("membar #Sync\n\t"
77 "lduha [%1] %2, %0\n\t"
78 "membar #Sync"
79 : "=r" (word)
80 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
81 : "memory");
82 pci_poke_in_progress = 0;
83 pci_poke_cpu = -1;
84 if (!pci_poke_faulted)
85 *ret = word;
86 spin_unlock_irqrestore(&pci_poke_lock, flags);
87 }
88
89 void pci_config_read32(u32 *addr, u32 *ret)
90 {
91 unsigned long flags;
92 u32 dword;
93
94 spin_lock_irqsave(&pci_poke_lock, flags);
95 pci_poke_cpu = smp_processor_id();
96 pci_poke_in_progress = 1;
97 pci_poke_faulted = 0;
98 __asm__ __volatile__("membar #Sync\n\t"
99 "lduwa [%1] %2, %0\n\t"
100 "membar #Sync"
101 : "=r" (dword)
102 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
103 : "memory");
104 pci_poke_in_progress = 0;
105 pci_poke_cpu = -1;
106 if (!pci_poke_faulted)
107 *ret = dword;
108 spin_unlock_irqrestore(&pci_poke_lock, flags);
109 }
110
111 void pci_config_write8(u8 *addr, u8 val)
112 {
113 unsigned long flags;
114
115 spin_lock_irqsave(&pci_poke_lock, flags);
116 pci_poke_cpu = smp_processor_id();
117 pci_poke_in_progress = 1;
118 pci_poke_faulted = 0;
119 __asm__ __volatile__("membar #Sync\n\t"
120 "stba %0, [%1] %2\n\t"
121 "membar #Sync"
122 : /* no outputs */
123 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
124 : "memory");
125 pci_poke_in_progress = 0;
126 pci_poke_cpu = -1;
127 spin_unlock_irqrestore(&pci_poke_lock, flags);
128 }
129
130 void pci_config_write16(u16 *addr, u16 val)
131 {
132 unsigned long flags;
133
134 spin_lock_irqsave(&pci_poke_lock, flags);
135 pci_poke_cpu = smp_processor_id();
136 pci_poke_in_progress = 1;
137 pci_poke_faulted = 0;
138 __asm__ __volatile__("membar #Sync\n\t"
139 "stha %0, [%1] %2\n\t"
140 "membar #Sync"
141 : /* no outputs */
142 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
143 : "memory");
144 pci_poke_in_progress = 0;
145 pci_poke_cpu = -1;
146 spin_unlock_irqrestore(&pci_poke_lock, flags);
147 }
148
149 void pci_config_write32(u32 *addr, u32 val)
150 {
151 unsigned long flags;
152
153 spin_lock_irqsave(&pci_poke_lock, flags);
154 pci_poke_cpu = smp_processor_id();
155 pci_poke_in_progress = 1;
156 pci_poke_faulted = 0;
157 __asm__ __volatile__("membar #Sync\n\t"
158 "stwa %0, [%1] %2\n\t"
159 "membar #Sync"
160 : /* no outputs */
161 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
162 : "memory");
163 pci_poke_in_progress = 0;
164 pci_poke_cpu = -1;
165 spin_unlock_irqrestore(&pci_poke_lock, flags);
166 }
167
168 static int ofpci_verbose;
169
170 static int __init ofpci_debug(char *str)
171 {
172 int val = 0;
173
174 get_option(&str, &val);
175 if (val)
176 ofpci_verbose = 1;
177 return 1;
178 }
179
180 __setup("ofpci_debug=", ofpci_debug);
181
182 static unsigned long pci_parse_of_flags(u32 addr0)
183 {
184 unsigned long flags = 0;
185
186 if (addr0 & 0x02000000) {
187 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
188 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
189 if (addr0 & 0x01000000)
190 flags |= IORESOURCE_MEM_64
191 | PCI_BASE_ADDRESS_MEM_TYPE_64;
192 if (addr0 & 0x40000000)
193 flags |= IORESOURCE_PREFETCH
194 | PCI_BASE_ADDRESS_MEM_PREFETCH;
195 } else if (addr0 & 0x01000000)
196 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
197 return flags;
198 }
199
200 /* The of_device layer has translated all of the assigned-address properties
201 * into physical address resources, we only have to figure out the register
202 * mapping.
203 */
204 static void pci_parse_of_addrs(struct platform_device *op,
205 struct device_node *node,
206 struct pci_dev *dev)
207 {
208 struct resource *op_res;
209 const u32 *addrs;
210 int proplen;
211
212 addrs = of_get_property(node, "assigned-addresses", &proplen);
213 if (!addrs)
214 return;
215 if (ofpci_verbose)
216 printk(" parse addresses (%d bytes) @ %p\n",
217 proplen, addrs);
218 op_res = &op->resource[0];
219 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
220 struct resource *res;
221 unsigned long flags;
222 int i;
223
224 flags = pci_parse_of_flags(addrs[0]);
225 if (!flags)
226 continue;
227 i = addrs[0] & 0xff;
228 if (ofpci_verbose)
229 printk(" start: %llx, end: %llx, i: %x\n",
230 op_res->start, op_res->end, i);
231
232 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
233 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
234 } else if (i == dev->rom_base_reg) {
235 res = &dev->resource[PCI_ROM_RESOURCE];
236 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
237 } else {
238 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
239 continue;
240 }
241 res->start = op_res->start;
242 res->end = op_res->end;
243 res->flags = flags;
244 res->name = pci_name(dev);
245 }
246 }
247
248 static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
249 struct device_node *node,
250 struct pci_bus *bus, int devfn)
251 {
252 struct dev_archdata *sd;
253 struct platform_device *op;
254 struct pci_dev *dev;
255 const char *type;
256 u32 class;
257
258 dev = pci_alloc_dev(bus);
259 if (!dev)
260 return NULL;
261
262 sd = &dev->dev.archdata;
263 sd->iommu = pbm->iommu;
264 sd->stc = &pbm->stc;
265 sd->host_controller = pbm;
266 sd->op = op = of_find_device_by_node(node);
267 sd->numa_node = pbm->numa_node;
268
269 sd = &op->dev.archdata;
270 sd->iommu = pbm->iommu;
271 sd->stc = &pbm->stc;
272 sd->numa_node = pbm->numa_node;
273
274 if (!strcmp(node->name, "ebus"))
275 of_propagate_archdata(op);
276
277 type = of_get_property(node, "device_type", NULL);
278 if (type == NULL)
279 type = "";
280
281 if (ofpci_verbose)
282 printk(" create device, devfn: %x, type: %s\n",
283 devfn, type);
284
285 dev->sysdata = node;
286 dev->dev.parent = bus->bridge;
287 dev->dev.bus = &pci_bus_type;
288 dev->dev.of_node = of_node_get(node);
289 dev->devfn = devfn;
290 dev->multifunction = 0; /* maybe a lie? */
291 set_pcie_port_type(dev);
292
293 pci_dev_assign_slot(dev);
294 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
295 dev->device = of_getintprop_default(node, "device-id", 0xffff);
296 dev->subsystem_vendor =
297 of_getintprop_default(node, "subsystem-vendor-id", 0);
298 dev->subsystem_device =
299 of_getintprop_default(node, "subsystem-id", 0);
300
301 dev->cfg_size = pci_cfg_space_size(dev);
302
303 /* We can't actually use the firmware value, we have
304 * to read what is in the register right now. One
305 * reason is that in the case of IDE interfaces the
306 * firmware can sample the value before the the IDE
307 * interface is programmed into native mode.
308 */
309 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
310 dev->class = class >> 8;
311 dev->revision = class & 0xff;
312
313 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
314 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
315
316 if (ofpci_verbose)
317 printk(" class: 0x%x device name: %s\n",
318 dev->class, pci_name(dev));
319
320 /* I have seen IDE devices which will not respond to
321 * the bmdma simplex check reads if bus mastering is
322 * disabled.
323 */
324 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
325 pci_set_master(dev);
326
327 dev->current_state = PCI_UNKNOWN; /* unknown power state */
328 dev->error_state = pci_channel_io_normal;
329 dev->dma_mask = 0xffffffff;
330
331 if (!strcmp(node->name, "pci")) {
332 /* a PCI-PCI bridge */
333 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
334 dev->rom_base_reg = PCI_ROM_ADDRESS1;
335 } else if (!strcmp(type, "cardbus")) {
336 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
337 } else {
338 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
339 dev->rom_base_reg = PCI_ROM_ADDRESS;
340
341 dev->irq = sd->op->archdata.irqs[0];
342 if (dev->irq == 0xffffffff)
343 dev->irq = PCI_IRQ_NONE;
344 }
345
346 pci_parse_of_addrs(sd->op, node, dev);
347
348 if (ofpci_verbose)
349 printk(" adding to system ...\n");
350
351 pci_device_add(dev, bus);
352
353 return dev;
354 }
355
356 static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
357 {
358 u32 idx, first, last;
359
360 first = 8;
361 last = 0;
362 for (idx = 0; idx < 8; idx++) {
363 if ((map & (1 << idx)) != 0) {
364 if (first > idx)
365 first = idx;
366 if (last < idx)
367 last = idx;
368 }
369 }
370
371 *first_p = first;
372 *last_p = last;
373 }
374
375 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
376 * a proper 'ranges' property.
377 */
378 static void apb_fake_ranges(struct pci_dev *dev,
379 struct pci_bus *bus,
380 struct pci_pbm_info *pbm)
381 {
382 struct pci_bus_region region;
383 struct resource *res;
384 u32 first, last;
385 u8 map;
386
387 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
388 apb_calc_first_last(map, &first, &last);
389 res = bus->resource[0];
390 res->flags = IORESOURCE_IO;
391 region.start = (first << 21);
392 region.end = (last << 21) + ((1 << 21) - 1);
393 pcibios_bus_to_resource(dev->bus, res, &region);
394
395 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
396 apb_calc_first_last(map, &first, &last);
397 res = bus->resource[1];
398 res->flags = IORESOURCE_MEM;
399 region.start = (first << 29);
400 region.end = (last << 29) + ((1 << 29) - 1);
401 pcibios_bus_to_resource(dev->bus, res, &region);
402 }
403
404 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
405 struct device_node *node,
406 struct pci_bus *bus);
407
408 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
409
410 static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
411 struct device_node *node,
412 struct pci_dev *dev)
413 {
414 struct pci_bus *bus;
415 const u32 *busrange, *ranges;
416 int len, i, simba;
417 struct pci_bus_region region;
418 struct resource *res;
419 unsigned int flags;
420 u64 size;
421
422 if (ofpci_verbose)
423 printk("of_scan_pci_bridge(%s)\n", node->full_name);
424
425 /* parse bus-range property */
426 busrange = of_get_property(node, "bus-range", &len);
427 if (busrange == NULL || len != 8) {
428 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
429 node->full_name);
430 return;
431 }
432
433 if (ofpci_verbose)
434 printk(" Bridge bus range [%u --> %u]\n",
435 busrange[0], busrange[1]);
436
437 ranges = of_get_property(node, "ranges", &len);
438 simba = 0;
439 if (ranges == NULL) {
440 const char *model = of_get_property(node, "model", NULL);
441 if (model && !strcmp(model, "SUNW,simba"))
442 simba = 1;
443 }
444
445 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
446 if (!bus) {
447 printk(KERN_ERR "Failed to create pci bus for %s\n",
448 node->full_name);
449 return;
450 }
451
452 bus->primary = dev->bus->number;
453 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
454 bus->bridge_ctl = 0;
455
456 if (ofpci_verbose)
457 printk(" Bridge ranges[%p] simba[%d]\n",
458 ranges, simba);
459
460 /* parse ranges property, or cook one up by hand for Simba */
461 /* PCI #address-cells == 3 and #size-cells == 2 always */
462 res = &dev->resource[PCI_BRIDGE_RESOURCES];
463 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
464 res->flags = 0;
465 bus->resource[i] = res;
466 ++res;
467 }
468 if (simba) {
469 apb_fake_ranges(dev, bus, pbm);
470 goto after_ranges;
471 } else if (ranges == NULL) {
472 pci_read_bridge_bases(bus);
473 goto after_ranges;
474 }
475 i = 1;
476 for (; len >= 32; len -= 32, ranges += 8) {
477 u64 start;
478
479 if (ofpci_verbose)
480 printk(" RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
481 "%08x:%08x]\n",
482 ranges[0], ranges[1], ranges[2], ranges[3],
483 ranges[4], ranges[5], ranges[6], ranges[7]);
484
485 flags = pci_parse_of_flags(ranges[0]);
486 size = GET_64BIT(ranges, 6);
487 if (flags == 0 || size == 0)
488 continue;
489
490 /* On PCI-Express systems, PCI bridges that have no devices downstream
491 * have a bogus size value where the first 32-bit cell is 0xffffffff.
492 * This results in a bogus range where start + size overflows.
493 *
494 * Just skip these otherwise the kernel will complain when the resource
495 * tries to be claimed.
496 */
497 if (size >> 32 == 0xffffffff)
498 continue;
499
500 if (flags & IORESOURCE_IO) {
501 res = bus->resource[0];
502 if (res->flags) {
503 printk(KERN_ERR "PCI: ignoring extra I/O range"
504 " for bridge %s\n", node->full_name);
505 continue;
506 }
507 } else {
508 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
509 printk(KERN_ERR "PCI: too many memory ranges"
510 " for bridge %s\n", node->full_name);
511 continue;
512 }
513 res = bus->resource[i];
514 ++i;
515 }
516
517 res->flags = flags;
518 region.start = start = GET_64BIT(ranges, 1);
519 region.end = region.start + size - 1;
520
521 if (ofpci_verbose)
522 printk(" Using flags[%08x] start[%016llx] size[%016llx]\n",
523 flags, start, size);
524
525 pcibios_bus_to_resource(dev->bus, res, &region);
526 }
527 after_ranges:
528 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
529 bus->number);
530 if (ofpci_verbose)
531 printk(" bus name: %s\n", bus->name);
532
533 pci_of_scan_bus(pbm, node, bus);
534 }
535
536 static void pci_of_scan_bus(struct pci_pbm_info *pbm,
537 struct device_node *node,
538 struct pci_bus *bus)
539 {
540 struct device_node *child;
541 const u32 *reg;
542 int reglen, devfn, prev_devfn;
543 struct pci_dev *dev;
544
545 if (ofpci_verbose)
546 printk("PCI: scan_bus[%s] bus no %d\n",
547 node->full_name, bus->number);
548
549 child = NULL;
550 prev_devfn = -1;
551 while ((child = of_get_next_child(node, child)) != NULL) {
552 if (ofpci_verbose)
553 printk(" * %s\n", child->full_name);
554 reg = of_get_property(child, "reg", &reglen);
555 if (reg == NULL || reglen < 20)
556 continue;
557
558 devfn = (reg[0] >> 8) & 0xff;
559
560 /* This is a workaround for some device trees
561 * which list PCI devices twice. On the V100
562 * for example, device number 3 is listed twice.
563 * Once as "pm" and once again as "lomp".
564 */
565 if (devfn == prev_devfn)
566 continue;
567 prev_devfn = devfn;
568
569 /* create a new pci_dev for this device */
570 dev = of_create_pci_dev(pbm, child, bus, devfn);
571 if (!dev)
572 continue;
573 if (ofpci_verbose)
574 printk("PCI: dev header type: %x\n",
575 dev->hdr_type);
576
577 if (pci_is_bridge(dev))
578 of_scan_pci_bridge(pbm, child, dev);
579 }
580 }
581
582 static ssize_t
583 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
584 {
585 struct pci_dev *pdev;
586 struct device_node *dp;
587
588 pdev = to_pci_dev(dev);
589 dp = pdev->dev.of_node;
590
591 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
592 }
593
594 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
595
596 static void pci_bus_register_of_sysfs(struct pci_bus *bus)
597 {
598 struct pci_dev *dev;
599 struct pci_bus *child_bus;
600 int err;
601
602 list_for_each_entry(dev, &bus->devices, bus_list) {
603 /* we don't really care if we can create this file or
604 * not, but we need to assign the result of the call
605 * or the world will fall under alien invasion and
606 * everybody will be frozen on a spaceship ready to be
607 * eaten on alpha centauri by some green and jelly
608 * humanoid.
609 */
610 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
611 (void) err;
612 }
613 list_for_each_entry(child_bus, &bus->children, node)
614 pci_bus_register_of_sysfs(child_bus);
615 }
616
617 static void pci_claim_bus_resources(struct pci_bus *bus)
618 {
619 struct pci_bus *child_bus;
620 struct pci_dev *dev;
621
622 list_for_each_entry(dev, &bus->devices, bus_list) {
623 int i;
624
625 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
626 struct resource *r = &dev->resource[i];
627
628 if (r->parent || !r->start || !r->flags)
629 continue;
630
631 if (ofpci_verbose)
632 printk("PCI: Claiming %s: "
633 "Resource %d: %016llx..%016llx [%x]\n",
634 pci_name(dev), i,
635 (unsigned long long)r->start,
636 (unsigned long long)r->end,
637 (unsigned int)r->flags);
638
639 pci_claim_resource(dev, i);
640 }
641 }
642
643 list_for_each_entry(child_bus, &bus->children, node)
644 pci_claim_bus_resources(child_bus);
645 }
646
647 struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
648 struct device *parent)
649 {
650 LIST_HEAD(resources);
651 struct device_node *node = pbm->op->dev.of_node;
652 struct pci_bus *bus;
653
654 printk("PCI: Scanning PBM %s\n", node->full_name);
655
656 pci_add_resource_offset(&resources, &pbm->io_space,
657 pbm->io_space.start);
658 pci_add_resource_offset(&resources, &pbm->mem_space,
659 pbm->mem_space.start);
660 if (pbm->mem64_space.flags)
661 pci_add_resource_offset(&resources, &pbm->mem64_space,
662 pbm->mem_space.start);
663 pbm->busn.start = pbm->pci_first_busno;
664 pbm->busn.end = pbm->pci_last_busno;
665 pbm->busn.flags = IORESOURCE_BUS;
666 pci_add_resource(&resources, &pbm->busn);
667 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
668 pbm, &resources);
669 if (!bus) {
670 printk(KERN_ERR "Failed to create bus for %s\n",
671 node->full_name);
672 pci_free_resource_list(&resources);
673 return NULL;
674 }
675
676 pci_of_scan_bus(pbm, node, bus);
677 pci_bus_register_of_sysfs(bus);
678
679 pci_claim_bus_resources(bus);
680 pci_bus_add_devices(bus);
681 return bus;
682 }
683
684 void pcibios_fixup_bus(struct pci_bus *pbus)
685 {
686 }
687
688 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
689 resource_size_t size, resource_size_t align)
690 {
691 return res->start;
692 }
693
694 int pcibios_enable_device(struct pci_dev *dev, int mask)
695 {
696 u16 cmd, oldcmd;
697 int i;
698
699 pci_read_config_word(dev, PCI_COMMAND, &cmd);
700 oldcmd = cmd;
701
702 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
703 struct resource *res = &dev->resource[i];
704
705 /* Only set up the requested stuff */
706 if (!(mask & (1<<i)))
707 continue;
708
709 if (res->flags & IORESOURCE_IO)
710 cmd |= PCI_COMMAND_IO;
711 if (res->flags & IORESOURCE_MEM)
712 cmd |= PCI_COMMAND_MEMORY;
713 }
714
715 if (cmd != oldcmd) {
716 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
717 pci_name(dev), cmd);
718 /* Enable the appropriate bits in the PCI command register. */
719 pci_write_config_word(dev, PCI_COMMAND, cmd);
720 }
721 return 0;
722 }
723
724 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
725
726 /* If the user uses a host-bridge as the PCI device, he may use
727 * this to perform a raw mmap() of the I/O or MEM space behind
728 * that controller.
729 *
730 * This can be useful for execution of x86 PCI bios initialization code
731 * on a PCI card, like the xfree86 int10 stuff does.
732 */
733 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
734 enum pci_mmap_state mmap_state)
735 {
736 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
737 unsigned long space_size, user_offset, user_size;
738
739 if (mmap_state == pci_mmap_io) {
740 space_size = resource_size(&pbm->io_space);
741 } else {
742 space_size = resource_size(&pbm->mem_space);
743 }
744
745 /* Make sure the request is in range. */
746 user_offset = vma->vm_pgoff << PAGE_SHIFT;
747 user_size = vma->vm_end - vma->vm_start;
748
749 if (user_offset >= space_size ||
750 (user_offset + user_size) > space_size)
751 return -EINVAL;
752
753 if (mmap_state == pci_mmap_io) {
754 vma->vm_pgoff = (pbm->io_space.start +
755 user_offset) >> PAGE_SHIFT;
756 } else {
757 vma->vm_pgoff = (pbm->mem_space.start +
758 user_offset) >> PAGE_SHIFT;
759 }
760
761 return 0;
762 }
763
764 /* Adjust vm_pgoff of VMA such that it is the physical page offset
765 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
766 *
767 * Basically, the user finds the base address for his device which he wishes
768 * to mmap. They read the 32-bit value from the config space base register,
769 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
770 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
771 *
772 * Returns negative error code on failure, zero on success.
773 */
774 static int __pci_mmap_make_offset(struct pci_dev *pdev,
775 struct vm_area_struct *vma,
776 enum pci_mmap_state mmap_state)
777 {
778 unsigned long user_paddr, user_size;
779 int i, err;
780
781 /* First compute the physical address in vma->vm_pgoff,
782 * making sure the user offset is within range in the
783 * appropriate PCI space.
784 */
785 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
786 if (err)
787 return err;
788
789 /* If this is a mapping on a host bridge, any address
790 * is OK.
791 */
792 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
793 return err;
794
795 /* Otherwise make sure it's in the range for one of the
796 * device's resources.
797 */
798 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
799 user_size = vma->vm_end - vma->vm_start;
800
801 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
802 struct resource *rp = &pdev->resource[i];
803 resource_size_t aligned_end;
804
805 /* Active? */
806 if (!rp->flags)
807 continue;
808
809 /* Same type? */
810 if (i == PCI_ROM_RESOURCE) {
811 if (mmap_state != pci_mmap_mem)
812 continue;
813 } else {
814 if ((mmap_state == pci_mmap_io &&
815 (rp->flags & IORESOURCE_IO) == 0) ||
816 (mmap_state == pci_mmap_mem &&
817 (rp->flags & IORESOURCE_MEM) == 0))
818 continue;
819 }
820
821 /* Align the resource end to the next page address.
822 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
823 * because actually we need the address of the next byte
824 * after rp->end.
825 */
826 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
827
828 if ((rp->start <= user_paddr) &&
829 (user_paddr + user_size) <= aligned_end)
830 break;
831 }
832
833 if (i > PCI_ROM_RESOURCE)
834 return -EINVAL;
835
836 return 0;
837 }
838
839 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
840 * device mapping.
841 */
842 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
843 enum pci_mmap_state mmap_state)
844 {
845 /* Our io_remap_pfn_range takes care of this, do nothing. */
846 }
847
848 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
849 * for this architecture. The region in the process to map is described by vm_start
850 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
851 * The pci device structure is provided so that architectures may make mapping
852 * decisions on a per-device or per-bus basis.
853 *
854 * Returns a negative error code on failure, zero on success.
855 */
856 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
857 enum pci_mmap_state mmap_state,
858 int write_combine)
859 {
860 int ret;
861
862 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
863 if (ret < 0)
864 return ret;
865
866 __pci_mmap_set_pgprot(dev, vma, mmap_state);
867
868 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
869 ret = io_remap_pfn_range(vma, vma->vm_start,
870 vma->vm_pgoff,
871 vma->vm_end - vma->vm_start,
872 vma->vm_page_prot);
873 if (ret)
874 return ret;
875
876 return 0;
877 }
878
879 #ifdef CONFIG_NUMA
880 int pcibus_to_node(struct pci_bus *pbus)
881 {
882 struct pci_pbm_info *pbm = pbus->sysdata;
883
884 return pbm->numa_node;
885 }
886 EXPORT_SYMBOL(pcibus_to_node);
887 #endif
888
889 /* Return the domain number for this pci bus */
890
891 int pci_domain_nr(struct pci_bus *pbus)
892 {
893 struct pci_pbm_info *pbm = pbus->sysdata;
894 int ret;
895
896 if (!pbm) {
897 ret = -ENXIO;
898 } else {
899 ret = pbm->index;
900 }
901
902 return ret;
903 }
904 EXPORT_SYMBOL(pci_domain_nr);
905
906 #ifdef CONFIG_PCI_MSI
907 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
908 {
909 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
910 unsigned int irq;
911
912 if (!pbm->setup_msi_irq)
913 return -EINVAL;
914
915 return pbm->setup_msi_irq(&irq, pdev, desc);
916 }
917
918 void arch_teardown_msi_irq(unsigned int irq)
919 {
920 struct msi_desc *entry = irq_get_msi_desc(irq);
921 struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
922 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
923
924 if (pbm->teardown_msi_irq)
925 pbm->teardown_msi_irq(irq, pdev);
926 }
927 #endif /* !(CONFIG_PCI_MSI) */
928
929 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
930 {
931 struct pci_dev *ali_isa_bridge;
932 u8 val;
933
934 /* ALI sound chips generate 31-bits of DMA, a special register
935 * determines what bit 31 is emitted as.
936 */
937 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
938 PCI_DEVICE_ID_AL_M1533,
939 NULL);
940
941 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
942 if (set_bit)
943 val |= 0x01;
944 else
945 val &= ~0x01;
946 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
947 pci_dev_put(ali_isa_bridge);
948 }
949
950 int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
951 {
952 u64 dma_addr_mask;
953
954 if (pdev == NULL) {
955 dma_addr_mask = 0xffffffff;
956 } else {
957 struct iommu *iommu = pdev->dev.archdata.iommu;
958
959 dma_addr_mask = iommu->dma_addr_mask;
960
961 if (pdev->vendor == PCI_VENDOR_ID_AL &&
962 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
963 device_mask == 0x7fffffff) {
964 ali_sound_dma_hack(pdev,
965 (dma_addr_mask & 0x80000000) != 0);
966 return 1;
967 }
968 }
969
970 if (device_mask >= (1UL << 32UL))
971 return 0;
972
973 return (device_mask & dma_addr_mask) == dma_addr_mask;
974 }
975
976 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
977 const struct resource *rp, resource_size_t *start,
978 resource_size_t *end)
979 {
980 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
981 unsigned long offset;
982
983 if (rp->flags & IORESOURCE_IO)
984 offset = pbm->io_space.start;
985 else
986 offset = pbm->mem_space.start;
987
988 *start = rp->start - offset;
989 *end = rp->end - offset;
990 }
991
992 void pcibios_set_master(struct pci_dev *dev)
993 {
994 /* No special bus mastering setup handling */
995 }
996
997 static int __init pcibios_init(void)
998 {
999 pci_dfl_cache_line_size = 64 >> 2;
1000 return 0;
1001 }
1002 subsys_initcall(pcibios_init);
1003
1004 #ifdef CONFIG_SYSFS
1005
1006 #define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
1007
1008 static void pcie_bus_slot_names(struct pci_bus *pbus)
1009 {
1010 struct pci_dev *pdev;
1011 struct pci_bus *bus;
1012
1013 list_for_each_entry(pdev, &pbus->devices, bus_list) {
1014 char name[SLOT_NAME_SIZE];
1015 struct pci_slot *pci_slot;
1016 const u32 *slot_num;
1017 int len;
1018
1019 slot_num = of_get_property(pdev->dev.of_node,
1020 "physical-slot#", &len);
1021
1022 if (slot_num == NULL || len != 4)
1023 continue;
1024
1025 snprintf(name, sizeof(name), "%u", slot_num[0]);
1026 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
1027
1028 if (IS_ERR(pci_slot))
1029 pr_err("PCI: pci_create_slot returned %ld.\n",
1030 PTR_ERR(pci_slot));
1031 }
1032
1033 list_for_each_entry(bus, &pbus->children, node)
1034 pcie_bus_slot_names(bus);
1035 }
1036
1037 static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
1038 {
1039 const struct pci_slot_names {
1040 u32 slot_mask;
1041 char names[0];
1042 } *prop;
1043 const char *sp;
1044 int len, i;
1045 u32 mask;
1046
1047 prop = of_get_property(node, "slot-names", &len);
1048 if (!prop)
1049 return;
1050
1051 mask = prop->slot_mask;
1052 sp = prop->names;
1053
1054 if (ofpci_verbose)
1055 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
1056 node->full_name, mask);
1057
1058 i = 0;
1059 while (mask) {
1060 struct pci_slot *pci_slot;
1061 u32 this_bit = 1 << i;
1062
1063 if (!(mask & this_bit)) {
1064 i++;
1065 continue;
1066 }
1067
1068 if (ofpci_verbose)
1069 printk("PCI: Making slot [%s]\n", sp);
1070
1071 pci_slot = pci_create_slot(bus, i, sp, NULL);
1072 if (IS_ERR(pci_slot))
1073 printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
1074 PTR_ERR(pci_slot));
1075
1076 sp += strlen(sp) + 1;
1077 mask &= ~this_bit;
1078 i++;
1079 }
1080 }
1081
1082 static int __init of_pci_slot_init(void)
1083 {
1084 struct pci_bus *pbus = NULL;
1085
1086 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1087 struct device_node *node;
1088 struct pci_dev *pdev;
1089
1090 pdev = list_first_entry(&pbus->devices, struct pci_dev,
1091 bus_list);
1092
1093 if (pdev && pci_is_pcie(pdev)) {
1094 pcie_bus_slot_names(pbus);
1095 } else {
1096
1097 if (pbus->self) {
1098
1099 /* PCI->PCI bridge */
1100 node = pbus->self->dev.of_node;
1101
1102 } else {
1103 struct pci_pbm_info *pbm = pbus->sysdata;
1104
1105 /* Host PCI controller */
1106 node = pbm->op->dev.of_node;
1107 }
1108
1109 pci_bus_slot_names(node, pbus);
1110 }
1111 }
1112
1113 return 0;
1114 }
1115 device_initcall(of_pci_slot_init);
1116 #endif
Linux with added FPC-III support