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powerpc: Hard wire PT_SOFTE value to 1 in ptrace & signals
[linux/fpc-iii.git] / arch / powerpc / kernel / ptrace.c
blobbd2c49475473d0438d487f69cda7ce6cd1fcf6e3
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/mm.h>
21 #include <linux/smp.h>
22 #include <linux/errno.h>
23 #include <linux/ptrace.h>
24 #include <linux/regset.h>
25 #include <linux/tracehook.h>
26 #include <linux/elf.h>
27 #include <linux/user.h>
28 #include <linux/security.h>
29 #include <linux/signal.h>
30 #include <linux/seccomp.h>
31 #include <linux/audit.h>
32 #include <trace/syscall.h>
33 #include <linux/hw_breakpoint.h>
34 #include <linux/perf_event.h>
35 #include <linux/context_tracking.h>
36
37 #include <linux/uaccess.h>
38 #include <asm/page.h>
39 #include <asm/pgtable.h>
40 #include <asm/switch_to.h>
41 #include <asm/tm.h>
42 #include <asm/asm-prototypes.h>
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/syscalls.h>
46
47 /*
48 * The parameter save area on the stack is used to store arguments being passed
49 * to callee function and is located at fixed offset from stack pointer.
50 */
51 #ifdef CONFIG_PPC32
52 #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
53 #else /* CONFIG_PPC32 */
54 #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
55 #endif
56
57 struct pt_regs_offset {
58 const char *name;
59 int offset;
60 };
61
62 #define STR(s) #s /* convert to string */
63 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
64 #define GPR_OFFSET_NAME(num) \
65 {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \
66 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
67 #define REG_OFFSET_END {.name = NULL, .offset = 0}
68
69 #define TVSO(f) (offsetof(struct thread_vr_state, f))
70 #define TFSO(f) (offsetof(struct thread_fp_state, f))
71 #define TSO(f) (offsetof(struct thread_struct, f))
72
73 static const struct pt_regs_offset regoffset_table[] = {
74 GPR_OFFSET_NAME(0),
75 GPR_OFFSET_NAME(1),
76 GPR_OFFSET_NAME(2),
77 GPR_OFFSET_NAME(3),
78 GPR_OFFSET_NAME(4),
79 GPR_OFFSET_NAME(5),
80 GPR_OFFSET_NAME(6),
81 GPR_OFFSET_NAME(7),
82 GPR_OFFSET_NAME(8),
83 GPR_OFFSET_NAME(9),
84 GPR_OFFSET_NAME(10),
85 GPR_OFFSET_NAME(11),
86 GPR_OFFSET_NAME(12),
87 GPR_OFFSET_NAME(13),
88 GPR_OFFSET_NAME(14),
89 GPR_OFFSET_NAME(15),
90 GPR_OFFSET_NAME(16),
91 GPR_OFFSET_NAME(17),
92 GPR_OFFSET_NAME(18),
93 GPR_OFFSET_NAME(19),
94 GPR_OFFSET_NAME(20),
95 GPR_OFFSET_NAME(21),
96 GPR_OFFSET_NAME(22),
97 GPR_OFFSET_NAME(23),
98 GPR_OFFSET_NAME(24),
99 GPR_OFFSET_NAME(25),
100 GPR_OFFSET_NAME(26),
101 GPR_OFFSET_NAME(27),
102 GPR_OFFSET_NAME(28),
103 GPR_OFFSET_NAME(29),
104 GPR_OFFSET_NAME(30),
105 GPR_OFFSET_NAME(31),
106 REG_OFFSET_NAME(nip),
107 REG_OFFSET_NAME(msr),
108 REG_OFFSET_NAME(ctr),
109 REG_OFFSET_NAME(link),
110 REG_OFFSET_NAME(xer),
111 REG_OFFSET_NAME(ccr),
112 #ifdef CONFIG_PPC64
113 REG_OFFSET_NAME(softe),
114 #else
115 REG_OFFSET_NAME(mq),
116 #endif
117 REG_OFFSET_NAME(trap),
118 REG_OFFSET_NAME(dar),
119 REG_OFFSET_NAME(dsisr),
120 REG_OFFSET_END,
121 };
122
123 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
124 static void flush_tmregs_to_thread(struct task_struct *tsk)
125 {
126 /*
127 * If task is not current, it will have been flushed already to
128 * it's thread_struct during __switch_to().
129 *
130 * A reclaim flushes ALL the state or if not in TM save TM SPRs
131 * in the appropriate thread structures from live.
132 */
133
134 if ((!cpu_has_feature(CPU_FTR_TM)) || (tsk != current))
135 return;
136
137 if (MSR_TM_SUSPENDED(mfmsr())) {
138 tm_reclaim_current(TM_CAUSE_SIGNAL);
139 } else {
140 tm_enable();
141 tm_save_sprs(&(tsk->thread));
142 }
143 }
144 #else
145 static inline void flush_tmregs_to_thread(struct task_struct *tsk) { }
146 #endif
147
148 /**
149 * regs_query_register_offset() - query register offset from its name
150 * @name: the name of a register
151 *
152 * regs_query_register_offset() returns the offset of a register in struct
153 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
154 */
155 int regs_query_register_offset(const char *name)
156 {
157 const struct pt_regs_offset *roff;
158 for (roff = regoffset_table; roff->name != NULL; roff++)
159 if (!strcmp(roff->name, name))
160 return roff->offset;
161 return -EINVAL;
162 }
163
164 /**
165 * regs_query_register_name() - query register name from its offset
166 * @offset: the offset of a register in struct pt_regs.
167 *
168 * regs_query_register_name() returns the name of a register from its
169 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
170 */
171 const char *regs_query_register_name(unsigned int offset)
172 {
173 const struct pt_regs_offset *roff;
174 for (roff = regoffset_table; roff->name != NULL; roff++)
175 if (roff->offset == offset)
176 return roff->name;
177 return NULL;
178 }
179
180 /*
181 * does not yet catch signals sent when the child dies.
182 * in exit.c or in signal.c.
183 */
184
185 /*
186 * Set of msr bits that gdb can change on behalf of a process.
187 */
188 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
189 #define MSR_DEBUGCHANGE 0
190 #else
191 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
192 #endif
193
194 /*
195 * Max register writeable via put_reg
196 */
197 #ifdef CONFIG_PPC32
198 #define PT_MAX_PUT_REG PT_MQ
199 #else
200 #define PT_MAX_PUT_REG PT_CCR
201 #endif
202
203 static unsigned long get_user_msr(struct task_struct *task)
204 {
205 return task->thread.regs->msr | task->thread.fpexc_mode;
206 }
207
208 static int set_user_msr(struct task_struct *task, unsigned long msr)
209 {
210 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
211 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
212 return 0;
213 }
214
215 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
216 static unsigned long get_user_ckpt_msr(struct task_struct *task)
217 {
218 return task->thread.ckpt_regs.msr | task->thread.fpexc_mode;
219 }
220
221 static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
222 {
223 task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
224 task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
225 return 0;
226 }
227
228 static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap)
229 {
230 task->thread.ckpt_regs.trap = trap & 0xfff0;
231 return 0;
232 }
233 #endif
234
235 #ifdef CONFIG_PPC64
236 static int get_user_dscr(struct task_struct *task, unsigned long *data)
237 {
238 *data = task->thread.dscr;
239 return 0;
240 }
241
242 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
243 {
244 task->thread.dscr = dscr;
245 task->thread.dscr_inherit = 1;
246 return 0;
247 }
248 #else
249 static int get_user_dscr(struct task_struct *task, unsigned long *data)
250 {
251 return -EIO;
252 }
253
254 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
255 {
256 return -EIO;
257 }
258 #endif
259
260 /*
261 * We prevent mucking around with the reserved area of trap
262 * which are used internally by the kernel.
263 */
264 static int set_user_trap(struct task_struct *task, unsigned long trap)
265 {
266 task->thread.regs->trap = trap & 0xfff0;
267 return 0;
268 }
269
270 /*
271 * Get contents of register REGNO in task TASK.
272 */
273 int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data)
274 {
275 if ((task->thread.regs == NULL) || !data)
276 return -EIO;
277
278 if (regno == PT_MSR) {
279 *data = get_user_msr(task);
280 return 0;
281 }
282
283 if (regno == PT_DSCR)
284 return get_user_dscr(task, data);
285
286 #ifdef CONFIG_PPC64
287 /*
288 * softe copies paca->soft_enabled variable state. Since soft_enabled is
289 * no more used as a flag, lets force usr to alway see the softe value as 1
290 * which means interrupts are not soft disabled.
291 */
292 if (regno == PT_SOFTE) {
293 *data = 1;
294 return 0;
295 }
296 #endif
297
298 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
299 *data = ((unsigned long *)task->thread.regs)[regno];
300 return 0;
301 }
302
303 return -EIO;
304 }
305
306 /*
307 * Write contents of register REGNO in task TASK.
308 */
309 int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
310 {
311 if (task->thread.regs == NULL)
312 return -EIO;
313
314 if (regno == PT_MSR)
315 return set_user_msr(task, data);
316 if (regno == PT_TRAP)
317 return set_user_trap(task, data);
318 if (regno == PT_DSCR)
319 return set_user_dscr(task, data);
320
321 if (regno <= PT_MAX_PUT_REG) {
322 ((unsigned long *)task->thread.regs)[regno] = data;
323 return 0;
324 }
325 return -EIO;
326 }
327
328 static int gpr_get(struct task_struct *target, const struct user_regset *regset,
329 unsigned int pos, unsigned int count,
330 void *kbuf, void __user *ubuf)
331 {
332 int i, ret;
333
334 if (target->thread.regs == NULL)
335 return -EIO;
336
337 if (!FULL_REGS(target->thread.regs)) {
338 /* We have a partial register set. Fill 14-31 with bogus values */
339 for (i = 14; i < 32; i++)
340 target->thread.regs->gpr[i] = NV_REG_POISON;
341 }
342
343 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
344 target->thread.regs,
345 0, offsetof(struct pt_regs, msr));
346 if (!ret) {
347 unsigned long msr = get_user_msr(target);
348 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
349 offsetof(struct pt_regs, msr),
350 offsetof(struct pt_regs, msr) +
351 sizeof(msr));
352 }
353
354 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
355 offsetof(struct pt_regs, msr) + sizeof(long));
356
357 if (!ret)
358 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
359 &target->thread.regs->orig_gpr3,
360 offsetof(struct pt_regs, orig_gpr3),
361 sizeof(struct pt_regs));
362 if (!ret)
363 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
364 sizeof(struct pt_regs), -1);
365
366 return ret;
367 }
368
369 static int gpr_set(struct task_struct *target, const struct user_regset *regset,
370 unsigned int pos, unsigned int count,
371 const void *kbuf, const void __user *ubuf)
372 {
373 unsigned long reg;
374 int ret;
375
376 if (target->thread.regs == NULL)
377 return -EIO;
378
379 CHECK_FULL_REGS(target->thread.regs);
380
381 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
382 target->thread.regs,
383 0, PT_MSR * sizeof(reg));
384
385 if (!ret && count > 0) {
386 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
387 PT_MSR * sizeof(reg),
388 (PT_MSR + 1) * sizeof(reg));
389 if (!ret)
390 ret = set_user_msr(target, reg);
391 }
392
393 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
394 offsetof(struct pt_regs, msr) + sizeof(long));
395
396 if (!ret)
397 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
398 &target->thread.regs->orig_gpr3,
399 PT_ORIG_R3 * sizeof(reg),
400 (PT_MAX_PUT_REG + 1) * sizeof(reg));
401
402 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
403 ret = user_regset_copyin_ignore(
404 &pos, &count, &kbuf, &ubuf,
405 (PT_MAX_PUT_REG + 1) * sizeof(reg),
406 PT_TRAP * sizeof(reg));
407
408 if (!ret && count > 0) {
409 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
410 PT_TRAP * sizeof(reg),
411 (PT_TRAP + 1) * sizeof(reg));
412 if (!ret)
413 ret = set_user_trap(target, reg);
414 }
415
416 if (!ret)
417 ret = user_regset_copyin_ignore(
418 &pos, &count, &kbuf, &ubuf,
419 (PT_TRAP + 1) * sizeof(reg), -1);
420
421 return ret;
422 }
423
424 /*
425 * Regardless of transactions, 'fp_state' holds the current running
426 * value of all FPR registers and 'ckfp_state' holds the last checkpointed
427 * value of all FPR registers for the current transaction.
428 *
429 * Userspace interface buffer layout:
430 *
431 * struct data {
432 * u64 fpr[32];
433 * u64 fpscr;
434 * };
435 */
436 static int fpr_get(struct task_struct *target, const struct user_regset *regset,
437 unsigned int pos, unsigned int count,
438 void *kbuf, void __user *ubuf)
439 {
440 #ifdef CONFIG_VSX
441 u64 buf[33];
442 int i;
443
444 flush_fp_to_thread(target);
445
446 /* copy to local buffer then write that out */
447 for (i = 0; i < 32 ; i++)
448 buf[i] = target->thread.TS_FPR(i);
449 buf[32] = target->thread.fp_state.fpscr;
450 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
451 #else
452 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
453 offsetof(struct thread_fp_state, fpr[32]));
454
455 flush_fp_to_thread(target);
456
457 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
458 &target->thread.fp_state, 0, -1);
459 #endif
460 }
461
462 /*
463 * Regardless of transactions, 'fp_state' holds the current running
464 * value of all FPR registers and 'ckfp_state' holds the last checkpointed
465 * value of all FPR registers for the current transaction.
466 *
467 * Userspace interface buffer layout:
468 *
469 * struct data {
470 * u64 fpr[32];
471 * u64 fpscr;
472 * };
473 *
474 */
475 static int fpr_set(struct task_struct *target, const struct user_regset *regset,
476 unsigned int pos, unsigned int count,
477 const void *kbuf, const void __user *ubuf)
478 {
479 #ifdef CONFIG_VSX
480 u64 buf[33];
481 int i;
482
483 flush_fp_to_thread(target);
484
485 for (i = 0; i < 32 ; i++)
486 buf[i] = target->thread.TS_FPR(i);
487 buf[32] = target->thread.fp_state.fpscr;
488
489 /* copy to local buffer then write that out */
490 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
491 if (i)
492 return i;
493
494 for (i = 0; i < 32 ; i++)
495 target->thread.TS_FPR(i) = buf[i];
496 target->thread.fp_state.fpscr = buf[32];
497 return 0;
498 #else
499 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
500 offsetof(struct thread_fp_state, fpr[32]));
501
502 flush_fp_to_thread(target);
503
504 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
505 &target->thread.fp_state, 0, -1);
506 #endif
507 }
508
509 #ifdef CONFIG_ALTIVEC
510 /*
511 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
512 * The transfer totals 34 quadword. Quadwords 0-31 contain the
513 * corresponding vector registers. Quadword 32 contains the vscr as the
514 * last word (offset 12) within that quadword. Quadword 33 contains the
515 * vrsave as the first word (offset 0) within the quadword.
516 *
517 * This definition of the VMX state is compatible with the current PPC32
518 * ptrace interface. This allows signal handling and ptrace to use the
519 * same structures. This also simplifies the implementation of a bi-arch
520 * (combined (32- and 64-bit) gdb.
521 */
522
523 static int vr_active(struct task_struct *target,
524 const struct user_regset *regset)
525 {
526 flush_altivec_to_thread(target);
527 return target->thread.used_vr ? regset->n : 0;
528 }
529
530 /*
531 * Regardless of transactions, 'vr_state' holds the current running
532 * value of all the VMX registers and 'ckvr_state' holds the last
533 * checkpointed value of all the VMX registers for the current
534 * transaction to fall back on in case it aborts.
535 *
536 * Userspace interface buffer layout:
537 *
538 * struct data {
539 * vector128 vr[32];
540 * vector128 vscr;
541 * vector128 vrsave;
542 * };
543 */
544 static int vr_get(struct task_struct *target, const struct user_regset *regset,
545 unsigned int pos, unsigned int count,
546 void *kbuf, void __user *ubuf)
547 {
548 int ret;
549
550 flush_altivec_to_thread(target);
551
552 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
553 offsetof(struct thread_vr_state, vr[32]));
554
555 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
556 &target->thread.vr_state, 0,
557 33 * sizeof(vector128));
558 if (!ret) {
559 /*
560 * Copy out only the low-order word of vrsave.
561 */
562 union {
563 elf_vrreg_t reg;
564 u32 word;
565 } vrsave;
566 memset(&vrsave, 0, sizeof(vrsave));
567
568 vrsave.word = target->thread.vrsave;
569
570 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
571 33 * sizeof(vector128), -1);
572 }
573
574 return ret;
575 }
576
577 /*
578 * Regardless of transactions, 'vr_state' holds the current running
579 * value of all the VMX registers and 'ckvr_state' holds the last
580 * checkpointed value of all the VMX registers for the current
581 * transaction to fall back on in case it aborts.
582 *
583 * Userspace interface buffer layout:
584 *
585 * struct data {
586 * vector128 vr[32];
587 * vector128 vscr;
588 * vector128 vrsave;
589 * };
590 */
591 static int vr_set(struct task_struct *target, const struct user_regset *regset,
592 unsigned int pos, unsigned int count,
593 const void *kbuf, const void __user *ubuf)
594 {
595 int ret;
596
597 flush_altivec_to_thread(target);
598
599 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
600 offsetof(struct thread_vr_state, vr[32]));
601
602 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
603 &target->thread.vr_state, 0,
604 33 * sizeof(vector128));
605 if (!ret && count > 0) {
606 /*
607 * We use only the first word of vrsave.
608 */
609 union {
610 elf_vrreg_t reg;
611 u32 word;
612 } vrsave;
613 memset(&vrsave, 0, sizeof(vrsave));
614
615 vrsave.word = target->thread.vrsave;
616
617 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
618 33 * sizeof(vector128), -1);
619 if (!ret)
620 target->thread.vrsave = vrsave.word;
621 }
622
623 return ret;
624 }
625 #endif /* CONFIG_ALTIVEC */
626
627 #ifdef CONFIG_VSX
628 /*
629 * Currently to set and and get all the vsx state, you need to call
630 * the fp and VMX calls as well. This only get/sets the lower 32
631 * 128bit VSX registers.
632 */
633
634 static int vsr_active(struct task_struct *target,
635 const struct user_regset *regset)
636 {
637 flush_vsx_to_thread(target);
638 return target->thread.used_vsr ? regset->n : 0;
639 }
640
641 /*
642 * Regardless of transactions, 'fp_state' holds the current running
643 * value of all FPR registers and 'ckfp_state' holds the last
644 * checkpointed value of all FPR registers for the current
645 * transaction.
646 *
647 * Userspace interface buffer layout:
648 *
649 * struct data {
650 * u64 vsx[32];
651 * };
652 */
653 static int vsr_get(struct task_struct *target, const struct user_regset *regset,
654 unsigned int pos, unsigned int count,
655 void *kbuf, void __user *ubuf)
656 {
657 u64 buf[32];
658 int ret, i;
659
660 flush_tmregs_to_thread(target);
661 flush_fp_to_thread(target);
662 flush_altivec_to_thread(target);
663 flush_vsx_to_thread(target);
664
665 for (i = 0; i < 32 ; i++)
666 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
667
668 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
669 buf, 0, 32 * sizeof(double));
670
671 return ret;
672 }
673
674 /*
675 * Regardless of transactions, 'fp_state' holds the current running
676 * value of all FPR registers and 'ckfp_state' holds the last
677 * checkpointed value of all FPR registers for the current
678 * transaction.
679 *
680 * Userspace interface buffer layout:
681 *
682 * struct data {
683 * u64 vsx[32];
684 * };
685 */
686 static int vsr_set(struct task_struct *target, const struct user_regset *regset,
687 unsigned int pos, unsigned int count,
688 const void *kbuf, const void __user *ubuf)
689 {
690 u64 buf[32];
691 int ret,i;
692
693 flush_tmregs_to_thread(target);
694 flush_fp_to_thread(target);
695 flush_altivec_to_thread(target);
696 flush_vsx_to_thread(target);
697
698 for (i = 0; i < 32 ; i++)
699 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
700
701 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
702 buf, 0, 32 * sizeof(double));
703 if (!ret)
704 for (i = 0; i < 32 ; i++)
705 target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
706
707 return ret;
708 }
709 #endif /* CONFIG_VSX */
710
711 #ifdef CONFIG_SPE
712
713 /*
714 * For get_evrregs/set_evrregs functions 'data' has the following layout:
715 *
716 * struct {
717 * u32 evr[32];
718 * u64 acc;
719 * u32 spefscr;
720 * }
721 */
722
723 static int evr_active(struct task_struct *target,
724 const struct user_regset *regset)
725 {
726 flush_spe_to_thread(target);
727 return target->thread.used_spe ? regset->n : 0;
728 }
729
730 static int evr_get(struct task_struct *target, const struct user_regset *regset,
731 unsigned int pos, unsigned int count,
732 void *kbuf, void __user *ubuf)
733 {
734 int ret;
735
736 flush_spe_to_thread(target);
737
738 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
739 &target->thread.evr,
740 0, sizeof(target->thread.evr));
741
742 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
743 offsetof(struct thread_struct, spefscr));
744
745 if (!ret)
746 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
747 &target->thread.acc,
748 sizeof(target->thread.evr), -1);
749
750 return ret;
751 }
752
753 static int evr_set(struct task_struct *target, const struct user_regset *regset,
754 unsigned int pos, unsigned int count,
755 const void *kbuf, const void __user *ubuf)
756 {
757 int ret;
758
759 flush_spe_to_thread(target);
760
761 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
762 &target->thread.evr,
763 0, sizeof(target->thread.evr));
764
765 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
766 offsetof(struct thread_struct, spefscr));
767
768 if (!ret)
769 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
770 &target->thread.acc,
771 sizeof(target->thread.evr), -1);
772
773 return ret;
774 }
775 #endif /* CONFIG_SPE */
776
777 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
778 /**
779 * tm_cgpr_active - get active number of registers in CGPR
780 * @target: The target task.
781 * @regset: The user regset structure.
782 *
783 * This function checks for the active number of available
784 * regisers in transaction checkpointed GPR category.
785 */
786 static int tm_cgpr_active(struct task_struct *target,
787 const struct user_regset *regset)
788 {
789 if (!cpu_has_feature(CPU_FTR_TM))
790 return -ENODEV;
791
792 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
793 return 0;
794
795 return regset->n;
796 }
797
798 /**
799 * tm_cgpr_get - get CGPR registers
800 * @target: The target task.
801 * @regset: The user regset structure.
802 * @pos: The buffer position.
803 * @count: Number of bytes to copy.
804 * @kbuf: Kernel buffer to copy from.
805 * @ubuf: User buffer to copy into.
806 *
807 * This function gets transaction checkpointed GPR registers.
808 *
809 * When the transaction is active, 'ckpt_regs' holds all the checkpointed
810 * GPR register values for the current transaction to fall back on if it
811 * aborts in between. This function gets those checkpointed GPR registers.
812 * The userspace interface buffer layout is as follows.
813 *
814 * struct data {
815 * struct pt_regs ckpt_regs;
816 * };
817 */
818 static int tm_cgpr_get(struct task_struct *target,
819 const struct user_regset *regset,
820 unsigned int pos, unsigned int count,
821 void *kbuf, void __user *ubuf)
822 {
823 int ret;
824
825 if (!cpu_has_feature(CPU_FTR_TM))
826 return -ENODEV;
827
828 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
829 return -ENODATA;
830
831 flush_tmregs_to_thread(target);
832 flush_fp_to_thread(target);
833 flush_altivec_to_thread(target);
834
835 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
836 &target->thread.ckpt_regs,
837 0, offsetof(struct pt_regs, msr));
838 if (!ret) {
839 unsigned long msr = get_user_ckpt_msr(target);
840
841 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
842 offsetof(struct pt_regs, msr),
843 offsetof(struct pt_regs, msr) +
844 sizeof(msr));
845 }
846
847 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
848 offsetof(struct pt_regs, msr) + sizeof(long));
849
850 if (!ret)
851 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
852 &target->thread.ckpt_regs.orig_gpr3,
853 offsetof(struct pt_regs, orig_gpr3),
854 sizeof(struct pt_regs));
855 if (!ret)
856 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
857 sizeof(struct pt_regs), -1);
858
859 return ret;
860 }
861
862 /*
863 * tm_cgpr_set - set the CGPR registers
864 * @target: The target task.
865 * @regset: The user regset structure.
866 * @pos: The buffer position.
867 * @count: Number of bytes to copy.
868 * @kbuf: Kernel buffer to copy into.
869 * @ubuf: User buffer to copy from.
870 *
871 * This function sets in transaction checkpointed GPR registers.
872 *
873 * When the transaction is active, 'ckpt_regs' holds the checkpointed
874 * GPR register values for the current transaction to fall back on if it
875 * aborts in between. This function sets those checkpointed GPR registers.
876 * The userspace interface buffer layout is as follows.
877 *
878 * struct data {
879 * struct pt_regs ckpt_regs;
880 * };
881 */
882 static int tm_cgpr_set(struct task_struct *target,
883 const struct user_regset *regset,
884 unsigned int pos, unsigned int count,
885 const void *kbuf, const void __user *ubuf)
886 {
887 unsigned long reg;
888 int ret;
889
890 if (!cpu_has_feature(CPU_FTR_TM))
891 return -ENODEV;
892
893 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
894 return -ENODATA;
895
896 flush_tmregs_to_thread(target);
897 flush_fp_to_thread(target);
898 flush_altivec_to_thread(target);
899
900 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
901 &target->thread.ckpt_regs,
902 0, PT_MSR * sizeof(reg));
903
904 if (!ret && count > 0) {
905 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
906 PT_MSR * sizeof(reg),
907 (PT_MSR + 1) * sizeof(reg));
908 if (!ret)
909 ret = set_user_ckpt_msr(target, reg);
910 }
911
912 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
913 offsetof(struct pt_regs, msr) + sizeof(long));
914
915 if (!ret)
916 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
917 &target->thread.ckpt_regs.orig_gpr3,
918 PT_ORIG_R3 * sizeof(reg),
919 (PT_MAX_PUT_REG + 1) * sizeof(reg));
920
921 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
922 ret = user_regset_copyin_ignore(
923 &pos, &count, &kbuf, &ubuf,
924 (PT_MAX_PUT_REG + 1) * sizeof(reg),
925 PT_TRAP * sizeof(reg));
926
927 if (!ret && count > 0) {
928 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
929 PT_TRAP * sizeof(reg),
930 (PT_TRAP + 1) * sizeof(reg));
931 if (!ret)
932 ret = set_user_ckpt_trap(target, reg);
933 }
934
935 if (!ret)
936 ret = user_regset_copyin_ignore(
937 &pos, &count, &kbuf, &ubuf,
938 (PT_TRAP + 1) * sizeof(reg), -1);
939
940 return ret;
941 }
942
943 /**
944 * tm_cfpr_active - get active number of registers in CFPR
945 * @target: The target task.
946 * @regset: The user regset structure.
947 *
948 * This function checks for the active number of available
949 * regisers in transaction checkpointed FPR category.
950 */
951 static int tm_cfpr_active(struct task_struct *target,
952 const struct user_regset *regset)
953 {
954 if (!cpu_has_feature(CPU_FTR_TM))
955 return -ENODEV;
956
957 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
958 return 0;
959
960 return regset->n;
961 }
962
963 /**
964 * tm_cfpr_get - get CFPR registers
965 * @target: The target task.
966 * @regset: The user regset structure.
967 * @pos: The buffer position.
968 * @count: Number of bytes to copy.
969 * @kbuf: Kernel buffer to copy from.
970 * @ubuf: User buffer to copy into.
971 *
972 * This function gets in transaction checkpointed FPR registers.
973 *
974 * When the transaction is active 'ckfp_state' holds the checkpointed
975 * values for the current transaction to fall back on if it aborts
976 * in between. This function gets those checkpointed FPR registers.
977 * The userspace interface buffer layout is as follows.
978 *
979 * struct data {
980 * u64 fpr[32];
981 * u64 fpscr;
982 *};
983 */
984 static int tm_cfpr_get(struct task_struct *target,
985 const struct user_regset *regset,
986 unsigned int pos, unsigned int count,
987 void *kbuf, void __user *ubuf)
988 {
989 u64 buf[33];
990 int i;
991
992 if (!cpu_has_feature(CPU_FTR_TM))
993 return -ENODEV;
994
995 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
996 return -ENODATA;
997
998 flush_tmregs_to_thread(target);
999 flush_fp_to_thread(target);
1000 flush_altivec_to_thread(target);
1001
1002 /* copy to local buffer then write that out */
1003 for (i = 0; i < 32 ; i++)
1004 buf[i] = target->thread.TS_CKFPR(i);
1005 buf[32] = target->thread.ckfp_state.fpscr;
1006 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
1007 }
1008
1009 /**
1010 * tm_cfpr_set - set CFPR registers
1011 * @target: The target task.
1012 * @regset: The user regset structure.
1013 * @pos: The buffer position.
1014 * @count: Number of bytes to copy.
1015 * @kbuf: Kernel buffer to copy into.
1016 * @ubuf: User buffer to copy from.
1017 *
1018 * This function sets in transaction checkpointed FPR registers.
1019 *
1020 * When the transaction is active 'ckfp_state' holds the checkpointed
1021 * FPR register values for the current transaction to fall back on
1022 * if it aborts in between. This function sets these checkpointed
1023 * FPR registers. The userspace interface buffer layout is as follows.
1024 *
1025 * struct data {
1026 * u64 fpr[32];
1027 * u64 fpscr;
1028 *};
1029 */
1030 static int tm_cfpr_set(struct task_struct *target,
1031 const struct user_regset *regset,
1032 unsigned int pos, unsigned int count,
1033 const void *kbuf, const void __user *ubuf)
1034 {
1035 u64 buf[33];
1036 int i;
1037
1038 if (!cpu_has_feature(CPU_FTR_TM))
1039 return -ENODEV;
1040
1041 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1042 return -ENODATA;
1043
1044 flush_tmregs_to_thread(target);
1045 flush_fp_to_thread(target);
1046 flush_altivec_to_thread(target);
1047
1048 for (i = 0; i < 32; i++)
1049 buf[i] = target->thread.TS_CKFPR(i);
1050 buf[32] = target->thread.ckfp_state.fpscr;
1051
1052 /* copy to local buffer then write that out */
1053 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
1054 if (i)
1055 return i;
1056 for (i = 0; i < 32 ; i++)
1057 target->thread.TS_CKFPR(i) = buf[i];
1058 target->thread.ckfp_state.fpscr = buf[32];
1059 return 0;
1060 }
1061
1062 /**
1063 * tm_cvmx_active - get active number of registers in CVMX
1064 * @target: The target task.
1065 * @regset: The user regset structure.
1066 *
1067 * This function checks for the active number of available
1068 * regisers in checkpointed VMX category.
1069 */
1070 static int tm_cvmx_active(struct task_struct *target,
1071 const struct user_regset *regset)
1072 {
1073 if (!cpu_has_feature(CPU_FTR_TM))
1074 return -ENODEV;
1075
1076 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1077 return 0;
1078
1079 return regset->n;
1080 }
1081
1082 /**
1083 * tm_cvmx_get - get CMVX registers
1084 * @target: The target task.
1085 * @regset: The user regset structure.
1086 * @pos: The buffer position.
1087 * @count: Number of bytes to copy.
1088 * @kbuf: Kernel buffer to copy from.
1089 * @ubuf: User buffer to copy into.
1090 *
1091 * This function gets in transaction checkpointed VMX registers.
1092 *
1093 * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1094 * the checkpointed values for the current transaction to fall
1095 * back on if it aborts in between. The userspace interface buffer
1096 * layout is as follows.
1097 *
1098 * struct data {
1099 * vector128 vr[32];
1100 * vector128 vscr;
1101 * vector128 vrsave;
1102 *};
1103 */
1104 static int tm_cvmx_get(struct task_struct *target,
1105 const struct user_regset *regset,
1106 unsigned int pos, unsigned int count,
1107 void *kbuf, void __user *ubuf)
1108 {
1109 int ret;
1110
1111 BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
1112
1113 if (!cpu_has_feature(CPU_FTR_TM))
1114 return -ENODEV;
1115
1116 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1117 return -ENODATA;
1118
1119 /* Flush the state */
1120 flush_tmregs_to_thread(target);
1121 flush_fp_to_thread(target);
1122 flush_altivec_to_thread(target);
1123
1124 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1125 &target->thread.ckvr_state, 0,
1126 33 * sizeof(vector128));
1127 if (!ret) {
1128 /*
1129 * Copy out only the low-order word of vrsave.
1130 */
1131 union {
1132 elf_vrreg_t reg;
1133 u32 word;
1134 } vrsave;
1135 memset(&vrsave, 0, sizeof(vrsave));
1136 vrsave.word = target->thread.ckvrsave;
1137 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
1138 33 * sizeof(vector128), -1);
1139 }
1140
1141 return ret;
1142 }
1143
1144 /**
1145 * tm_cvmx_set - set CMVX registers
1146 * @target: The target task.
1147 * @regset: The user regset structure.
1148 * @pos: The buffer position.
1149 * @count: Number of bytes to copy.
1150 * @kbuf: Kernel buffer to copy into.
1151 * @ubuf: User buffer to copy from.
1152 *
1153 * This function sets in transaction checkpointed VMX registers.
1154 *
1155 * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1156 * the checkpointed values for the current transaction to fall
1157 * back on if it aborts in between. The userspace interface buffer
1158 * layout is as follows.
1159 *
1160 * struct data {
1161 * vector128 vr[32];
1162 * vector128 vscr;
1163 * vector128 vrsave;
1164 *};
1165 */
1166 static int tm_cvmx_set(struct task_struct *target,
1167 const struct user_regset *regset,
1168 unsigned int pos, unsigned int count,
1169 const void *kbuf, const void __user *ubuf)
1170 {
1171 int ret;
1172
1173 BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
1174
1175 if (!cpu_has_feature(CPU_FTR_TM))
1176 return -ENODEV;
1177
1178 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1179 return -ENODATA;
1180
1181 flush_tmregs_to_thread(target);
1182 flush_fp_to_thread(target);
1183 flush_altivec_to_thread(target);
1184
1185 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1186 &target->thread.ckvr_state, 0,
1187 33 * sizeof(vector128));
1188 if (!ret && count > 0) {
1189 /*
1190 * We use only the low-order word of vrsave.
1191 */
1192 union {
1193 elf_vrreg_t reg;
1194 u32 word;
1195 } vrsave;
1196 memset(&vrsave, 0, sizeof(vrsave));
1197 vrsave.word = target->thread.ckvrsave;
1198 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
1199 33 * sizeof(vector128), -1);
1200 if (!ret)
1201 target->thread.ckvrsave = vrsave.word;
1202 }
1203
1204 return ret;
1205 }
1206
1207 /**
1208 * tm_cvsx_active - get active number of registers in CVSX
1209 * @target: The target task.
1210 * @regset: The user regset structure.
1211 *
1212 * This function checks for the active number of available
1213 * regisers in transaction checkpointed VSX category.
1214 */
1215 static int tm_cvsx_active(struct task_struct *target,
1216 const struct user_regset *regset)
1217 {
1218 if (!cpu_has_feature(CPU_FTR_TM))
1219 return -ENODEV;
1220
1221 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1222 return 0;
1223
1224 flush_vsx_to_thread(target);
1225 return target->thread.used_vsr ? regset->n : 0;
1226 }
1227
1228 /**
1229 * tm_cvsx_get - get CVSX registers
1230 * @target: The target task.
1231 * @regset: The user regset structure.
1232 * @pos: The buffer position.
1233 * @count: Number of bytes to copy.
1234 * @kbuf: Kernel buffer to copy from.
1235 * @ubuf: User buffer to copy into.
1236 *
1237 * This function gets in transaction checkpointed VSX registers.
1238 *
1239 * When the transaction is active 'ckfp_state' holds the checkpointed
1240 * values for the current transaction to fall back on if it aborts
1241 * in between. This function gets those checkpointed VSX registers.
1242 * The userspace interface buffer layout is as follows.
1243 *
1244 * struct data {
1245 * u64 vsx[32];
1246 *};
1247 */
1248 static int tm_cvsx_get(struct task_struct *target,
1249 const struct user_regset *regset,
1250 unsigned int pos, unsigned int count,
1251 void *kbuf, void __user *ubuf)
1252 {
1253 u64 buf[32];
1254 int ret, i;
1255
1256 if (!cpu_has_feature(CPU_FTR_TM))
1257 return -ENODEV;
1258
1259 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1260 return -ENODATA;
1261
1262 /* Flush the state */
1263 flush_tmregs_to_thread(target);
1264 flush_fp_to_thread(target);
1265 flush_altivec_to_thread(target);
1266 flush_vsx_to_thread(target);
1267
1268 for (i = 0; i < 32 ; i++)
1269 buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
1270 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1271 buf, 0, 32 * sizeof(double));
1272
1273 return ret;
1274 }
1275
1276 /**
1277 * tm_cvsx_set - set CFPR registers
1278 * @target: The target task.
1279 * @regset: The user regset structure.
1280 * @pos: The buffer position.
1281 * @count: Number of bytes to copy.
1282 * @kbuf: Kernel buffer to copy into.
1283 * @ubuf: User buffer to copy from.
1284 *
1285 * This function sets in transaction checkpointed VSX registers.
1286 *
1287 * When the transaction is active 'ckfp_state' holds the checkpointed
1288 * VSX register values for the current transaction to fall back on
1289 * if it aborts in between. This function sets these checkpointed
1290 * FPR registers. The userspace interface buffer layout is as follows.
1291 *
1292 * struct data {
1293 * u64 vsx[32];
1294 *};
1295 */
1296 static int tm_cvsx_set(struct task_struct *target,
1297 const struct user_regset *regset,
1298 unsigned int pos, unsigned int count,
1299 const void *kbuf, const void __user *ubuf)
1300 {
1301 u64 buf[32];
1302 int ret, i;
1303
1304 if (!cpu_has_feature(CPU_FTR_TM))
1305 return -ENODEV;
1306
1307 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1308 return -ENODATA;
1309
1310 /* Flush the state */
1311 flush_tmregs_to_thread(target);
1312 flush_fp_to_thread(target);
1313 flush_altivec_to_thread(target);
1314 flush_vsx_to_thread(target);
1315
1316 for (i = 0; i < 32 ; i++)
1317 buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
1318
1319 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1320 buf, 0, 32 * sizeof(double));
1321 if (!ret)
1322 for (i = 0; i < 32 ; i++)
1323 target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
1324
1325 return ret;
1326 }
1327
1328 /**
1329 * tm_spr_active - get active number of registers in TM SPR
1330 * @target: The target task.
1331 * @regset: The user regset structure.
1332 *
1333 * This function checks the active number of available
1334 * regisers in the transactional memory SPR category.
1335 */
1336 static int tm_spr_active(struct task_struct *target,
1337 const struct user_regset *regset)
1338 {
1339 if (!cpu_has_feature(CPU_FTR_TM))
1340 return -ENODEV;
1341
1342 return regset->n;
1343 }
1344
1345 /**
1346 * tm_spr_get - get the TM related SPR registers
1347 * @target: The target task.
1348 * @regset: The user regset structure.
1349 * @pos: The buffer position.
1350 * @count: Number of bytes to copy.
1351 * @kbuf: Kernel buffer to copy from.
1352 * @ubuf: User buffer to copy into.
1353 *
1354 * This function gets transactional memory related SPR registers.
1355 * The userspace interface buffer layout is as follows.
1356 *
1357 * struct {
1358 * u64 tm_tfhar;
1359 * u64 tm_texasr;
1360 * u64 tm_tfiar;
1361 * };
1362 */
1363 static int tm_spr_get(struct task_struct *target,
1364 const struct user_regset *regset,
1365 unsigned int pos, unsigned int count,
1366 void *kbuf, void __user *ubuf)
1367 {
1368 int ret;
1369
1370 /* Build tests */
1371 BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
1372 BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
1373 BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
1374
1375 if (!cpu_has_feature(CPU_FTR_TM))
1376 return -ENODEV;
1377
1378 /* Flush the states */
1379 flush_tmregs_to_thread(target);
1380 flush_fp_to_thread(target);
1381 flush_altivec_to_thread(target);
1382
1383 /* TFHAR register */
1384 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1385 &target->thread.tm_tfhar, 0, sizeof(u64));
1386
1387 /* TEXASR register */
1388 if (!ret)
1389 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1390 &target->thread.tm_texasr, sizeof(u64),
1391 2 * sizeof(u64));
1392
1393 /* TFIAR register */
1394 if (!ret)
1395 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1396 &target->thread.tm_tfiar,
1397 2 * sizeof(u64), 3 * sizeof(u64));
1398 return ret;
1399 }
1400
1401 /**
1402 * tm_spr_set - set the TM related SPR registers
1403 * @target: The target task.
1404 * @regset: The user regset structure.
1405 * @pos: The buffer position.
1406 * @count: Number of bytes to copy.
1407 * @kbuf: Kernel buffer to copy into.
1408 * @ubuf: User buffer to copy from.
1409 *
1410 * This function sets transactional memory related SPR registers.
1411 * The userspace interface buffer layout is as follows.
1412 *
1413 * struct {
1414 * u64 tm_tfhar;
1415 * u64 tm_texasr;
1416 * u64 tm_tfiar;
1417 * };
1418 */
1419 static int tm_spr_set(struct task_struct *target,
1420 const struct user_regset *regset,
1421 unsigned int pos, unsigned int count,
1422 const void *kbuf, const void __user *ubuf)
1423 {
1424 int ret;
1425
1426 /* Build tests */
1427 BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
1428 BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
1429 BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
1430
1431 if (!cpu_has_feature(CPU_FTR_TM))
1432 return -ENODEV;
1433
1434 /* Flush the states */
1435 flush_tmregs_to_thread(target);
1436 flush_fp_to_thread(target);
1437 flush_altivec_to_thread(target);
1438
1439 /* TFHAR register */
1440 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1441 &target->thread.tm_tfhar, 0, sizeof(u64));
1442
1443 /* TEXASR register */
1444 if (!ret)
1445 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1446 &target->thread.tm_texasr, sizeof(u64),
1447 2 * sizeof(u64));
1448
1449 /* TFIAR register */
1450 if (!ret)
1451 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1452 &target->thread.tm_tfiar,
1453 2 * sizeof(u64), 3 * sizeof(u64));
1454 return ret;
1455 }
1456
1457 static int tm_tar_active(struct task_struct *target,
1458 const struct user_regset *regset)
1459 {
1460 if (!cpu_has_feature(CPU_FTR_TM))
1461 return -ENODEV;
1462
1463 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1464 return regset->n;
1465
1466 return 0;
1467 }
1468
1469 static int tm_tar_get(struct task_struct *target,
1470 const struct user_regset *regset,
1471 unsigned int pos, unsigned int count,
1472 void *kbuf, void __user *ubuf)
1473 {
1474 int ret;
1475
1476 if (!cpu_has_feature(CPU_FTR_TM))
1477 return -ENODEV;
1478
1479 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1480 return -ENODATA;
1481
1482 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1483 &target->thread.tm_tar, 0, sizeof(u64));
1484 return ret;
1485 }
1486
1487 static int tm_tar_set(struct task_struct *target,
1488 const struct user_regset *regset,
1489 unsigned int pos, unsigned int count,
1490 const void *kbuf, const void __user *ubuf)
1491 {
1492 int ret;
1493
1494 if (!cpu_has_feature(CPU_FTR_TM))
1495 return -ENODEV;
1496
1497 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1498 return -ENODATA;
1499
1500 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1501 &target->thread.tm_tar, 0, sizeof(u64));
1502 return ret;
1503 }
1504
1505 static int tm_ppr_active(struct task_struct *target,
1506 const struct user_regset *regset)
1507 {
1508 if (!cpu_has_feature(CPU_FTR_TM))
1509 return -ENODEV;
1510
1511 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1512 return regset->n;
1513
1514 return 0;
1515 }
1516
1517
1518 static int tm_ppr_get(struct task_struct *target,
1519 const struct user_regset *regset,
1520 unsigned int pos, unsigned int count,
1521 void *kbuf, void __user *ubuf)
1522 {
1523 int ret;
1524
1525 if (!cpu_has_feature(CPU_FTR_TM))
1526 return -ENODEV;
1527
1528 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1529 return -ENODATA;
1530
1531 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1532 &target->thread.tm_ppr, 0, sizeof(u64));
1533 return ret;
1534 }
1535
1536 static int tm_ppr_set(struct task_struct *target,
1537 const struct user_regset *regset,
1538 unsigned int pos, unsigned int count,
1539 const void *kbuf, const void __user *ubuf)
1540 {
1541 int ret;
1542
1543 if (!cpu_has_feature(CPU_FTR_TM))
1544 return -ENODEV;
1545
1546 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1547 return -ENODATA;
1548
1549 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1550 &target->thread.tm_ppr, 0, sizeof(u64));
1551 return ret;
1552 }
1553
1554 static int tm_dscr_active(struct task_struct *target,
1555 const struct user_regset *regset)
1556 {
1557 if (!cpu_has_feature(CPU_FTR_TM))
1558 return -ENODEV;
1559
1560 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1561 return regset->n;
1562
1563 return 0;
1564 }
1565
1566 static int tm_dscr_get(struct task_struct *target,
1567 const struct user_regset *regset,
1568 unsigned int pos, unsigned int count,
1569 void *kbuf, void __user *ubuf)
1570 {
1571 int ret;
1572
1573 if (!cpu_has_feature(CPU_FTR_TM))
1574 return -ENODEV;
1575
1576 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1577 return -ENODATA;
1578
1579 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1580 &target->thread.tm_dscr, 0, sizeof(u64));
1581 return ret;
1582 }
1583
1584 static int tm_dscr_set(struct task_struct *target,
1585 const struct user_regset *regset,
1586 unsigned int pos, unsigned int count,
1587 const void *kbuf, const void __user *ubuf)
1588 {
1589 int ret;
1590
1591 if (!cpu_has_feature(CPU_FTR_TM))
1592 return -ENODEV;
1593
1594 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1595 return -ENODATA;
1596
1597 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1598 &target->thread.tm_dscr, 0, sizeof(u64));
1599 return ret;
1600 }
1601 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1602
1603 #ifdef CONFIG_PPC64
1604 static int ppr_get(struct task_struct *target,
1605 const struct user_regset *regset,
1606 unsigned int pos, unsigned int count,
1607 void *kbuf, void __user *ubuf)
1608 {
1609 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1610 &target->thread.ppr, 0, sizeof(u64));
1611 }
1612
1613 static int ppr_set(struct task_struct *target,
1614 const struct user_regset *regset,
1615 unsigned int pos, unsigned int count,
1616 const void *kbuf, const void __user *ubuf)
1617 {
1618 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1619 &target->thread.ppr, 0, sizeof(u64));
1620 }
1621
1622 static int dscr_get(struct task_struct *target,
1623 const struct user_regset *regset,
1624 unsigned int pos, unsigned int count,
1625 void *kbuf, void __user *ubuf)
1626 {
1627 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1628 &target->thread.dscr, 0, sizeof(u64));
1629 }
1630 static int dscr_set(struct task_struct *target,
1631 const struct user_regset *regset,
1632 unsigned int pos, unsigned int count,
1633 const void *kbuf, const void __user *ubuf)
1634 {
1635 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1636 &target->thread.dscr, 0, sizeof(u64));
1637 }
1638 #endif
1639 #ifdef CONFIG_PPC_BOOK3S_64
1640 static int tar_get(struct task_struct *target,
1641 const struct user_regset *regset,
1642 unsigned int pos, unsigned int count,
1643 void *kbuf, void __user *ubuf)
1644 {
1645 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1646 &target->thread.tar, 0, sizeof(u64));
1647 }
1648 static int tar_set(struct task_struct *target,
1649 const struct user_regset *regset,
1650 unsigned int pos, unsigned int count,
1651 const void *kbuf, const void __user *ubuf)
1652 {
1653 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1654 &target->thread.tar, 0, sizeof(u64));
1655 }
1656
1657 static int ebb_active(struct task_struct *target,
1658 const struct user_regset *regset)
1659 {
1660 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1661 return -ENODEV;
1662
1663 if (target->thread.used_ebb)
1664 return regset->n;
1665
1666 return 0;
1667 }
1668
1669 static int ebb_get(struct task_struct *target,
1670 const struct user_regset *regset,
1671 unsigned int pos, unsigned int count,
1672 void *kbuf, void __user *ubuf)
1673 {
1674 /* Build tests */
1675 BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
1676 BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
1677
1678 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1679 return -ENODEV;
1680
1681 if (!target->thread.used_ebb)
1682 return -ENODATA;
1683
1684 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1685 &target->thread.ebbrr, 0, 3 * sizeof(unsigned long));
1686 }
1687
1688 static int ebb_set(struct task_struct *target,
1689 const struct user_regset *regset,
1690 unsigned int pos, unsigned int count,
1691 const void *kbuf, const void __user *ubuf)
1692 {
1693 int ret = 0;
1694
1695 /* Build tests */
1696 BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
1697 BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
1698
1699 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1700 return -ENODEV;
1701
1702 if (target->thread.used_ebb)
1703 return -ENODATA;
1704
1705 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1706 &target->thread.ebbrr, 0, sizeof(unsigned long));
1707
1708 if (!ret)
1709 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1710 &target->thread.ebbhr, sizeof(unsigned long),
1711 2 * sizeof(unsigned long));
1712
1713 if (!ret)
1714 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1715 &target->thread.bescr,
1716 2 * sizeof(unsigned long), 3 * sizeof(unsigned long));
1717
1718 return ret;
1719 }
1720 static int pmu_active(struct task_struct *target,
1721 const struct user_regset *regset)
1722 {
1723 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1724 return -ENODEV;
1725
1726 return regset->n;
1727 }
1728
1729 static int pmu_get(struct task_struct *target,
1730 const struct user_regset *regset,
1731 unsigned int pos, unsigned int count,
1732 void *kbuf, void __user *ubuf)
1733 {
1734 /* Build tests */
1735 BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
1736 BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
1737 BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
1738 BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
1739
1740 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1741 return -ENODEV;
1742
1743 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1744 &target->thread.siar, 0,
1745 5 * sizeof(unsigned long));
1746 }
1747
1748 static int pmu_set(struct task_struct *target,
1749 const struct user_regset *regset,
1750 unsigned int pos, unsigned int count,
1751 const void *kbuf, const void __user *ubuf)
1752 {
1753 int ret = 0;
1754
1755 /* Build tests */
1756 BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
1757 BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
1758 BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
1759 BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
1760
1761 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1762 return -ENODEV;
1763
1764 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1765 &target->thread.siar, 0,
1766 sizeof(unsigned long));
1767
1768 if (!ret)
1769 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1770 &target->thread.sdar, sizeof(unsigned long),
1771 2 * sizeof(unsigned long));
1772
1773 if (!ret)
1774 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1775 &target->thread.sier, 2 * sizeof(unsigned long),
1776 3 * sizeof(unsigned long));
1777
1778 if (!ret)
1779 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1780 &target->thread.mmcr2, 3 * sizeof(unsigned long),
1781 4 * sizeof(unsigned long));
1782
1783 if (!ret)
1784 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1785 &target->thread.mmcr0, 4 * sizeof(unsigned long),
1786 5 * sizeof(unsigned long));
1787 return ret;
1788 }
1789 #endif
1790 /*
1791 * These are our native regset flavors.
1792 */
1793 enum powerpc_regset {
1794 REGSET_GPR,
1795 REGSET_FPR,
1796 #ifdef CONFIG_ALTIVEC
1797 REGSET_VMX,
1798 #endif
1799 #ifdef CONFIG_VSX
1800 REGSET_VSX,
1801 #endif
1802 #ifdef CONFIG_SPE
1803 REGSET_SPE,
1804 #endif
1805 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1806 REGSET_TM_CGPR, /* TM checkpointed GPR registers */
1807 REGSET_TM_CFPR, /* TM checkpointed FPR registers */
1808 REGSET_TM_CVMX, /* TM checkpointed VMX registers */
1809 REGSET_TM_CVSX, /* TM checkpointed VSX registers */
1810 REGSET_TM_SPR, /* TM specific SPR registers */
1811 REGSET_TM_CTAR, /* TM checkpointed TAR register */
1812 REGSET_TM_CPPR, /* TM checkpointed PPR register */
1813 REGSET_TM_CDSCR, /* TM checkpointed DSCR register */
1814 #endif
1815 #ifdef CONFIG_PPC64
1816 REGSET_PPR, /* PPR register */
1817 REGSET_DSCR, /* DSCR register */
1818 #endif
1819 #ifdef CONFIG_PPC_BOOK3S_64
1820 REGSET_TAR, /* TAR register */
1821 REGSET_EBB, /* EBB registers */
1822 REGSET_PMR, /* Performance Monitor Registers */
1823 #endif
1824 };
1825
1826 static const struct user_regset native_regsets[] = {
1827 [REGSET_GPR] = {
1828 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
1829 .size = sizeof(long), .align = sizeof(long),
1830 .get = gpr_get, .set = gpr_set
1831 },
1832 [REGSET_FPR] = {
1833 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
1834 .size = sizeof(double), .align = sizeof(double),
1835 .get = fpr_get, .set = fpr_set
1836 },
1837 #ifdef CONFIG_ALTIVEC
1838 [REGSET_VMX] = {
1839 .core_note_type = NT_PPC_VMX, .n = 34,
1840 .size = sizeof(vector128), .align = sizeof(vector128),
1841 .active = vr_active, .get = vr_get, .set = vr_set
1842 },
1843 #endif
1844 #ifdef CONFIG_VSX
1845 [REGSET_VSX] = {
1846 .core_note_type = NT_PPC_VSX, .n = 32,
1847 .size = sizeof(double), .align = sizeof(double),
1848 .active = vsr_active, .get = vsr_get, .set = vsr_set
1849 },
1850 #endif
1851 #ifdef CONFIG_SPE
1852 [REGSET_SPE] = {
1853 .core_note_type = NT_PPC_SPE, .n = 35,
1854 .size = sizeof(u32), .align = sizeof(u32),
1855 .active = evr_active, .get = evr_get, .set = evr_set
1856 },
1857 #endif
1858 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1859 [REGSET_TM_CGPR] = {
1860 .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
1861 .size = sizeof(long), .align = sizeof(long),
1862 .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set
1863 },
1864 [REGSET_TM_CFPR] = {
1865 .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
1866 .size = sizeof(double), .align = sizeof(double),
1867 .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
1868 },
1869 [REGSET_TM_CVMX] = {
1870 .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
1871 .size = sizeof(vector128), .align = sizeof(vector128),
1872 .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
1873 },
1874 [REGSET_TM_CVSX] = {
1875 .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
1876 .size = sizeof(double), .align = sizeof(double),
1877 .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
1878 },
1879 [REGSET_TM_SPR] = {
1880 .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
1881 .size = sizeof(u64), .align = sizeof(u64),
1882 .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
1883 },
1884 [REGSET_TM_CTAR] = {
1885 .core_note_type = NT_PPC_TM_CTAR, .n = 1,
1886 .size = sizeof(u64), .align = sizeof(u64),
1887 .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
1888 },
1889 [REGSET_TM_CPPR] = {
1890 .core_note_type = NT_PPC_TM_CPPR, .n = 1,
1891 .size = sizeof(u64), .align = sizeof(u64),
1892 .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
1893 },
1894 [REGSET_TM_CDSCR] = {
1895 .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
1896 .size = sizeof(u64), .align = sizeof(u64),
1897 .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
1898 },
1899 #endif
1900 #ifdef CONFIG_PPC64
1901 [REGSET_PPR] = {
1902 .core_note_type = NT_PPC_PPR, .n = 1,
1903 .size = sizeof(u64), .align = sizeof(u64),
1904 .get = ppr_get, .set = ppr_set
1905 },
1906 [REGSET_DSCR] = {
1907 .core_note_type = NT_PPC_DSCR, .n = 1,
1908 .size = sizeof(u64), .align = sizeof(u64),
1909 .get = dscr_get, .set = dscr_set
1910 },
1911 #endif
1912 #ifdef CONFIG_PPC_BOOK3S_64
1913 [REGSET_TAR] = {
1914 .core_note_type = NT_PPC_TAR, .n = 1,
1915 .size = sizeof(u64), .align = sizeof(u64),
1916 .get = tar_get, .set = tar_set
1917 },
1918 [REGSET_EBB] = {
1919 .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
1920 .size = sizeof(u64), .align = sizeof(u64),
1921 .active = ebb_active, .get = ebb_get, .set = ebb_set
1922 },
1923 [REGSET_PMR] = {
1924 .core_note_type = NT_PPC_PMU, .n = ELF_NPMU,
1925 .size = sizeof(u64), .align = sizeof(u64),
1926 .active = pmu_active, .get = pmu_get, .set = pmu_set
1927 },
1928 #endif
1929 };
1930
1931 static const struct user_regset_view user_ppc_native_view = {
1932 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
1933 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
1934 };
1935
1936 #ifdef CONFIG_PPC64
1937 #include <linux/compat.h>
1938
1939 static int gpr32_get_common(struct task_struct *target,
1940 const struct user_regset *regset,
1941 unsigned int pos, unsigned int count,
1942 void *kbuf, void __user *ubuf,
1943 unsigned long *regs)
1944 {
1945 compat_ulong_t *k = kbuf;
1946 compat_ulong_t __user *u = ubuf;
1947 compat_ulong_t reg;
1948
1949 pos /= sizeof(reg);
1950 count /= sizeof(reg);
1951
1952 if (kbuf)
1953 for (; count > 0 && pos < PT_MSR; --count)
1954 *k++ = regs[pos++];
1955 else
1956 for (; count > 0 && pos < PT_MSR; --count)
1957 if (__put_user((compat_ulong_t) regs[pos++], u++))
1958 return -EFAULT;
1959
1960 if (count > 0 && pos == PT_MSR) {
1961 reg = get_user_msr(target);
1962 if (kbuf)
1963 *k++ = reg;
1964 else if (__put_user(reg, u++))
1965 return -EFAULT;
1966 ++pos;
1967 --count;
1968 }
1969
1970 if (kbuf)
1971 for (; count > 0 && pos < PT_REGS_COUNT; --count)
1972 *k++ = regs[pos++];
1973 else
1974 for (; count > 0 && pos < PT_REGS_COUNT; --count)
1975 if (__put_user((compat_ulong_t) regs[pos++], u++))
1976 return -EFAULT;
1977
1978 kbuf = k;
1979 ubuf = u;
1980 pos *= sizeof(reg);
1981 count *= sizeof(reg);
1982 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
1983 PT_REGS_COUNT * sizeof(reg), -1);
1984 }
1985
1986 static int gpr32_set_common(struct task_struct *target,
1987 const struct user_regset *regset,
1988 unsigned int pos, unsigned int count,
1989 const void *kbuf, const void __user *ubuf,
1990 unsigned long *regs)
1991 {
1992 const compat_ulong_t *k = kbuf;
1993 const compat_ulong_t __user *u = ubuf;
1994 compat_ulong_t reg;
1995
1996 pos /= sizeof(reg);
1997 count /= sizeof(reg);
1998
1999 if (kbuf)
2000 for (; count > 0 && pos < PT_MSR; --count)
2001 regs[pos++] = *k++;
2002 else
2003 for (; count > 0 && pos < PT_MSR; --count) {
2004 if (__get_user(reg, u++))
2005 return -EFAULT;
2006 regs[pos++] = reg;
2007 }
2008
2009
2010 if (count > 0 && pos == PT_MSR) {
2011 if (kbuf)
2012 reg = *k++;
2013 else if (__get_user(reg, u++))
2014 return -EFAULT;
2015 set_user_msr(target, reg);
2016 ++pos;
2017 --count;
2018 }
2019
2020 if (kbuf) {
2021 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
2022 regs[pos++] = *k++;
2023 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
2024 ++k;
2025 } else {
2026 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
2027 if (__get_user(reg, u++))
2028 return -EFAULT;
2029 regs[pos++] = reg;
2030 }
2031 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
2032 if (__get_user(reg, u++))
2033 return -EFAULT;
2034 }
2035
2036 if (count > 0 && pos == PT_TRAP) {
2037 if (kbuf)
2038 reg = *k++;
2039 else if (__get_user(reg, u++))
2040 return -EFAULT;
2041 set_user_trap(target, reg);
2042 ++pos;
2043 --count;
2044 }
2045
2046 kbuf = k;
2047 ubuf = u;
2048 pos *= sizeof(reg);
2049 count *= sizeof(reg);
2050 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
2051 (PT_TRAP + 1) * sizeof(reg), -1);
2052 }
2053
2054 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2055 static int tm_cgpr32_get(struct task_struct *target,
2056 const struct user_regset *regset,
2057 unsigned int pos, unsigned int count,
2058 void *kbuf, void __user *ubuf)
2059 {
2060 return gpr32_get_common(target, regset, pos, count, kbuf, ubuf,
2061 &target->thread.ckpt_regs.gpr[0]);
2062 }
2063
2064 static int tm_cgpr32_set(struct task_struct *target,
2065 const struct user_regset *regset,
2066 unsigned int pos, unsigned int count,
2067 const void *kbuf, const void __user *ubuf)
2068 {
2069 return gpr32_set_common(target, regset, pos, count, kbuf, ubuf,
2070 &target->thread.ckpt_regs.gpr[0]);
2071 }
2072 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2073
2074 static int gpr32_get(struct task_struct *target,
2075 const struct user_regset *regset,
2076 unsigned int pos, unsigned int count,
2077 void *kbuf, void __user *ubuf)
2078 {
2079 int i;
2080
2081 if (target->thread.regs == NULL)
2082 return -EIO;
2083
2084 if (!FULL_REGS(target->thread.regs)) {
2085 /*
2086 * We have a partial register set.
2087 * Fill 14-31 with bogus values.
2088 */
2089 for (i = 14; i < 32; i++)
2090 target->thread.regs->gpr[i] = NV_REG_POISON;
2091 }
2092 return gpr32_get_common(target, regset, pos, count, kbuf, ubuf,
2093 &target->thread.regs->gpr[0]);
2094 }
2095
2096 static int gpr32_set(struct task_struct *target,
2097 const struct user_regset *regset,
2098 unsigned int pos, unsigned int count,
2099 const void *kbuf, const void __user *ubuf)
2100 {
2101 if (target->thread.regs == NULL)
2102 return -EIO;
2103
2104 CHECK_FULL_REGS(target->thread.regs);
2105 return gpr32_set_common(target, regset, pos, count, kbuf, ubuf,
2106 &target->thread.regs->gpr[0]);
2107 }
2108
2109 /*
2110 * These are the regset flavors matching the CONFIG_PPC32 native set.
2111 */
2112 static const struct user_regset compat_regsets[] = {
2113 [REGSET_GPR] = {
2114 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
2115 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
2116 .get = gpr32_get, .set = gpr32_set
2117 },
2118 [REGSET_FPR] = {
2119 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
2120 .size = sizeof(double), .align = sizeof(double),
2121 .get = fpr_get, .set = fpr_set
2122 },
2123 #ifdef CONFIG_ALTIVEC
2124 [REGSET_VMX] = {
2125 .core_note_type = NT_PPC_VMX, .n = 34,
2126 .size = sizeof(vector128), .align = sizeof(vector128),
2127 .active = vr_active, .get = vr_get, .set = vr_set
2128 },
2129 #endif
2130 #ifdef CONFIG_SPE
2131 [REGSET_SPE] = {
2132 .core_note_type = NT_PPC_SPE, .n = 35,
2133 .size = sizeof(u32), .align = sizeof(u32),
2134 .active = evr_active, .get = evr_get, .set = evr_set
2135 },
2136 #endif
2137 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2138 [REGSET_TM_CGPR] = {
2139 .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
2140 .size = sizeof(long), .align = sizeof(long),
2141 .active = tm_cgpr_active,
2142 .get = tm_cgpr32_get, .set = tm_cgpr32_set
2143 },
2144 [REGSET_TM_CFPR] = {
2145 .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
2146 .size = sizeof(double), .align = sizeof(double),
2147 .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
2148 },
2149 [REGSET_TM_CVMX] = {
2150 .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
2151 .size = sizeof(vector128), .align = sizeof(vector128),
2152 .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
2153 },
2154 [REGSET_TM_CVSX] = {
2155 .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
2156 .size = sizeof(double), .align = sizeof(double),
2157 .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
2158 },
2159 [REGSET_TM_SPR] = {
2160 .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
2161 .size = sizeof(u64), .align = sizeof(u64),
2162 .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
2163 },
2164 [REGSET_TM_CTAR] = {
2165 .core_note_type = NT_PPC_TM_CTAR, .n = 1,
2166 .size = sizeof(u64), .align = sizeof(u64),
2167 .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
2168 },
2169 [REGSET_TM_CPPR] = {
2170 .core_note_type = NT_PPC_TM_CPPR, .n = 1,
2171 .size = sizeof(u64), .align = sizeof(u64),
2172 .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
2173 },
2174 [REGSET_TM_CDSCR] = {
2175 .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
2176 .size = sizeof(u64), .align = sizeof(u64),
2177 .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
2178 },
2179 #endif
2180 #ifdef CONFIG_PPC64
2181 [REGSET_PPR] = {
2182 .core_note_type = NT_PPC_PPR, .n = 1,
2183 .size = sizeof(u64), .align = sizeof(u64),
2184 .get = ppr_get, .set = ppr_set
2185 },
2186 [REGSET_DSCR] = {
2187 .core_note_type = NT_PPC_DSCR, .n = 1,
2188 .size = sizeof(u64), .align = sizeof(u64),
2189 .get = dscr_get, .set = dscr_set
2190 },
2191 #endif
2192 #ifdef CONFIG_PPC_BOOK3S_64
2193 [REGSET_TAR] = {
2194 .core_note_type = NT_PPC_TAR, .n = 1,
2195 .size = sizeof(u64), .align = sizeof(u64),
2196 .get = tar_get, .set = tar_set
2197 },
2198 [REGSET_EBB] = {
2199 .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
2200 .size = sizeof(u64), .align = sizeof(u64),
2201 .active = ebb_active, .get = ebb_get, .set = ebb_set
2202 },
2203 #endif
2204 };
2205
2206 static const struct user_regset_view user_ppc_compat_view = {
2207 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
2208 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
2209 };
2210 #endif /* CONFIG_PPC64 */
2211
2212 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
2213 {
2214 #ifdef CONFIG_PPC64
2215 if (test_tsk_thread_flag(task, TIF_32BIT))
2216 return &user_ppc_compat_view;
2217 #endif
2218 return &user_ppc_native_view;
2219 }
2220
2221
2222 void user_enable_single_step(struct task_struct *task)
2223 {
2224 struct pt_regs *regs = task->thread.regs;
2225
2226 if (regs != NULL) {
2227 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2228 task->thread.debug.dbcr0 &= ~DBCR0_BT;
2229 task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
2230 regs->msr |= MSR_DE;
2231 #else
2232 regs->msr &= ~MSR_BE;
2233 regs->msr |= MSR_SE;
2234 #endif
2235 }
2236 set_tsk_thread_flag(task, TIF_SINGLESTEP);
2237 }
2238
2239 void user_enable_block_step(struct task_struct *task)
2240 {
2241 struct pt_regs *regs = task->thread.regs;
2242
2243 if (regs != NULL) {
2244 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2245 task->thread.debug.dbcr0 &= ~DBCR0_IC;
2246 task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
2247 regs->msr |= MSR_DE;
2248 #else
2249 regs->msr &= ~MSR_SE;
2250 regs->msr |= MSR_BE;
2251 #endif
2252 }
2253 set_tsk_thread_flag(task, TIF_SINGLESTEP);
2254 }
2255
2256 void user_disable_single_step(struct task_struct *task)
2257 {
2258 struct pt_regs *regs = task->thread.regs;
2259
2260 if (regs != NULL) {
2261 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2262 /*
2263 * The logic to disable single stepping should be as
2264 * simple as turning off the Instruction Complete flag.
2265 * And, after doing so, if all debug flags are off, turn
2266 * off DBCR0(IDM) and MSR(DE) .... Torez
2267 */
2268 task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
2269 /*
2270 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
2271 */
2272 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
2273 task->thread.debug.dbcr1)) {
2274 /*
2275 * All debug events were off.....
2276 */
2277 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
2278 regs->msr &= ~MSR_DE;
2279 }
2280 #else
2281 regs->msr &= ~(MSR_SE | MSR_BE);
2282 #endif
2283 }
2284 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
2285 }
2286
2287 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2288 void ptrace_triggered(struct perf_event *bp,
2289 struct perf_sample_data *data, struct pt_regs *regs)
2290 {
2291 struct perf_event_attr attr;
2292
2293 /*
2294 * Disable the breakpoint request here since ptrace has defined a
2295 * one-shot behaviour for breakpoint exceptions in PPC64.
2296 * The SIGTRAP signal is generated automatically for us in do_dabr().
2297 * We don't have to do anything about that here
2298 */
2299 attr = bp->attr;
2300 attr.disabled = true;
2301 modify_user_hw_breakpoint(bp, &attr);
2302 }
2303 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2304
2305 static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
2306 unsigned long data)
2307 {
2308 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2309 int ret;
2310 struct thread_struct *thread = &(task->thread);
2311 struct perf_event *bp;
2312 struct perf_event_attr attr;
2313 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2314 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2315 struct arch_hw_breakpoint hw_brk;
2316 #endif
2317
2318 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
2319 * For embedded processors we support one DAC and no IAC's at the
2320 * moment.
2321 */
2322 if (addr > 0)
2323 return -EINVAL;
2324
2325 /* The bottom 3 bits in dabr are flags */
2326 if ((data & ~0x7UL) >= TASK_SIZE)
2327 return -EIO;
2328
2329 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2330 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
2331 * It was assumed, on previous implementations, that 3 bits were
2332 * passed together with the data address, fitting the design of the
2333 * DABR register, as follows:
2334 *
2335 * bit 0: Read flag
2336 * bit 1: Write flag
2337 * bit 2: Breakpoint translation
2338 *
2339 * Thus, we use them here as so.
2340 */
2341
2342 /* Ensure breakpoint translation bit is set */
2343 if (data && !(data & HW_BRK_TYPE_TRANSLATE))
2344 return -EIO;
2345 hw_brk.address = data & (~HW_BRK_TYPE_DABR);
2346 hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
2347 hw_brk.len = 8;
2348 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2349 bp = thread->ptrace_bps[0];
2350 if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) {
2351 if (bp) {
2352 unregister_hw_breakpoint(bp);
2353 thread->ptrace_bps[0] = NULL;
2354 }
2355 return 0;
2356 }
2357 if (bp) {
2358 attr = bp->attr;
2359 attr.bp_addr = hw_brk.address;
2360 arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
2361
2362 /* Enable breakpoint */
2363 attr.disabled = false;
2364
2365 ret = modify_user_hw_breakpoint(bp, &attr);
2366 if (ret) {
2367 return ret;
2368 }
2369 thread->ptrace_bps[0] = bp;
2370 thread->hw_brk = hw_brk;
2371 return 0;
2372 }
2373
2374 /* Create a new breakpoint request if one doesn't exist already */
2375 hw_breakpoint_init(&attr);
2376 attr.bp_addr = hw_brk.address;
2377 arch_bp_generic_fields(hw_brk.type,
2378 &attr.bp_type);
2379
2380 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
2381 ptrace_triggered, NULL, task);
2382 if (IS_ERR(bp)) {
2383 thread->ptrace_bps[0] = NULL;
2384 return PTR_ERR(bp);
2385 }
2386
2387 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2388 task->thread.hw_brk = hw_brk;
2389 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
2390 /* As described above, it was assumed 3 bits were passed with the data
2391 * address, but we will assume only the mode bits will be passed
2392 * as to not cause alignment restrictions for DAC-based processors.
2393 */
2394
2395 /* DAC's hold the whole address without any mode flags */
2396 task->thread.debug.dac1 = data & ~0x3UL;
2397
2398 if (task->thread.debug.dac1 == 0) {
2399 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
2400 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
2401 task->thread.debug.dbcr1)) {
2402 task->thread.regs->msr &= ~MSR_DE;
2403 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
2404 }
2405 return 0;
2406 }
2407
2408 /* Read or Write bits must be set */
2409
2410 if (!(data & 0x3UL))
2411 return -EINVAL;
2412
2413 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
2414 register */
2415 task->thread.debug.dbcr0 |= DBCR0_IDM;
2416
2417 /* Check for write and read flags and set DBCR0
2418 accordingly */
2419 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
2420 if (data & 0x1UL)
2421 dbcr_dac(task) |= DBCR_DAC1R;
2422 if (data & 0x2UL)
2423 dbcr_dac(task) |= DBCR_DAC1W;
2424 task->thread.regs->msr |= MSR_DE;
2425 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2426 return 0;
2427 }
2428
2429 /*
2430 * Called by kernel/ptrace.c when detaching..
2431 *
2432 * Make sure single step bits etc are not set.
2433 */
2434 void ptrace_disable(struct task_struct *child)
2435 {
2436 /* make sure the single step bit is not set. */
2437 user_disable_single_step(child);
2438 }
2439
2440 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2441 static long set_instruction_bp(struct task_struct *child,
2442 struct ppc_hw_breakpoint *bp_info)
2443 {
2444 int slot;
2445 int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
2446 int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
2447 int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
2448 int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
2449
2450 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
2451 slot2_in_use = 1;
2452 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
2453 slot4_in_use = 1;
2454
2455 if (bp_info->addr >= TASK_SIZE)
2456 return -EIO;
2457
2458 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
2459
2460 /* Make sure range is valid. */
2461 if (bp_info->addr2 >= TASK_SIZE)
2462 return -EIO;
2463
2464 /* We need a pair of IAC regsisters */
2465 if ((!slot1_in_use) && (!slot2_in_use)) {
2466 slot = 1;
2467 child->thread.debug.iac1 = bp_info->addr;
2468 child->thread.debug.iac2 = bp_info->addr2;
2469 child->thread.debug.dbcr0 |= DBCR0_IAC1;
2470 if (bp_info->addr_mode ==
2471 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2472 dbcr_iac_range(child) |= DBCR_IAC12X;
2473 else
2474 dbcr_iac_range(child) |= DBCR_IAC12I;
2475 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2476 } else if ((!slot3_in_use) && (!slot4_in_use)) {
2477 slot = 3;
2478 child->thread.debug.iac3 = bp_info->addr;
2479 child->thread.debug.iac4 = bp_info->addr2;
2480 child->thread.debug.dbcr0 |= DBCR0_IAC3;
2481 if (bp_info->addr_mode ==
2482 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2483 dbcr_iac_range(child) |= DBCR_IAC34X;
2484 else
2485 dbcr_iac_range(child) |= DBCR_IAC34I;
2486 #endif
2487 } else
2488 return -ENOSPC;
2489 } else {
2490 /* We only need one. If possible leave a pair free in
2491 * case a range is needed later
2492 */
2493 if (!slot1_in_use) {
2494 /*
2495 * Don't use iac1 if iac1-iac2 are free and either
2496 * iac3 or iac4 (but not both) are free
2497 */
2498 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
2499 slot = 1;
2500 child->thread.debug.iac1 = bp_info->addr;
2501 child->thread.debug.dbcr0 |= DBCR0_IAC1;
2502 goto out;
2503 }
2504 }
2505 if (!slot2_in_use) {
2506 slot = 2;
2507 child->thread.debug.iac2 = bp_info->addr;
2508 child->thread.debug.dbcr0 |= DBCR0_IAC2;
2509 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2510 } else if (!slot3_in_use) {
2511 slot = 3;
2512 child->thread.debug.iac3 = bp_info->addr;
2513 child->thread.debug.dbcr0 |= DBCR0_IAC3;
2514 } else if (!slot4_in_use) {
2515 slot = 4;
2516 child->thread.debug.iac4 = bp_info->addr;
2517 child->thread.debug.dbcr0 |= DBCR0_IAC4;
2518 #endif
2519 } else
2520 return -ENOSPC;
2521 }
2522 out:
2523 child->thread.debug.dbcr0 |= DBCR0_IDM;
2524 child->thread.regs->msr |= MSR_DE;
2525
2526 return slot;
2527 }
2528
2529 static int del_instruction_bp(struct task_struct *child, int slot)
2530 {
2531 switch (slot) {
2532 case 1:
2533 if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
2534 return -ENOENT;
2535
2536 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
2537 /* address range - clear slots 1 & 2 */
2538 child->thread.debug.iac2 = 0;
2539 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
2540 }
2541 child->thread.debug.iac1 = 0;
2542 child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
2543 break;
2544 case 2:
2545 if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
2546 return -ENOENT;
2547
2548 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
2549 /* used in a range */
2550 return -EINVAL;
2551 child->thread.debug.iac2 = 0;
2552 child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
2553 break;
2554 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2555 case 3:
2556 if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
2557 return -ENOENT;
2558
2559 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
2560 /* address range - clear slots 3 & 4 */
2561 child->thread.debug.iac4 = 0;
2562 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
2563 }
2564 child->thread.debug.iac3 = 0;
2565 child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
2566 break;
2567 case 4:
2568 if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
2569 return -ENOENT;
2570
2571 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
2572 /* Used in a range */
2573 return -EINVAL;
2574 child->thread.debug.iac4 = 0;
2575 child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
2576 break;
2577 #endif
2578 default:
2579 return -EINVAL;
2580 }
2581 return 0;
2582 }
2583
2584 static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
2585 {
2586 int byte_enable =
2587 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
2588 & 0xf;
2589 int condition_mode =
2590 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
2591 int slot;
2592
2593 if (byte_enable && (condition_mode == 0))
2594 return -EINVAL;
2595
2596 if (bp_info->addr >= TASK_SIZE)
2597 return -EIO;
2598
2599 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
2600 slot = 1;
2601 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2602 dbcr_dac(child) |= DBCR_DAC1R;
2603 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2604 dbcr_dac(child) |= DBCR_DAC1W;
2605 child->thread.debug.dac1 = (unsigned long)bp_info->addr;
2606 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2607 if (byte_enable) {
2608 child->thread.debug.dvc1 =
2609 (unsigned long)bp_info->condition_value;
2610 child->thread.debug.dbcr2 |=
2611 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
2612 (condition_mode << DBCR2_DVC1M_SHIFT));
2613 }
2614 #endif
2615 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2616 } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
2617 /* Both dac1 and dac2 are part of a range */
2618 return -ENOSPC;
2619 #endif
2620 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
2621 slot = 2;
2622 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2623 dbcr_dac(child) |= DBCR_DAC2R;
2624 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2625 dbcr_dac(child) |= DBCR_DAC2W;
2626 child->thread.debug.dac2 = (unsigned long)bp_info->addr;
2627 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2628 if (byte_enable) {
2629 child->thread.debug.dvc2 =
2630 (unsigned long)bp_info->condition_value;
2631 child->thread.debug.dbcr2 |=
2632 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
2633 (condition_mode << DBCR2_DVC2M_SHIFT));
2634 }
2635 #endif
2636 } else
2637 return -ENOSPC;
2638 child->thread.debug.dbcr0 |= DBCR0_IDM;
2639 child->thread.regs->msr |= MSR_DE;
2640
2641 return slot + 4;
2642 }
2643
2644 static int del_dac(struct task_struct *child, int slot)
2645 {
2646 if (slot == 1) {
2647 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
2648 return -ENOENT;
2649
2650 child->thread.debug.dac1 = 0;
2651 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
2652 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2653 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
2654 child->thread.debug.dac2 = 0;
2655 child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
2656 }
2657 child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
2658 #endif
2659 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2660 child->thread.debug.dvc1 = 0;
2661 #endif
2662 } else if (slot == 2) {
2663 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
2664 return -ENOENT;
2665
2666 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2667 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
2668 /* Part of a range */
2669 return -EINVAL;
2670 child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
2671 #endif
2672 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2673 child->thread.debug.dvc2 = 0;
2674 #endif
2675 child->thread.debug.dac2 = 0;
2676 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
2677 } else
2678 return -EINVAL;
2679
2680 return 0;
2681 }
2682 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2683
2684 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2685 static int set_dac_range(struct task_struct *child,
2686 struct ppc_hw_breakpoint *bp_info)
2687 {
2688 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
2689
2690 /* We don't allow range watchpoints to be used with DVC */
2691 if (bp_info->condition_mode)
2692 return -EINVAL;
2693
2694 /*
2695 * Best effort to verify the address range. The user/supervisor bits
2696 * prevent trapping in kernel space, but let's fail on an obvious bad
2697 * range. The simple test on the mask is not fool-proof, and any
2698 * exclusive range will spill over into kernel space.
2699 */
2700 if (bp_info->addr >= TASK_SIZE)
2701 return -EIO;
2702 if (mode == PPC_BREAKPOINT_MODE_MASK) {
2703 /*
2704 * dac2 is a bitmask. Don't allow a mask that makes a
2705 * kernel space address from a valid dac1 value
2706 */
2707 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
2708 return -EIO;
2709 } else {
2710 /*
2711 * For range breakpoints, addr2 must also be a valid address
2712 */
2713 if (bp_info->addr2 >= TASK_SIZE)
2714 return -EIO;
2715 }
2716
2717 if (child->thread.debug.dbcr0 &
2718 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
2719 return -ENOSPC;
2720
2721 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2722 child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
2723 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2724 child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
2725 child->thread.debug.dac1 = bp_info->addr;
2726 child->thread.debug.dac2 = bp_info->addr2;
2727 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
2728 child->thread.debug.dbcr2 |= DBCR2_DAC12M;
2729 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2730 child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
2731 else /* PPC_BREAKPOINT_MODE_MASK */
2732 child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
2733 child->thread.regs->msr |= MSR_DE;
2734
2735 return 5;
2736 }
2737 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
2738
2739 static long ppc_set_hwdebug(struct task_struct *child,
2740 struct ppc_hw_breakpoint *bp_info)
2741 {
2742 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2743 int len = 0;
2744 struct thread_struct *thread = &(child->thread);
2745 struct perf_event *bp;
2746 struct perf_event_attr attr;
2747 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2748 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2749 struct arch_hw_breakpoint brk;
2750 #endif
2751
2752 if (bp_info->version != 1)
2753 return -ENOTSUPP;
2754 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2755 /*
2756 * Check for invalid flags and combinations
2757 */
2758 if ((bp_info->trigger_type == 0) ||
2759 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
2760 PPC_BREAKPOINT_TRIGGER_RW)) ||
2761 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
2762 (bp_info->condition_mode &
2763 ~(PPC_BREAKPOINT_CONDITION_MODE |
2764 PPC_BREAKPOINT_CONDITION_BE_ALL)))
2765 return -EINVAL;
2766 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
2767 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
2768 return -EINVAL;
2769 #endif
2770
2771 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
2772 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
2773 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
2774 return -EINVAL;
2775 return set_instruction_bp(child, bp_info);
2776 }
2777 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
2778 return set_dac(child, bp_info);
2779
2780 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2781 return set_dac_range(child, bp_info);
2782 #else
2783 return -EINVAL;
2784 #endif
2785 #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2786 /*
2787 * We only support one data breakpoint
2788 */
2789 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
2790 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
2791 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
2792 return -EINVAL;
2793
2794 if ((unsigned long)bp_info->addr >= TASK_SIZE)
2795 return -EIO;
2796
2797 brk.address = bp_info->addr & ~7UL;
2798 brk.type = HW_BRK_TYPE_TRANSLATE;
2799 brk.len = 8;
2800 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2801 brk.type |= HW_BRK_TYPE_READ;
2802 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2803 brk.type |= HW_BRK_TYPE_WRITE;
2804 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2805 /*
2806 * Check if the request is for 'range' breakpoints. We can
2807 * support it if range < 8 bytes.
2808 */
2809 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
2810 len = bp_info->addr2 - bp_info->addr;
2811 else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
2812 len = 1;
2813 else
2814 return -EINVAL;
2815 bp = thread->ptrace_bps[0];
2816 if (bp)
2817 return -ENOSPC;
2818
2819 /* Create a new breakpoint request if one doesn't exist already */
2820 hw_breakpoint_init(&attr);
2821 attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
2822 attr.bp_len = len;
2823 arch_bp_generic_fields(brk.type, &attr.bp_type);
2824
2825 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
2826 ptrace_triggered, NULL, child);
2827 if (IS_ERR(bp)) {
2828 thread->ptrace_bps[0] = NULL;
2829 return PTR_ERR(bp);
2830 }
2831
2832 return 1;
2833 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2834
2835 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
2836 return -EINVAL;
2837
2838 if (child->thread.hw_brk.address)
2839 return -ENOSPC;
2840
2841 child->thread.hw_brk = brk;
2842
2843 return 1;
2844 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2845 }
2846
2847 static long ppc_del_hwdebug(struct task_struct *child, long data)
2848 {
2849 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2850 int ret = 0;
2851 struct thread_struct *thread = &(child->thread);
2852 struct perf_event *bp;
2853 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2854 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2855 int rc;
2856
2857 if (data <= 4)
2858 rc = del_instruction_bp(child, (int)data);
2859 else
2860 rc = del_dac(child, (int)data - 4);
2861
2862 if (!rc) {
2863 if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
2864 child->thread.debug.dbcr1)) {
2865 child->thread.debug.dbcr0 &= ~DBCR0_IDM;
2866 child->thread.regs->msr &= ~MSR_DE;
2867 }
2868 }
2869 return rc;
2870 #else
2871 if (data != 1)
2872 return -EINVAL;
2873
2874 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2875 bp = thread->ptrace_bps[0];
2876 if (bp) {
2877 unregister_hw_breakpoint(bp);
2878 thread->ptrace_bps[0] = NULL;
2879 } else
2880 ret = -ENOENT;
2881 return ret;
2882 #else /* CONFIG_HAVE_HW_BREAKPOINT */
2883 if (child->thread.hw_brk.address == 0)
2884 return -ENOENT;
2885
2886 child->thread.hw_brk.address = 0;
2887 child->thread.hw_brk.type = 0;
2888 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2889
2890 return 0;
2891 #endif
2892 }
2893
2894 long arch_ptrace(struct task_struct *child, long request,
2895 unsigned long addr, unsigned long data)
2896 {
2897 int ret = -EPERM;
2898 void __user *datavp = (void __user *) data;
2899 unsigned long __user *datalp = datavp;
2900
2901 switch (request) {
2902 /* read the word at location addr in the USER area. */
2903 case PTRACE_PEEKUSR: {
2904 unsigned long index, tmp;
2905
2906 ret = -EIO;
2907 /* convert to index and check */
2908 #ifdef CONFIG_PPC32
2909 index = addr >> 2;
2910 if ((addr & 3) || (index > PT_FPSCR)
2911 || (child->thread.regs == NULL))
2912 #else
2913 index = addr >> 3;
2914 if ((addr & 7) || (index > PT_FPSCR))
2915 #endif
2916 break;
2917
2918 CHECK_FULL_REGS(child->thread.regs);
2919 if (index < PT_FPR0) {
2920 ret = ptrace_get_reg(child, (int) index, &tmp);
2921 if (ret)
2922 break;
2923 } else {
2924 unsigned int fpidx = index - PT_FPR0;
2925
2926 flush_fp_to_thread(child);
2927 if (fpidx < (PT_FPSCR - PT_FPR0))
2928 memcpy(&tmp, &child->thread.TS_FPR(fpidx),
2929 sizeof(long));
2930 else
2931 tmp = child->thread.fp_state.fpscr;
2932 }
2933 ret = put_user(tmp, datalp);
2934 break;
2935 }
2936
2937 /* write the word at location addr in the USER area */
2938 case PTRACE_POKEUSR: {
2939 unsigned long index;
2940
2941 ret = -EIO;
2942 /* convert to index and check */
2943 #ifdef CONFIG_PPC32
2944 index = addr >> 2;
2945 if ((addr & 3) || (index > PT_FPSCR)
2946 || (child->thread.regs == NULL))
2947 #else
2948 index = addr >> 3;
2949 if ((addr & 7) || (index > PT_FPSCR))
2950 #endif
2951 break;
2952
2953 CHECK_FULL_REGS(child->thread.regs);
2954 if (index < PT_FPR0) {
2955 ret = ptrace_put_reg(child, index, data);
2956 } else {
2957 unsigned int fpidx = index - PT_FPR0;
2958
2959 flush_fp_to_thread(child);
2960 if (fpidx < (PT_FPSCR - PT_FPR0))
2961 memcpy(&child->thread.TS_FPR(fpidx), &data,
2962 sizeof(long));
2963 else
2964 child->thread.fp_state.fpscr = data;
2965 ret = 0;
2966 }
2967 break;
2968 }
2969
2970 case PPC_PTRACE_GETHWDBGINFO: {
2971 struct ppc_debug_info dbginfo;
2972
2973 dbginfo.version = 1;
2974 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2975 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
2976 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
2977 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
2978 dbginfo.data_bp_alignment = 4;
2979 dbginfo.sizeof_condition = 4;
2980 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
2981 PPC_DEBUG_FEATURE_INSN_BP_MASK;
2982 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2983 dbginfo.features |=
2984 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
2985 PPC_DEBUG_FEATURE_DATA_BP_MASK;
2986 #endif
2987 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
2988 dbginfo.num_instruction_bps = 0;
2989 dbginfo.num_data_bps = 1;
2990 dbginfo.num_condition_regs = 0;
2991 #ifdef CONFIG_PPC64
2992 dbginfo.data_bp_alignment = 8;
2993 #else
2994 dbginfo.data_bp_alignment = 4;
2995 #endif
2996 dbginfo.sizeof_condition = 0;
2997 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2998 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
2999 if (cpu_has_feature(CPU_FTR_DAWR))
3000 dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
3001 #else
3002 dbginfo.features = 0;
3003 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
3004 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
3005
3006 if (!access_ok(VERIFY_WRITE, datavp,
3007 sizeof(struct ppc_debug_info)))
3008 return -EFAULT;
3009 ret = __copy_to_user(datavp, &dbginfo,
3010 sizeof(struct ppc_debug_info)) ?
3011 -EFAULT : 0;
3012 break;
3013 }
3014
3015 case PPC_PTRACE_SETHWDEBUG: {
3016 struct ppc_hw_breakpoint bp_info;
3017
3018 if (!access_ok(VERIFY_READ, datavp,
3019 sizeof(struct ppc_hw_breakpoint)))
3020 return -EFAULT;
3021 ret = __copy_from_user(&bp_info, datavp,
3022 sizeof(struct ppc_hw_breakpoint)) ?
3023 -EFAULT : 0;
3024 if (!ret)
3025 ret = ppc_set_hwdebug(child, &bp_info);
3026 break;
3027 }
3028
3029 case PPC_PTRACE_DELHWDEBUG: {
3030 ret = ppc_del_hwdebug(child, data);
3031 break;
3032 }
3033
3034 case PTRACE_GET_DEBUGREG: {
3035 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
3036 unsigned long dabr_fake;
3037 #endif
3038 ret = -EINVAL;
3039 /* We only support one DABR and no IABRS at the moment */
3040 if (addr > 0)
3041 break;
3042 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
3043 ret = put_user(child->thread.debug.dac1, datalp);
3044 #else
3045 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
3046 (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
3047 ret = put_user(dabr_fake, datalp);
3048 #endif
3049 break;
3050 }
3051
3052 case PTRACE_SET_DEBUGREG:
3053 ret = ptrace_set_debugreg(child, addr, data);
3054 break;
3055
3056 #ifdef CONFIG_PPC64
3057 case PTRACE_GETREGS64:
3058 #endif
3059 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
3060 return copy_regset_to_user(child, &user_ppc_native_view,
3061 REGSET_GPR,
3062 0, sizeof(struct pt_regs),
3063 datavp);
3064
3065 #ifdef CONFIG_PPC64
3066 case PTRACE_SETREGS64:
3067 #endif
3068 case PTRACE_SETREGS: /* Set all gp regs in the child. */
3069 return copy_regset_from_user(child, &user_ppc_native_view,
3070 REGSET_GPR,
3071 0, sizeof(struct pt_regs),
3072 datavp);
3073
3074 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
3075 return copy_regset_to_user(child, &user_ppc_native_view,
3076 REGSET_FPR,
3077 0, sizeof(elf_fpregset_t),
3078 datavp);
3079
3080 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
3081 return copy_regset_from_user(child, &user_ppc_native_view,
3082 REGSET_FPR,
3083 0, sizeof(elf_fpregset_t),
3084 datavp);
3085
3086 #ifdef CONFIG_ALTIVEC
3087 case PTRACE_GETVRREGS:
3088 return copy_regset_to_user(child, &user_ppc_native_view,
3089 REGSET_VMX,
3090 0, (33 * sizeof(vector128) +
3091 sizeof(u32)),
3092 datavp);
3093
3094 case PTRACE_SETVRREGS:
3095 return copy_regset_from_user(child, &user_ppc_native_view,
3096 REGSET_VMX,
3097 0, (33 * sizeof(vector128) +
3098 sizeof(u32)),
3099 datavp);
3100 #endif
3101 #ifdef CONFIG_VSX
3102 case PTRACE_GETVSRREGS:
3103 return copy_regset_to_user(child, &user_ppc_native_view,
3104 REGSET_VSX,
3105 0, 32 * sizeof(double),
3106 datavp);
3107
3108 case PTRACE_SETVSRREGS:
3109 return copy_regset_from_user(child, &user_ppc_native_view,
3110 REGSET_VSX,
3111 0, 32 * sizeof(double),
3112 datavp);
3113 #endif
3114 #ifdef CONFIG_SPE
3115 case PTRACE_GETEVRREGS:
3116 /* Get the child spe register state. */
3117 return copy_regset_to_user(child, &user_ppc_native_view,
3118 REGSET_SPE, 0, 35 * sizeof(u32),
3119 datavp);
3120
3121 case PTRACE_SETEVRREGS:
3122 /* Set the child spe register state. */
3123 return copy_regset_from_user(child, &user_ppc_native_view,
3124 REGSET_SPE, 0, 35 * sizeof(u32),
3125 datavp);
3126 #endif
3127
3128 default:
3129 ret = ptrace_request(child, request, addr, data);
3130 break;
3131 }
3132 return ret;
3133 }
3134
3135 #ifdef CONFIG_SECCOMP
3136 static int do_seccomp(struct pt_regs *regs)
3137 {
3138 if (!test_thread_flag(TIF_SECCOMP))
3139 return 0;
3140
3141 /*
3142 * The ABI we present to seccomp tracers is that r3 contains
3143 * the syscall return value and orig_gpr3 contains the first
3144 * syscall parameter. This is different to the ptrace ABI where
3145 * both r3 and orig_gpr3 contain the first syscall parameter.
3146 */
3147 regs->gpr[3] = -ENOSYS;
3148
3149 /*
3150 * We use the __ version here because we have already checked
3151 * TIF_SECCOMP. If this fails, there is nothing left to do, we
3152 * have already loaded -ENOSYS into r3, or seccomp has put
3153 * something else in r3 (via SECCOMP_RET_ERRNO/TRACE).
3154 */
3155 if (__secure_computing(NULL))
3156 return -1;
3157
3158 /*
3159 * The syscall was allowed by seccomp, restore the register
3160 * state to what audit expects.
3161 * Note that we use orig_gpr3, which means a seccomp tracer can
3162 * modify the first syscall parameter (in orig_gpr3) and also
3163 * allow the syscall to proceed.
3164 */
3165 regs->gpr[3] = regs->orig_gpr3;
3166
3167 return 0;
3168 }
3169 #else
3170 static inline int do_seccomp(struct pt_regs *regs) { return 0; }
3171 #endif /* CONFIG_SECCOMP */
3172
3173 /**
3174 * do_syscall_trace_enter() - Do syscall tracing on kernel entry.
3175 * @regs: the pt_regs of the task to trace (current)
3176 *
3177 * Performs various types of tracing on syscall entry. This includes seccomp,
3178 * ptrace, syscall tracepoints and audit.
3179 *
3180 * The pt_regs are potentially visible to userspace via ptrace, so their
3181 * contents is ABI.
3182 *
3183 * One or more of the tracers may modify the contents of pt_regs, in particular
3184 * to modify arguments or even the syscall number itself.
3185 *
3186 * It's also possible that a tracer can choose to reject the system call. In
3187 * that case this function will return an illegal syscall number, and will put
3188 * an appropriate return value in regs->r3.
3189 *
3190 * Return: the (possibly changed) syscall number.
3191 */
3192 long do_syscall_trace_enter(struct pt_regs *regs)
3193 {
3194 user_exit();
3195
3196 /*
3197 * The tracer may decide to abort the syscall, if so tracehook
3198 * will return !0. Note that the tracer may also just change
3199 * regs->gpr[0] to an invalid syscall number, that is handled
3200 * below on the exit path.
3201 */
3202 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
3203 tracehook_report_syscall_entry(regs))
3204 goto skip;
3205
3206 /* Run seccomp after ptrace; allow it to set gpr[3]. */
3207 if (do_seccomp(regs))
3208 return -1;
3209
3210 /* Avoid trace and audit when syscall is invalid. */
3211 if (regs->gpr[0] >= NR_syscalls)
3212 goto skip;
3213
3214 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
3215 trace_sys_enter(regs, regs->gpr[0]);
3216
3217 #ifdef CONFIG_PPC64
3218 if (!is_32bit_task())
3219 audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4],
3220 regs->gpr[5], regs->gpr[6]);
3221 else
3222 #endif
3223 audit_syscall_entry(regs->gpr[0],
3224 regs->gpr[3] & 0xffffffff,
3225 regs->gpr[4] & 0xffffffff,
3226 regs->gpr[5] & 0xffffffff,
3227 regs->gpr[6] & 0xffffffff);
3228
3229 /* Return the possibly modified but valid syscall number */
3230 return regs->gpr[0];
3231
3232 skip:
3233 /*
3234 * If we are aborting explicitly, or if the syscall number is
3235 * now invalid, set the return value to -ENOSYS.
3236 */
3237 regs->gpr[3] = -ENOSYS;
3238 return -1;
3239 }
3240
3241 void do_syscall_trace_leave(struct pt_regs *regs)
3242 {
3243 int step;
3244
3245 audit_syscall_exit(regs);
3246
3247 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
3248 trace_sys_exit(regs, regs->result);
3249
3250 step = test_thread_flag(TIF_SINGLESTEP);
3251 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
3252 tracehook_report_syscall_exit(regs, step);
3253
3254 user_enter();
3255 }
Linux with added FPC-III support