staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / clk / actions / owl-gate.c
blobf11500ba46a72c4342b4b58d0758a0ad147c00d8
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // OWL gate clock driver
4 //
5 // Copyright (c) 2014 Actions Semi Inc.
6 // Author: David Liu <liuwei@actions-semi.com>
7 //
8 // Copyright (c) 2018 Linaro Ltd.
9 // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
11 #include <linux/clk-provider.h>
12 #include <linux/regmap.h>
14 #include "owl-gate.h"
16 void owl_gate_set(const struct owl_clk_common *common,
17 const struct owl_gate_hw *gate_hw, bool enable)
19 int set = gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
20 u32 reg;
22 set ^= enable;
24 regmap_read(common->regmap, gate_hw->reg, &reg);
26 if (set)
27 reg |= BIT(gate_hw->bit_idx);
28 else
29 reg &= ~BIT(gate_hw->bit_idx);
31 regmap_write(common->regmap, gate_hw->reg, reg);
34 static void owl_gate_disable(struct clk_hw *hw)
36 struct owl_gate *gate = hw_to_owl_gate(hw);
37 struct owl_clk_common *common = &gate->common;
39 owl_gate_set(common, &gate->gate_hw, false);
42 static int owl_gate_enable(struct clk_hw *hw)
44 struct owl_gate *gate = hw_to_owl_gate(hw);
45 struct owl_clk_common *common = &gate->common;
47 owl_gate_set(common, &gate->gate_hw, true);
49 return 0;
52 int owl_gate_clk_is_enabled(const struct owl_clk_common *common,
53 const struct owl_gate_hw *gate_hw)
55 u32 reg;
57 regmap_read(common->regmap, gate_hw->reg, &reg);
59 if (gate_hw->gate_flags & CLK_GATE_SET_TO_DISABLE)
60 reg ^= BIT(gate_hw->bit_idx);
62 return !!(reg & BIT(gate_hw->bit_idx));
65 static int owl_gate_is_enabled(struct clk_hw *hw)
67 struct owl_gate *gate = hw_to_owl_gate(hw);
68 struct owl_clk_common *common = &gate->common;
70 return owl_gate_clk_is_enabled(common, &gate->gate_hw);
73 const struct clk_ops owl_gate_ops = {
74 .disable = owl_gate_disable,
75 .enable = owl_gate_enable,
76 .is_enabled = owl_gate_is_enabled,