drivers/clk/meson/axg-aoclk.h

   1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
   2 /*
   3  * Copyright (c) 2017 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  *
   6  * Copyright (c) 2018 Amlogic, inc.
   7  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
   8  */
   9
  10 #ifndef __AXG_AOCLKC_H
  11 #define __AXG_AOCLKC_H
  12
  13 #define NR_CLKS 11
  14 /* AO Configuration Clock registers offsets
  15  * Register offsets from the data sheet must be multiplied by 4.
  16  */
  17 #define AO_RTI_PWR_CNTL_REG1    0x0C
  18 #define AO_RTI_PWR_CNTL_REG0    0x10
  19 #define AO_RTI_GEN_CNTL_REG0    0x40
  20 #define AO_OSCIN_CNTL           0x58
  21 #define AO_CRT_CLK_CNTL1        0x68
  22 #define AO_SAR_CLK              0x90
  23 #define AO_RTC_ALT_CLK_CNTL0    0x94
  24 #define AO_RTC_ALT_CLK_CNTL1    0x98
  25
  26 #include <dt-bindings/clock/axg-aoclkc.h>
  27 #include <dt-bindings/reset/axg-aoclkc.h>
  28
  29 #endif /* __AXG_AOCLKC_H */