arch/arm/mach-at91/at91rm9200.c

   1 /*
   2  * arch/arm/mach-at91/at91rm9200.c
   3  *
   4  *  Copyright (C) 2005 SAN People
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14
  15 #include <asm/irq.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/map.h>
  18 #include <mach/at91rm9200.h>
  19 #include <mach/at91_pmc.h>
  20 #include <mach/at91_st.h>
  21 #include <mach/cpu.h>
  22
  23 #include "generic.h"
  24 #include "clock.h"
  25
  26 static struct map_desc at91rm9200_io_desc[] __initdata = {
  27         {
  28                 .virtual        = AT91_VA_BASE_SYS,
  29                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  30                 .length         = SZ_4K,
  31                 .type           = MT_DEVICE,
  32         }, {
  33                 .virtual        = AT91_VA_BASE_EMAC,
  34                 .pfn            = __phys_to_pfn(AT91RM9200_BASE_EMAC),
  35                 .length         = SZ_16K,
  36                 .type           = MT_DEVICE,
  37         }, {
  38                 .virtual        = AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE,
  39                 .pfn            = __phys_to_pfn(AT91RM9200_SRAM_BASE),
  40                 .length         = AT91RM9200_SRAM_SIZE,
  41                 .type           = MT_DEVICE,
  42         },
  43 };
  44
  45 /* --------------------------------------------------------------------
  46  *  Clocks
  47  * -------------------------------------------------------------------- */
  48
  49 /*
  50  * The peripheral clocks.
  51  */
  52 static struct clk udc_clk = {
  53         .name           = "udc_clk",
  54         .pmc_mask       = 1 << AT91RM9200_ID_UDP,
  55         .type           = CLK_TYPE_PERIPHERAL,
  56 };
  57 static struct clk ohci_clk = {
  58         .name           = "ohci_clk",
  59         .pmc_mask       = 1 << AT91RM9200_ID_UHP,
  60         .type           = CLK_TYPE_PERIPHERAL,
  61 };
  62 static struct clk ether_clk = {
  63         .name           = "ether_clk",
  64         .pmc_mask       = 1 << AT91RM9200_ID_EMAC,
  65         .type           = CLK_TYPE_PERIPHERAL,
  66 };
  67 static struct clk mmc_clk = {
  68         .name           = "mci_clk",
  69         .pmc_mask       = 1 << AT91RM9200_ID_MCI,
  70         .type           = CLK_TYPE_PERIPHERAL,
  71 };
  72 static struct clk twi_clk = {
  73         .name           = "twi_clk",
  74         .pmc_mask       = 1 << AT91RM9200_ID_TWI,
  75         .type           = CLK_TYPE_PERIPHERAL,
  76 };
  77 static struct clk usart0_clk = {
  78         .name           = "usart0_clk",
  79         .pmc_mask       = 1 << AT91RM9200_ID_US0,
  80         .type           = CLK_TYPE_PERIPHERAL,
  81 };
  82 static struct clk usart1_clk = {
  83         .name           = "usart1_clk",
  84         .pmc_mask       = 1 << AT91RM9200_ID_US1,
  85         .type           = CLK_TYPE_PERIPHERAL,
  86 };
  87 static struct clk usart2_clk = {
  88         .name           = "usart2_clk",
  89         .pmc_mask       = 1 << AT91RM9200_ID_US2,
  90         .type           = CLK_TYPE_PERIPHERAL,
  91 };
  92 static struct clk usart3_clk = {
  93         .name           = "usart3_clk",
  94         .pmc_mask       = 1 << AT91RM9200_ID_US3,
  95         .type           = CLK_TYPE_PERIPHERAL,
  96 };
  97 static struct clk spi_clk = {
  98         .name           = "spi_clk",
  99         .pmc_mask       = 1 << AT91RM9200_ID_SPI,
 100         .type           = CLK_TYPE_PERIPHERAL,
 101 };
 102 static struct clk pioA_clk = {
 103         .name           = "pioA_clk",
 104         .pmc_mask       = 1 << AT91RM9200_ID_PIOA,
 105         .type           = CLK_TYPE_PERIPHERAL,
 106 };
 107 static struct clk pioB_clk = {
 108         .name           = "pioB_clk",
 109         .pmc_mask       = 1 << AT91RM9200_ID_PIOB,
 110         .type           = CLK_TYPE_PERIPHERAL,
 111 };
 112 static struct clk pioC_clk = {
 113         .name           = "pioC_clk",
 114         .pmc_mask       = 1 << AT91RM9200_ID_PIOC,
 115         .type           = CLK_TYPE_PERIPHERAL,
 116 };
 117 static struct clk pioD_clk = {
 118         .name           = "pioD_clk",
 119         .pmc_mask       = 1 << AT91RM9200_ID_PIOD,
 120         .type           = CLK_TYPE_PERIPHERAL,
 121 };
 122 static struct clk ssc0_clk = {
 123         .name           = "ssc0_clk",
 124         .pmc_mask       = 1 << AT91RM9200_ID_SSC0,
 125         .type           = CLK_TYPE_PERIPHERAL,
 126 };
 127 static struct clk ssc1_clk = {
 128         .name           = "ssc1_clk",
 129         .pmc_mask       = 1 << AT91RM9200_ID_SSC1,
 130         .type           = CLK_TYPE_PERIPHERAL,
 131 };
 132 static struct clk ssc2_clk = {
 133         .name           = "ssc2_clk",
 134         .pmc_mask       = 1 << AT91RM9200_ID_SSC2,
 135         .type           = CLK_TYPE_PERIPHERAL,
 136 };
 137 static struct clk tc0_clk = {
 138         .name           = "tc0_clk",
 139         .pmc_mask       = 1 << AT91RM9200_ID_TC0,
 140         .type           = CLK_TYPE_PERIPHERAL,
 141 };
 142 static struct clk tc1_clk = {
 143         .name           = "tc1_clk",
 144         .pmc_mask       = 1 << AT91RM9200_ID_TC1,
 145         .type           = CLK_TYPE_PERIPHERAL,
 146 };
 147 static struct clk tc2_clk = {
 148         .name           = "tc2_clk",
 149         .pmc_mask       = 1 << AT91RM9200_ID_TC2,
 150         .type           = CLK_TYPE_PERIPHERAL,
 151 };
 152 static struct clk tc3_clk = {
 153         .name           = "tc3_clk",
 154         .pmc_mask       = 1 << AT91RM9200_ID_TC3,
 155         .type           = CLK_TYPE_PERIPHERAL,
 156 };
 157 static struct clk tc4_clk = {
 158         .name           = "tc4_clk",
 159         .pmc_mask       = 1 << AT91RM9200_ID_TC4,
 160         .type           = CLK_TYPE_PERIPHERAL,
 161 };
 162 static struct clk tc5_clk = {
 163         .name           = "tc5_clk",
 164         .pmc_mask       = 1 << AT91RM9200_ID_TC5,
 165         .type           = CLK_TYPE_PERIPHERAL,
 166 };
 167
 168 static struct clk *periph_clocks[] __initdata = {
 169         &pioA_clk,
 170         &pioB_clk,
 171         &pioC_clk,
 172         &pioD_clk,
 173         &usart0_clk,
 174         &usart1_clk,
 175         &usart2_clk,
 176         &usart3_clk,
 177         &mmc_clk,
 178         &udc_clk,
 179         &twi_clk,
 180         &spi_clk,
 181         &ssc0_clk,
 182         &ssc1_clk,
 183         &ssc2_clk,
 184         &tc0_clk,
 185         &tc1_clk,
 186         &tc2_clk,
 187         &tc3_clk,
 188         &tc4_clk,
 189         &tc5_clk,
 190         &ohci_clk,
 191         &ether_clk,
 192         // irq0 .. irq6
 193 };
 194
 195 static struct clk_lookup periph_clocks_lookups[] = {
 196         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
 197         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
 198         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
 199         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
 200         CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
 201         CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
 202         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 203         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 204         CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk),
 205 };
 206
 207 static struct clk_lookup usart_clocks_lookups[] = {
 208         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 209         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 210         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 211         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 212         CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
 213 };
 214
 215 /*
 216  * The four programmable clocks.
 217  * You must configure pin multiplexing to bring these signals out.
 218  */
 219 static struct clk pck0 = {
 220         .name           = "pck0",
 221         .pmc_mask       = AT91_PMC_PCK0,
 222         .type           = CLK_TYPE_PROGRAMMABLE,
 223         .id             = 0,
 224 };
 225 static struct clk pck1 = {
 226         .name           = "pck1",
 227         .pmc_mask       = AT91_PMC_PCK1,
 228         .type           = CLK_TYPE_PROGRAMMABLE,
 229         .id             = 1,
 230 };
 231 static struct clk pck2 = {
 232         .name           = "pck2",
 233         .pmc_mask       = AT91_PMC_PCK2,
 234         .type           = CLK_TYPE_PROGRAMMABLE,
 235         .id             = 2,
 236 };
 237 static struct clk pck3 = {
 238         .name           = "pck3",
 239         .pmc_mask       = AT91_PMC_PCK3,
 240         .type           = CLK_TYPE_PROGRAMMABLE,
 241         .id             = 3,
 242 };
 243
 244 static void __init at91rm9200_register_clocks(void)
 245 {
 246         int i;
 247
 248         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 249                 clk_register(periph_clocks[i]);
 250
 251         clkdev_add_table(periph_clocks_lookups,
 252                          ARRAY_SIZE(periph_clocks_lookups));
 253         clkdev_add_table(usart_clocks_lookups,
 254                          ARRAY_SIZE(usart_clocks_lookups));
 255
 256         clk_register(&pck0);
 257         clk_register(&pck1);
 258         clk_register(&pck2);
 259         clk_register(&pck3);
 260 }
 261
 262 static struct clk_lookup console_clock_lookup;
 263
 264 void __init at91rm9200_set_console_clock(int id)
 265 {
 266         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 267                 return;
 268
 269         console_clock_lookup.con_id = "usart";
 270         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 271         clkdev_add(&console_clock_lookup);
 272 }
 273
 274 /* --------------------------------------------------------------------
 275  *  GPIO
 276  * -------------------------------------------------------------------- */
 277
 278 static struct at91_gpio_bank at91rm9200_gpio[] = {
 279         {
 280                 .id             = AT91RM9200_ID_PIOA,
 281                 .offset         = AT91_PIOA,
 282                 .clock          = &pioA_clk,
 283         }, {
 284                 .id             = AT91RM9200_ID_PIOB,
 285                 .offset         = AT91_PIOB,
 286                 .clock          = &pioB_clk,
 287         }, {
 288                 .id             = AT91RM9200_ID_PIOC,
 289                 .offset         = AT91_PIOC,
 290                 .clock          = &pioC_clk,
 291         }, {
 292                 .id             = AT91RM9200_ID_PIOD,
 293                 .offset         = AT91_PIOD,
 294                 .clock          = &pioD_clk,
 295         }
 296 };
 297
 298 static void at91rm9200_reset(void)
 299 {
 300         /*
 301          * Perform a hardware reset with the use of the Watchdog timer.
 302          */
 303         at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
 304         at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
 305 }
 306
 307 int rm9200_type;
 308 EXPORT_SYMBOL(rm9200_type);
 309
 310 void __init at91rm9200_set_type(int type)
 311 {
 312         rm9200_type = type;
 313 }
 314
 315 /* --------------------------------------------------------------------
 316  *  AT91RM9200 processor initialization
 317  * -------------------------------------------------------------------- */
 318 void __init at91rm9200_map_io(void)
 319 {
 320         /* Map peripherals */
 321         iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
 322 }
 323
 324 void __init at91rm9200_initialize(unsigned long main_clock)
 325 {
 326         at91_arch_reset = at91rm9200_reset;
 327         at91_extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
 328                         | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
 329                         | (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
 330                         | (1 << AT91RM9200_ID_IRQ6);
 331
 332         /* Init clock subsystem */
 333         at91_clock_init(main_clock);
 334
 335         /* Register the processor-specific clocks */
 336         at91rm9200_register_clocks();
 337
 338         /* Initialize GPIO subsystem */
 339         at91_gpio_init(at91rm9200_gpio,
 340                 cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
 341 }
 342
 343
 344 /* --------------------------------------------------------------------
 345  *  Interrupt initialization
 346  * -------------------------------------------------------------------- */
 347
 348 /*
 349  * The default interrupt priority levels (0 = lowest, 7 = highest).
 350  */
 351 static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
 352         7,      /* Advanced Interrupt Controller (FIQ) */
 353         7,      /* System Peripherals */
 354         1,      /* Parallel IO Controller A */
 355         1,      /* Parallel IO Controller B */
 356         1,      /* Parallel IO Controller C */
 357         1,      /* Parallel IO Controller D */
 358         5,      /* USART 0 */
 359         5,      /* USART 1 */
 360         5,      /* USART 2 */
 361         5,      /* USART 3 */
 362         0,      /* Multimedia Card Interface */
 363         2,      /* USB Device Port */
 364         6,      /* Two-Wire Interface */
 365         5,      /* Serial Peripheral Interface */
 366         4,      /* Serial Synchronous Controller 0 */
 367         4,      /* Serial Synchronous Controller 1 */
 368         4,      /* Serial Synchronous Controller 2 */
 369         0,      /* Timer Counter 0 */
 370         0,      /* Timer Counter 1 */
 371         0,      /* Timer Counter 2 */
 372         0,      /* Timer Counter 3 */
 373         0,      /* Timer Counter 4 */
 374         0,      /* Timer Counter 5 */
 375         2,      /* USB Host port */
 376         3,      /* Ethernet MAC */
 377         0,      /* Advanced Interrupt Controller (IRQ0) */
 378         0,      /* Advanced Interrupt Controller (IRQ1) */
 379         0,      /* Advanced Interrupt Controller (IRQ2) */
 380         0,      /* Advanced Interrupt Controller (IRQ3) */
 381         0,      /* Advanced Interrupt Controller (IRQ4) */
 382         0,      /* Advanced Interrupt Controller (IRQ5) */
 383         0       /* Advanced Interrupt Controller (IRQ6) */
 384 };
 385
 386 void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 387 {
 388         if (!priority)
 389                 priority = at91rm9200_default_irq_priority;
 390
 391         /* Initialize the AIC interrupt controller */
 392         at91_aic_init(priority);
 393
 394         /* Enable GPIO interrupts */
 395         at91_gpio_irq_setup();
 396 }