2 * Copyright 2008 Cavium Networks
4 * This file is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License, Version 2, as
6 * published by the Free Software Foundation.
9 #include <linux/init.h>
10 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <asm/atomic.h>
14 #include <mach/system.h>
15 #include <mach/cns3xxx.h>
18 void cns3xxx_pwr_clk_en(unsigned int block
)
20 u32 reg
= __raw_readl(PM_CLK_GATE_REG
);
22 reg
|= (block
& PM_CLK_GATE_REG_MASK
);
23 __raw_writel(reg
, PM_CLK_GATE_REG
);
25 EXPORT_SYMBOL(cns3xxx_pwr_clk_en
);
27 void cns3xxx_pwr_clk_dis(unsigned int block
)
29 u32 reg
= __raw_readl(PM_CLK_GATE_REG
);
31 reg
&= ~(block
& PM_CLK_GATE_REG_MASK
);
32 __raw_writel(reg
, PM_CLK_GATE_REG
);
34 EXPORT_SYMBOL(cns3xxx_pwr_clk_dis
);
36 void cns3xxx_pwr_power_up(unsigned int block
)
38 u32 reg
= __raw_readl(PM_PLL_HM_PD_CTRL_REG
);
40 reg
&= ~(block
& CNS3XXX_PWR_PLL_ALL
);
41 __raw_writel(reg
, PM_PLL_HM_PD_CTRL_REG
);
43 /* Wait for 300us for the PLL output clock locked. */
46 EXPORT_SYMBOL(cns3xxx_pwr_power_up
);
48 void cns3xxx_pwr_power_down(unsigned int block
)
50 u32 reg
= __raw_readl(PM_PLL_HM_PD_CTRL_REG
);
52 /* write '1' to power down */
53 reg
|= (block
& CNS3XXX_PWR_PLL_ALL
);
54 __raw_writel(reg
, PM_PLL_HM_PD_CTRL_REG
);
56 EXPORT_SYMBOL(cns3xxx_pwr_power_down
);
58 static void cns3xxx_pwr_soft_rst_force(unsigned int block
)
60 u32 reg
= __raw_readl(PM_SOFT_RST_REG
);
63 * bit 0, 28, 29 => program low to reset,
64 * the other else program low and then high
66 if (block
& 0x30000001) {
67 reg
&= ~(block
& PM_SOFT_RST_REG_MASK
);
69 reg
&= ~(block
& PM_SOFT_RST_REG_MASK
);
70 __raw_writel(reg
, PM_SOFT_RST_REG
);
71 reg
|= (block
& PM_SOFT_RST_REG_MASK
);
74 __raw_writel(reg
, PM_SOFT_RST_REG
);
76 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force
);
78 void cns3xxx_pwr_soft_rst(unsigned int block
)
80 static unsigned int soft_reset
;
82 if (soft_reset
& block
) {
83 /* SPI/I2C/GPIO use the same block, reset once. */
88 cns3xxx_pwr_soft_rst_force(block
);
90 EXPORT_SYMBOL(cns3xxx_pwr_soft_rst
);
92 void arch_reset(char mode
, const char *cmd
)
95 * To reset, we hit the on-board reset register
98 cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL
));
102 * cns3xxx_cpu_clock - return CPU/L2 clock
107 int cns3xxx_cpu_clock(void)
109 u32 reg
= __raw_readl(PM_CLK_CTRL_REG
);
114 cpu_sel
= (reg
>> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL
) & 0xf;
115 div_sel
= (reg
>> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV
) & 0x3;
117 cpu
= (300 + ((cpu_sel
/ 3) * 100) + ((cpu_sel
% 3) * 33)) >> div_sel
;
121 EXPORT_SYMBOL(cns3xxx_cpu_clock
);
123 atomic_t usb_pwr_ref
= ATOMIC_INIT(0);
124 EXPORT_SYMBOL(usb_pwr_ref
);