arch/arm/mach-msm/platsmp.c

   1 /*
   2  *  Copyright (C) 2002 ARM Ltd.
   3  *  All Rights Reserved
   4  *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/errno.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/smp.h>
  17 #include <linux/io.h>
  18
  19 #include <asm/hardware/gic.h>
  20 #include <asm/cacheflush.h>
  21 #include <asm/mach-types.h>
  22
  23 #include <mach/msm_iomap.h>
  24
  25 #include "scm-boot.h"
  26
  27 #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x15A0
  28 #define SCSS_CPU1CORE_RESET 0xD80
  29 #define SCSS_DBG_STATUS_CORE_PWRDUP 0xE64
  30
  31 /* Mask for edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
  32 #define GIC_PPI_EDGE_MASK 0xFFFFD7FF
  33
  34 extern void msm_secondary_startup(void);
  35 /*
  36  * control for which core is the next to come out of the secondary
  37  * boot "holding pen".
  38  */
  39 volatile int pen_release = -1;
  40
  41 static DEFINE_SPINLOCK(boot_lock);
  42
  43 void __cpuinit platform_secondary_init(unsigned int cpu)
  44 {
  45         /* Configure edge-triggered PPIs */
  46         writel(GIC_PPI_EDGE_MASK, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
  47
  48         /*
  49          * if any interrupts are already enabled for the primary
  50          * core (e.g. timer irq), then they will not have been enabled
  51          * for us: do so
  52          */
  53         gic_secondary_init(0);
  54
  55         /*
  56          * let the primary processor know we're out of the
  57          * pen, then head off into the C entry point
  58          */
  59         pen_release = -1;
  60         smp_wmb();
  61
  62         /*
  63          * Synchronise with the boot thread.
  64          */
  65         spin_lock(&boot_lock);
  66         spin_unlock(&boot_lock);
  67 }
  68
  69 static __cpuinit void prepare_cold_cpu(unsigned int cpu)
  70 {
  71         int ret;
  72         ret = scm_set_boot_addr(virt_to_phys(msm_secondary_startup),
  73                                 SCM_FLAG_COLDBOOT_CPU1);
  74         if (ret == 0) {
  75                 void *sc1_base_ptr;
  76                 sc1_base_ptr = ioremap_nocache(0x00902000, SZ_4K*2);
  77                 if (sc1_base_ptr) {
  78                         writel(0, sc1_base_ptr + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
  79                         writel(0, sc1_base_ptr + SCSS_CPU1CORE_RESET);
  80                         writel(3, sc1_base_ptr + SCSS_DBG_STATUS_CORE_PWRDUP);
  81                         iounmap(sc1_base_ptr);
  82                 }
  83         } else
  84                 printk(KERN_DEBUG "Failed to set secondary core boot "
  85                                   "address\n");
  86 }
  87
  88 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  89 {
  90         unsigned long timeout;
  91         static int cold_boot_done;
  92
  93         /* Only need to bring cpu out of reset this way once */
  94         if (cold_boot_done == false) {
  95                 prepare_cold_cpu(cpu);
  96                 cold_boot_done = true;
  97         }
  98
  99         /*
 100          * set synchronisation state between this boot processor
 101          * and the secondary one
 102          */
 103         spin_lock(&boot_lock);
 104
 105         /*
 106          * The secondary processor is waiting to be released from
 107          * the holding pen - release it, then wait for it to flag
 108          * that it has been released by resetting pen_release.
 109          *
 110          * Note that "pen_release" is the hardware CPU ID, whereas
 111          * "cpu" is Linux's internal ID.
 112          */
 113         pen_release = cpu;
 114         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 115         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 116
 117         /*
 118          * Send the secondary CPU a soft interrupt, thereby causing
 119          * the boot monitor to read the system wide flags register,
 120          * and branch to the address found there.
 121          */
 122         gic_raise_softirq(cpumask_of(cpu), 1);
 123
 124         timeout = jiffies + (1 * HZ);
 125         while (time_before(jiffies, timeout)) {
 126                 smp_rmb();
 127                 if (pen_release == -1)
 128                         break;
 129
 130                 udelay(10);
 131         }
 132
 133         /*
 134          * now the secondary core is starting up let it run its
 135          * calibrations, then wait for it to finish
 136          */
 137         spin_unlock(&boot_lock);
 138
 139         return pen_release != -1 ? -ENOSYS : 0;
 140 }
 141
 142 /*
 143  * Initialise the CPU possible map early - this describes the CPUs
 144  * which may be present or become present in the system. The msm8x60
 145  * does not support the ARM SCU, so just set the possible cpu mask to
 146  * NR_CPUS.
 147  */
 148 void __init smp_init_cpus(void)
 149 {
 150         unsigned int i;
 151
 152         for (i = 0; i < NR_CPUS; i++)
 153                 set_cpu_possible(i, true);
 154
 155         set_smp_cross_call(gic_raise_softirq);
 156 }
 157
 158 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 159 {
 160         int i;
 161
 162         /*
 163          * Initialise the present map, which describes the set of CPUs
 164          * actually populated at the present time.
 165          */
 166         for (i = 0; i < max_cpus; i++)
 167                 set_cpu_present(i, true);
 168 }