ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / arch / arm / mach-omap2 / irq.c
blob3af2b7a1045e38d957e40a1f125acb19bc57ba41
1 /*
2 * linux/arch/arm/mach-omap2/irq.c
4 * Interrupt handler for OMAP2 boards.
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <mach/hardware.h>
18 #include <asm/mach/irq.h>
21 /* selected INTC register offsets */
23 #define INTC_REVISION 0x0000
24 #define INTC_SYSCONFIG 0x0010
25 #define INTC_SYSSTATUS 0x0014
26 #define INTC_SIR 0x0040
27 #define INTC_CONTROL 0x0048
28 #define INTC_PROTECTION 0x004C
29 #define INTC_IDLE 0x0050
30 #define INTC_THRESHOLD 0x0068
31 #define INTC_MIR0 0x0084
32 #define INTC_MIR_CLEAR0 0x0088
33 #define INTC_MIR_SET0 0x008c
34 #define INTC_PENDING_IRQ0 0x0098
35 /* Number of IRQ state bits in each MIR register */
36 #define IRQ_BITS_PER_REG 32
39 * OMAP2 has a number of different interrupt controllers, each interrupt
40 * controller is identified as its own "bank". Register definitions are
41 * fairly consistent for each bank, but not all registers are implemented
42 * for each bank.. when in doubt, consult the TRM.
44 static struct omap_irq_bank {
45 void __iomem *base_reg;
46 unsigned int nr_irqs;
47 } __attribute__ ((aligned(4))) irq_banks[] = {
49 /* MPU INTC */
50 .nr_irqs = 96,
54 /* Structure to save interrupt controller context */
55 struct omap3_intc_regs {
56 u32 sysconfig;
57 u32 protection;
58 u32 idle;
59 u32 threshold;
60 u32 ilr[INTCPS_NR_IRQS];
61 u32 mir[INTCPS_NR_MIR_REGS];
64 /* INTC bank register get/set */
66 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
68 __raw_writel(val, bank->base_reg + reg);
71 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
73 return __raw_readl(bank->base_reg + reg);
76 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
77 static void omap_ack_irq(struct irq_data *d)
79 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
82 static void omap_mask_ack_irq(struct irq_data *d)
84 irq_gc_mask_disable_reg(d);
85 omap_ack_irq(d);
88 static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
90 unsigned long tmp;
92 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
93 printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
94 "(revision %ld.%ld) with %d interrupts\n",
95 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
97 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
98 tmp |= 1 << 1; /* soft reset */
99 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
101 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
102 /* Wait for reset to complete */;
104 /* Enable autoidle */
105 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
108 int omap_irq_pending(void)
110 int i;
112 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
113 struct omap_irq_bank *bank = irq_banks + i;
114 int irq;
116 for (irq = 0; irq < bank->nr_irqs; irq += 32)
117 if (intc_bank_read_reg(bank, INTC_PENDING_IRQ0 +
118 ((irq >> 5) << 5)))
119 return 1;
121 return 0;
124 static __init void
125 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
127 struct irq_chip_generic *gc;
128 struct irq_chip_type *ct;
130 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
131 handle_level_irq);
132 ct = gc->chip_types;
133 ct->chip.irq_ack = omap_mask_ack_irq;
134 ct->chip.irq_mask = irq_gc_mask_disable_reg;
135 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
137 ct->regs.ack = INTC_CONTROL;
138 ct->regs.enable = INTC_MIR_CLEAR0;
139 ct->regs.disable = INTC_MIR_SET0;
140 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
141 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
144 void __init omap_init_irq(void)
146 unsigned long nr_of_irqs = 0;
147 unsigned int nr_banks = 0;
148 int i, j;
150 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
151 unsigned long base = 0;
152 struct omap_irq_bank *bank = irq_banks + i;
154 if (cpu_is_omap24xx())
155 base = OMAP24XX_IC_BASE;
156 else if (cpu_is_omap34xx())
157 base = OMAP34XX_IC_BASE;
159 BUG_ON(!base);
161 if (cpu_is_ti816x())
162 bank->nr_irqs = 128;
164 /* Static mapping, never released */
165 bank->base_reg = ioremap(base, SZ_4K);
166 if (!bank->base_reg) {
167 printk(KERN_ERR "Could not ioremap irq bank%i\n", i);
168 continue;
171 omap_irq_bank_init_one(bank);
173 for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
174 omap_alloc_gc(bank->base_reg + j, i, 32);
176 nr_of_irqs += bank->nr_irqs;
177 nr_banks++;
180 printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
181 nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
184 #ifdef CONFIG_ARCH_OMAP3
185 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
187 void omap_intc_save_context(void)
189 int ind = 0, i = 0;
190 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
191 struct omap_irq_bank *bank = irq_banks + ind;
192 intc_context[ind].sysconfig =
193 intc_bank_read_reg(bank, INTC_SYSCONFIG);
194 intc_context[ind].protection =
195 intc_bank_read_reg(bank, INTC_PROTECTION);
196 intc_context[ind].idle =
197 intc_bank_read_reg(bank, INTC_IDLE);
198 intc_context[ind].threshold =
199 intc_bank_read_reg(bank, INTC_THRESHOLD);
200 for (i = 0; i < INTCPS_NR_IRQS; i++)
201 intc_context[ind].ilr[i] =
202 intc_bank_read_reg(bank, (0x100 + 0x4*i));
203 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
204 intc_context[ind].mir[i] =
205 intc_bank_read_reg(&irq_banks[0], INTC_MIR0 +
206 (0x20 * i));
210 void omap_intc_restore_context(void)
212 int ind = 0, i = 0;
214 for (ind = 0; ind < ARRAY_SIZE(irq_banks); ind++) {
215 struct omap_irq_bank *bank = irq_banks + ind;
216 intc_bank_write_reg(intc_context[ind].sysconfig,
217 bank, INTC_SYSCONFIG);
218 intc_bank_write_reg(intc_context[ind].sysconfig,
219 bank, INTC_SYSCONFIG);
220 intc_bank_write_reg(intc_context[ind].protection,
221 bank, INTC_PROTECTION);
222 intc_bank_write_reg(intc_context[ind].idle,
223 bank, INTC_IDLE);
224 intc_bank_write_reg(intc_context[ind].threshold,
225 bank, INTC_THRESHOLD);
226 for (i = 0; i < INTCPS_NR_IRQS; i++)
227 intc_bank_write_reg(intc_context[ind].ilr[i],
228 bank, (0x100 + 0x4*i));
229 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
230 intc_bank_write_reg(intc_context[ind].mir[i],
231 &irq_banks[0], INTC_MIR0 + (0x20 * i));
233 /* MIRs are saved and restore with other PRCM registers */
236 void omap3_intc_suspend(void)
238 /* A pending interrupt would prevent OMAP from entering suspend */
239 omap_ack_irq(0);
242 void omap3_intc_prepare_idle(void)
245 * Disable autoidle as it can stall interrupt controller,
246 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
248 intc_bank_write_reg(0, &irq_banks[0], INTC_SYSCONFIG);
251 void omap3_intc_resume_idle(void)
253 /* Re-enable autoidle */
254 intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
256 #endif /* CONFIG_ARCH_OMAP3 */