ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / arch / arm / mach-omap2 / omap-smp.c
blobecfe93c4b5859d25c333f6f01b2507d882ff3895
1 /*
2 * OMAP4 SMP source file. It contains platform specific fucntions
3 * needed for the linux smp kernel.
5 * Copyright (C) 2009 Texas Instruments, Inc.
7 * Author:
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/smp.h>
21 #include <linux/io.h>
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/gic.h>
25 #include <asm/smp_scu.h>
26 #include <mach/hardware.h>
27 #include <mach/omap4-common.h>
29 /* SCU base address */
30 static void __iomem *scu_base;
32 static DEFINE_SPINLOCK(boot_lock);
34 void __cpuinit platform_secondary_init(unsigned int cpu)
37 * If any interrupts are already enabled for the primary
38 * core (e.g. timer irq), then they will not have been enabled
39 * for us: do so
41 gic_secondary_init(0);
44 * Synchronise with the boot thread.
46 spin_lock(&boot_lock);
47 spin_unlock(&boot_lock);
50 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
53 * Set synchronisation state between this boot processor
54 * and the secondary one
56 spin_lock(&boot_lock);
59 * Update the AuxCoreBoot0 with boot state for secondary core.
60 * omap_secondary_startup() routine will hold the secondary core till
61 * the AuxCoreBoot1 register is updated with cpu state
62 * A barrier is added to ensure that write buffer is drained
64 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
65 flush_cache_all();
66 smp_wmb();
67 gic_raise_softirq(cpumask_of(cpu), 1);
70 * Now the secondary core is starting up let it run its
71 * calibrations, then wait for it to finish
73 spin_unlock(&boot_lock);
75 return 0;
78 static void __init wakeup_secondary(void)
81 * Write the address of secondary startup routine into the
82 * AuxCoreBoot1 where ROM code will jump and start executing
83 * on secondary core once out of WFE
84 * A barrier is added to ensure that write buffer is drained
86 omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup));
87 smp_wmb();
90 * Send a 'sev' to wake the secondary core from WFE.
91 * Drain the outstanding writes to memory
93 dsb_sev();
94 mb();
98 * Initialise the CPU possible map early - this describes the CPUs
99 * which may be present or become present in the system.
101 void __init smp_init_cpus(void)
103 unsigned int i, ncores;
105 /* Never released */
106 scu_base = ioremap(OMAP44XX_SCU_BASE, SZ_256);
107 BUG_ON(!scu_base);
109 ncores = scu_get_core_count(scu_base);
111 /* sanity check */
112 if (ncores > NR_CPUS) {
113 printk(KERN_WARNING
114 "OMAP4: no. of cores (%d) greater than configured "
115 "maximum of %d - clipping\n",
116 ncores, NR_CPUS);
117 ncores = NR_CPUS;
120 for (i = 0; i < ncores; i++)
121 set_cpu_possible(i, true);
123 set_smp_cross_call(gic_raise_softirq);
126 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
128 int i;
131 * Initialise the present map, which describes the set of CPUs
132 * actually populated at the present time.
134 for (i = 0; i < max_cpus; i++)
135 set_cpu_present(i, true);
138 * Initialise the SCU and wake up the secondary core using
139 * wakeup_secondary().
141 scu_enable(scu_base);
142 wakeup_secondary();