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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / arch / x86 / kernel / amd_iommu.c
blobbfd75ff5d5bda6083651eaa23cfc86e8f3a843de
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/pci-ats.h>
22 #include <linux/bitmap.h>
23 #include <linux/slab.h>
24 #include <linux/debugfs.h>
25 #include <linux/scatterlist.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/iommu-helper.h>
28 #include <linux/iommu.h>
29 #include <linux/delay.h>
30 #include <asm/proto.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/dma.h>
34 #include <asm/amd_iommu_proto.h>
35 #include <asm/amd_iommu_types.h>
36 #include <asm/amd_iommu.h>
37
38 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
39
40 #define LOOP_TIMEOUT 100000
41
42 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
43
44 /* A list of preallocated protection domains */
45 static LIST_HEAD(iommu_pd_list);
46 static DEFINE_SPINLOCK(iommu_pd_list_lock);
47
48 /*
49 * Domain for untranslated devices - only allocated
50 * if iommu=pt passed on kernel cmd line.
51 */
52 static struct protection_domain *pt_domain;
53
54 static struct iommu_ops amd_iommu_ops;
55
56 /*
57 * general struct to manage commands send to an IOMMU
58 */
59 struct iommu_cmd {
60 u32 data[4];
61 };
62
63 static void update_domain(struct protection_domain *domain);
64
65 /****************************************************************************
66 *
67 * Helper functions
68 *
69 ****************************************************************************/
70
71 static inline u16 get_device_id(struct device *dev)
72 {
73 struct pci_dev *pdev = to_pci_dev(dev);
74
75 return calc_devid(pdev->bus->number, pdev->devfn);
76 }
77
78 static struct iommu_dev_data *get_dev_data(struct device *dev)
79 {
80 return dev->archdata.iommu;
81 }
82
83 /*
84 * In this function the list of preallocated protection domains is traversed to
85 * find the domain for a specific device
86 */
87 static struct dma_ops_domain *find_protection_domain(u16 devid)
88 {
89 struct dma_ops_domain *entry, *ret = NULL;
90 unsigned long flags;
91 u16 alias = amd_iommu_alias_table[devid];
92
93 if (list_empty(&iommu_pd_list))
94 return NULL;
95
96 spin_lock_irqsave(&iommu_pd_list_lock, flags);
97
98 list_for_each_entry(entry, &iommu_pd_list, list) {
99 if (entry->target_dev == devid ||
100 entry->target_dev == alias) {
101 ret = entry;
102 break;
103 }
104 }
105
106 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
107
108 return ret;
109 }
110
111 /*
112 * This function checks if the driver got a valid device from the caller to
113 * avoid dereferencing invalid pointers.
114 */
115 static bool check_device(struct device *dev)
116 {
117 u16 devid;
118
119 if (!dev || !dev->dma_mask)
120 return false;
121
122 /* No device or no PCI device */
123 if (dev->bus != &pci_bus_type)
124 return false;
125
126 devid = get_device_id(dev);
127
128 /* Out of our scope? */
129 if (devid > amd_iommu_last_bdf)
130 return false;
131
132 if (amd_iommu_rlookup_table[devid] == NULL)
133 return false;
134
135 return true;
136 }
137
138 static int iommu_init_device(struct device *dev)
139 {
140 struct iommu_dev_data *dev_data;
141 struct pci_dev *pdev;
142 u16 devid, alias;
143
144 if (dev->archdata.iommu)
145 return 0;
146
147 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
148 if (!dev_data)
149 return -ENOMEM;
150
151 dev_data->dev = dev;
152
153 devid = get_device_id(dev);
154 alias = amd_iommu_alias_table[devid];
155 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
156 if (pdev)
157 dev_data->alias = &pdev->dev;
158 else {
159 kfree(dev_data);
160 return -ENOTSUPP;
161 }
162
163 atomic_set(&dev_data->bind, 0);
164
165 dev->archdata.iommu = dev_data;
166
167
168 return 0;
169 }
170
171 static void iommu_ignore_device(struct device *dev)
172 {
173 u16 devid, alias;
174
175 devid = get_device_id(dev);
176 alias = amd_iommu_alias_table[devid];
177
178 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
179 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
180
181 amd_iommu_rlookup_table[devid] = NULL;
182 amd_iommu_rlookup_table[alias] = NULL;
183 }
184
185 static void iommu_uninit_device(struct device *dev)
186 {
187 kfree(dev->archdata.iommu);
188 }
189
190 void __init amd_iommu_uninit_devices(void)
191 {
192 struct pci_dev *pdev = NULL;
193
194 for_each_pci_dev(pdev) {
195
196 if (!check_device(&pdev->dev))
197 continue;
198
199 iommu_uninit_device(&pdev->dev);
200 }
201 }
202
203 int __init amd_iommu_init_devices(void)
204 {
205 struct pci_dev *pdev = NULL;
206 int ret = 0;
207
208 for_each_pci_dev(pdev) {
209
210 if (!check_device(&pdev->dev))
211 continue;
212
213 ret = iommu_init_device(&pdev->dev);
214 if (ret == -ENOTSUPP)
215 iommu_ignore_device(&pdev->dev);
216 else if (ret)
217 goto out_free;
218 }
219
220 return 0;
221
222 out_free:
223
224 amd_iommu_uninit_devices();
225
226 return ret;
227 }
228 #ifdef CONFIG_AMD_IOMMU_STATS
229
230 /*
231 * Initialization code for statistics collection
232 */
233
234 DECLARE_STATS_COUNTER(compl_wait);
235 DECLARE_STATS_COUNTER(cnt_map_single);
236 DECLARE_STATS_COUNTER(cnt_unmap_single);
237 DECLARE_STATS_COUNTER(cnt_map_sg);
238 DECLARE_STATS_COUNTER(cnt_unmap_sg);
239 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
240 DECLARE_STATS_COUNTER(cnt_free_coherent);
241 DECLARE_STATS_COUNTER(cross_page);
242 DECLARE_STATS_COUNTER(domain_flush_single);
243 DECLARE_STATS_COUNTER(domain_flush_all);
244 DECLARE_STATS_COUNTER(alloced_io_mem);
245 DECLARE_STATS_COUNTER(total_map_requests);
246
247 static struct dentry *stats_dir;
248 static struct dentry *de_fflush;
249
250 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
251 {
252 if (stats_dir == NULL)
253 return;
254
255 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
256 &cnt->value);
257 }
258
259 static void amd_iommu_stats_init(void)
260 {
261 stats_dir = debugfs_create_dir("amd-iommu", NULL);
262 if (stats_dir == NULL)
263 return;
264
265 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
266 (u32 *)&amd_iommu_unmap_flush);
267
268 amd_iommu_stats_add(&compl_wait);
269 amd_iommu_stats_add(&cnt_map_single);
270 amd_iommu_stats_add(&cnt_unmap_single);
271 amd_iommu_stats_add(&cnt_map_sg);
272 amd_iommu_stats_add(&cnt_unmap_sg);
273 amd_iommu_stats_add(&cnt_alloc_coherent);
274 amd_iommu_stats_add(&cnt_free_coherent);
275 amd_iommu_stats_add(&cross_page);
276 amd_iommu_stats_add(&domain_flush_single);
277 amd_iommu_stats_add(&domain_flush_all);
278 amd_iommu_stats_add(&alloced_io_mem);
279 amd_iommu_stats_add(&total_map_requests);
280 }
281
282 #endif
283
284 /****************************************************************************
285 *
286 * Interrupt handling functions
287 *
288 ****************************************************************************/
289
290 static void dump_dte_entry(u16 devid)
291 {
292 int i;
293
294 for (i = 0; i < 8; ++i)
295 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
296 amd_iommu_dev_table[devid].data[i]);
297 }
298
299 static void dump_command(unsigned long phys_addr)
300 {
301 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
302 int i;
303
304 for (i = 0; i < 4; ++i)
305 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
306 }
307
308 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
309 {
310 u32 *event = __evt;
311 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
312 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
313 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
314 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
315 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
316
317 printk(KERN_ERR "AMD-Vi: Event logged [");
318
319 switch (type) {
320 case EVENT_TYPE_ILL_DEV:
321 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
322 "address=0x%016llx flags=0x%04x]\n",
323 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
324 address, flags);
325 dump_dte_entry(devid);
326 break;
327 case EVENT_TYPE_IO_FAULT:
328 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
329 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
330 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
331 domid, address, flags);
332 break;
333 case EVENT_TYPE_DEV_TAB_ERR:
334 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
335 "address=0x%016llx flags=0x%04x]\n",
336 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
337 address, flags);
338 break;
339 case EVENT_TYPE_PAGE_TAB_ERR:
340 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
341 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
342 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
343 domid, address, flags);
344 break;
345 case EVENT_TYPE_ILL_CMD:
346 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
347 dump_command(address);
348 break;
349 case EVENT_TYPE_CMD_HARD_ERR:
350 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
351 "flags=0x%04x]\n", address, flags);
352 break;
353 case EVENT_TYPE_IOTLB_INV_TO:
354 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
355 "address=0x%016llx]\n",
356 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
357 address);
358 break;
359 case EVENT_TYPE_INV_DEV_REQ:
360 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
361 "address=0x%016llx flags=0x%04x]\n",
362 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
363 address, flags);
364 break;
365 default:
366 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
367 }
368 }
369
370 static void iommu_poll_events(struct amd_iommu *iommu)
371 {
372 u32 head, tail;
373 unsigned long flags;
374
375 spin_lock_irqsave(&iommu->lock, flags);
376
377 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
378 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
379
380 while (head != tail) {
381 iommu_print_event(iommu, iommu->evt_buf + head);
382 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
383 }
384
385 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
386
387 spin_unlock_irqrestore(&iommu->lock, flags);
388 }
389
390 irqreturn_t amd_iommu_int_thread(int irq, void *data)
391 {
392 struct amd_iommu *iommu;
393
394 for_each_iommu(iommu)
395 iommu_poll_events(iommu);
396
397 return IRQ_HANDLED;
398 }
399
400 irqreturn_t amd_iommu_int_handler(int irq, void *data)
401 {
402 return IRQ_WAKE_THREAD;
403 }
404
405 /****************************************************************************
406 *
407 * IOMMU command queuing functions
408 *
409 ****************************************************************************/
410
411 static int wait_on_sem(volatile u64 *sem)
412 {
413 int i = 0;
414
415 while (*sem == 0 && i < LOOP_TIMEOUT) {
416 udelay(1);
417 i += 1;
418 }
419
420 if (i == LOOP_TIMEOUT) {
421 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
422 return -EIO;
423 }
424
425 return 0;
426 }
427
428 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
429 struct iommu_cmd *cmd,
430 u32 tail)
431 {
432 u8 *target;
433
434 target = iommu->cmd_buf + tail;
435 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
436
437 /* Copy command to buffer */
438 memcpy(target, cmd, sizeof(*cmd));
439
440 /* Tell the IOMMU about it */
441 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
442 }
443
444 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
445 {
446 WARN_ON(address & 0x7ULL);
447
448 memset(cmd, 0, sizeof(*cmd));
449 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
450 cmd->data[1] = upper_32_bits(__pa(address));
451 cmd->data[2] = 1;
452 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
453 }
454
455 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
456 {
457 memset(cmd, 0, sizeof(*cmd));
458 cmd->data[0] = devid;
459 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
460 }
461
462 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
463 size_t size, u16 domid, int pde)
464 {
465 u64 pages;
466 int s;
467
468 pages = iommu_num_pages(address, size, PAGE_SIZE);
469 s = 0;
470
471 if (pages > 1) {
472 /*
473 * If we have to flush more than one page, flush all
474 * TLB entries for this domain
475 */
476 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
477 s = 1;
478 }
479
480 address &= PAGE_MASK;
481
482 memset(cmd, 0, sizeof(*cmd));
483 cmd->data[1] |= domid;
484 cmd->data[2] = lower_32_bits(address);
485 cmd->data[3] = upper_32_bits(address);
486 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
487 if (s) /* size bit - we flush more than one 4kb page */
488 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
489 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
490 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
491 }
492
493 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
494 u64 address, size_t size)
495 {
496 u64 pages;
497 int s;
498
499 pages = iommu_num_pages(address, size, PAGE_SIZE);
500 s = 0;
501
502 if (pages > 1) {
503 /*
504 * If we have to flush more than one page, flush all
505 * TLB entries for this domain
506 */
507 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
508 s = 1;
509 }
510
511 address &= PAGE_MASK;
512
513 memset(cmd, 0, sizeof(*cmd));
514 cmd->data[0] = devid;
515 cmd->data[0] |= (qdep & 0xff) << 24;
516 cmd->data[1] = devid;
517 cmd->data[2] = lower_32_bits(address);
518 cmd->data[3] = upper_32_bits(address);
519 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
520 if (s)
521 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
522 }
523
524 static void build_inv_all(struct iommu_cmd *cmd)
525 {
526 memset(cmd, 0, sizeof(*cmd));
527 CMD_SET_TYPE(cmd, CMD_INV_ALL);
528 }
529
530 /*
531 * Writes the command to the IOMMUs command buffer and informs the
532 * hardware about the new command.
533 */
534 static int iommu_queue_command_sync(struct amd_iommu *iommu,
535 struct iommu_cmd *cmd,
536 bool sync)
537 {
538 u32 left, tail, head, next_tail;
539 unsigned long flags;
540
541 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
542
543 again:
544 spin_lock_irqsave(&iommu->lock, flags);
545
546 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
547 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
548 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
549 left = (head - next_tail) % iommu->cmd_buf_size;
550
551 if (left <= 2) {
552 struct iommu_cmd sync_cmd;
553 volatile u64 sem = 0;
554 int ret;
555
556 build_completion_wait(&sync_cmd, (u64)&sem);
557 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
558
559 spin_unlock_irqrestore(&iommu->lock, flags);
560
561 if ((ret = wait_on_sem(&sem)) != 0)
562 return ret;
563
564 goto again;
565 }
566
567 copy_cmd_to_buffer(iommu, cmd, tail);
568
569 /* We need to sync now to make sure all commands are processed */
570 iommu->need_sync = sync;
571
572 spin_unlock_irqrestore(&iommu->lock, flags);
573
574 return 0;
575 }
576
577 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
578 {
579 return iommu_queue_command_sync(iommu, cmd, true);
580 }
581
582 /*
583 * This function queues a completion wait command into the command
584 * buffer of an IOMMU
585 */
586 static int iommu_completion_wait(struct amd_iommu *iommu)
587 {
588 struct iommu_cmd cmd;
589 volatile u64 sem = 0;
590 int ret;
591
592 if (!iommu->need_sync)
593 return 0;
594
595 build_completion_wait(&cmd, (u64)&sem);
596
597 ret = iommu_queue_command_sync(iommu, &cmd, false);
598 if (ret)
599 return ret;
600
601 return wait_on_sem(&sem);
602 }
603
604 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
605 {
606 struct iommu_cmd cmd;
607
608 build_inv_dte(&cmd, devid);
609
610 return iommu_queue_command(iommu, &cmd);
611 }
612
613 static void iommu_flush_dte_all(struct amd_iommu *iommu)
614 {
615 u32 devid;
616
617 for (devid = 0; devid <= 0xffff; ++devid)
618 iommu_flush_dte(iommu, devid);
619
620 iommu_completion_wait(iommu);
621 }
622
623 /*
624 * This function uses heavy locking and may disable irqs for some time. But
625 * this is no issue because it is only called during resume.
626 */
627 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
628 {
629 u32 dom_id;
630
631 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
632 struct iommu_cmd cmd;
633 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
634 dom_id, 1);
635 iommu_queue_command(iommu, &cmd);
636 }
637
638 iommu_completion_wait(iommu);
639 }
640
641 static void iommu_flush_all(struct amd_iommu *iommu)
642 {
643 struct iommu_cmd cmd;
644
645 build_inv_all(&cmd);
646
647 iommu_queue_command(iommu, &cmd);
648 iommu_completion_wait(iommu);
649 }
650
651 void iommu_flush_all_caches(struct amd_iommu *iommu)
652 {
653 if (iommu_feature(iommu, FEATURE_IA)) {
654 iommu_flush_all(iommu);
655 } else {
656 iommu_flush_dte_all(iommu);
657 iommu_flush_tlb_all(iommu);
658 }
659 }
660
661 /*
662 * Command send function for flushing on-device TLB
663 */
664 static int device_flush_iotlb(struct device *dev, u64 address, size_t size)
665 {
666 struct pci_dev *pdev = to_pci_dev(dev);
667 struct amd_iommu *iommu;
668 struct iommu_cmd cmd;
669 u16 devid;
670 int qdep;
671
672 qdep = pci_ats_queue_depth(pdev);
673 devid = get_device_id(dev);
674 iommu = amd_iommu_rlookup_table[devid];
675
676 build_inv_iotlb_pages(&cmd, devid, qdep, address, size);
677
678 return iommu_queue_command(iommu, &cmd);
679 }
680
681 /*
682 * Command send function for invalidating a device table entry
683 */
684 static int device_flush_dte(struct device *dev)
685 {
686 struct amd_iommu *iommu;
687 struct pci_dev *pdev;
688 u16 devid;
689 int ret;
690
691 pdev = to_pci_dev(dev);
692 devid = get_device_id(dev);
693 iommu = amd_iommu_rlookup_table[devid];
694
695 ret = iommu_flush_dte(iommu, devid);
696 if (ret)
697 return ret;
698
699 if (pci_ats_enabled(pdev))
700 ret = device_flush_iotlb(dev, 0, ~0UL);
701
702 return ret;
703 }
704
705 /*
706 * TLB invalidation function which is called from the mapping functions.
707 * It invalidates a single PTE if the range to flush is within a single
708 * page. Otherwise it flushes the whole TLB of the IOMMU.
709 */
710 static void __domain_flush_pages(struct protection_domain *domain,
711 u64 address, size_t size, int pde)
712 {
713 struct iommu_dev_data *dev_data;
714 struct iommu_cmd cmd;
715 int ret = 0, i;
716
717 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
718
719 for (i = 0; i < amd_iommus_present; ++i) {
720 if (!domain->dev_iommu[i])
721 continue;
722
723 /*
724 * Devices of this domain are behind this IOMMU
725 * We need a TLB flush
726 */
727 ret |= iommu_queue_command(amd_iommus[i], &cmd);
728 }
729
730 list_for_each_entry(dev_data, &domain->dev_list, list) {
731 struct pci_dev *pdev = to_pci_dev(dev_data->dev);
732
733 if (!pci_ats_enabled(pdev))
734 continue;
735
736 ret |= device_flush_iotlb(dev_data->dev, address, size);
737 }
738
739 WARN_ON(ret);
740 }
741
742 static void domain_flush_pages(struct protection_domain *domain,
743 u64 address, size_t size)
744 {
745 __domain_flush_pages(domain, address, size, 0);
746 }
747
748 /* Flush the whole IO/TLB for a given protection domain */
749 static void domain_flush_tlb(struct protection_domain *domain)
750 {
751 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
752 }
753
754 /* Flush the whole IO/TLB for a given protection domain - including PDE */
755 static void domain_flush_tlb_pde(struct protection_domain *domain)
756 {
757 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
758 }
759
760 static void domain_flush_complete(struct protection_domain *domain)
761 {
762 int i;
763
764 for (i = 0; i < amd_iommus_present; ++i) {
765 if (!domain->dev_iommu[i])
766 continue;
767
768 /*
769 * Devices of this domain are behind this IOMMU
770 * We need to wait for completion of all commands.
771 */
772 iommu_completion_wait(amd_iommus[i]);
773 }
774 }
775
776
777 /*
778 * This function flushes the DTEs for all devices in domain
779 */
780 static void domain_flush_devices(struct protection_domain *domain)
781 {
782 struct iommu_dev_data *dev_data;
783
784 list_for_each_entry(dev_data, &domain->dev_list, list)
785 device_flush_dte(dev_data->dev);
786 }
787
788 /****************************************************************************
789 *
790 * The functions below are used the create the page table mappings for
791 * unity mapped regions.
792 *
793 ****************************************************************************/
794
795 /*
796 * This function is used to add another level to an IO page table. Adding
797 * another level increases the size of the address space by 9 bits to a size up
798 * to 64 bits.
799 */
800 static bool increase_address_space(struct protection_domain *domain,
801 gfp_t gfp)
802 {
803 u64 *pte;
804
805 if (domain->mode == PAGE_MODE_6_LEVEL)
806 /* address space already 64 bit large */
807 return false;
808
809 pte = (void *)get_zeroed_page(gfp);
810 if (!pte)
811 return false;
812
813 *pte = PM_LEVEL_PDE(domain->mode,
814 virt_to_phys(domain->pt_root));
815 domain->pt_root = pte;
816 domain->mode += 1;
817 domain->updated = true;
818
819 return true;
820 }
821
822 static u64 *alloc_pte(struct protection_domain *domain,
823 unsigned long address,
824 unsigned long page_size,
825 u64 **pte_page,
826 gfp_t gfp)
827 {
828 int level, end_lvl;
829 u64 *pte, *page;
830
831 BUG_ON(!is_power_of_2(page_size));
832
833 while (address > PM_LEVEL_SIZE(domain->mode))
834 increase_address_space(domain, gfp);
835
836 level = domain->mode - 1;
837 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
838 address = PAGE_SIZE_ALIGN(address, page_size);
839 end_lvl = PAGE_SIZE_LEVEL(page_size);
840
841 while (level > end_lvl) {
842 if (!IOMMU_PTE_PRESENT(*pte)) {
843 page = (u64 *)get_zeroed_page(gfp);
844 if (!page)
845 return NULL;
846 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
847 }
848
849 /* No level skipping support yet */
850 if (PM_PTE_LEVEL(*pte) != level)
851 return NULL;
852
853 level -= 1;
854
855 pte = IOMMU_PTE_PAGE(*pte);
856
857 if (pte_page && level == end_lvl)
858 *pte_page = pte;
859
860 pte = &pte[PM_LEVEL_INDEX(level, address)];
861 }
862
863 return pte;
864 }
865
866 /*
867 * This function checks if there is a PTE for a given dma address. If
868 * there is one, it returns the pointer to it.
869 */
870 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
871 {
872 int level;
873 u64 *pte;
874
875 if (address > PM_LEVEL_SIZE(domain->mode))
876 return NULL;
877
878 level = domain->mode - 1;
879 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
880
881 while (level > 0) {
882
883 /* Not Present */
884 if (!IOMMU_PTE_PRESENT(*pte))
885 return NULL;
886
887 /* Large PTE */
888 if (PM_PTE_LEVEL(*pte) == 0x07) {
889 unsigned long pte_mask, __pte;
890
891 /*
892 * If we have a series of large PTEs, make
893 * sure to return a pointer to the first one.
894 */
895 pte_mask = PTE_PAGE_SIZE(*pte);
896 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
897 __pte = ((unsigned long)pte) & pte_mask;
898
899 return (u64 *)__pte;
900 }
901
902 /* No level skipping support yet */
903 if (PM_PTE_LEVEL(*pte) != level)
904 return NULL;
905
906 level -= 1;
907
908 /* Walk to the next level */
909 pte = IOMMU_PTE_PAGE(*pte);
910 pte = &pte[PM_LEVEL_INDEX(level, address)];
911 }
912
913 return pte;
914 }
915
916 /*
917 * Generic mapping functions. It maps a physical address into a DMA
918 * address space. It allocates the page table pages if necessary.
919 * In the future it can be extended to a generic mapping function
920 * supporting all features of AMD IOMMU page tables like level skipping
921 * and full 64 bit address spaces.
922 */
923 static int iommu_map_page(struct protection_domain *dom,
924 unsigned long bus_addr,
925 unsigned long phys_addr,
926 int prot,
927 unsigned long page_size)
928 {
929 u64 __pte, *pte;
930 int i, count;
931
932 if (!(prot & IOMMU_PROT_MASK))
933 return -EINVAL;
934
935 bus_addr = PAGE_ALIGN(bus_addr);
936 phys_addr = PAGE_ALIGN(phys_addr);
937 count = PAGE_SIZE_PTE_COUNT(page_size);
938 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
939
940 for (i = 0; i < count; ++i)
941 if (IOMMU_PTE_PRESENT(pte[i]))
942 return -EBUSY;
943
944 if (page_size > PAGE_SIZE) {
945 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
946 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
947 } else
948 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
949
950 if (prot & IOMMU_PROT_IR)
951 __pte |= IOMMU_PTE_IR;
952 if (prot & IOMMU_PROT_IW)
953 __pte |= IOMMU_PTE_IW;
954
955 for (i = 0; i < count; ++i)
956 pte[i] = __pte;
957
958 update_domain(dom);
959
960 return 0;
961 }
962
963 static unsigned long iommu_unmap_page(struct protection_domain *dom,
964 unsigned long bus_addr,
965 unsigned long page_size)
966 {
967 unsigned long long unmap_size, unmapped;
968 u64 *pte;
969
970 BUG_ON(!is_power_of_2(page_size));
971
972 unmapped = 0;
973
974 while (unmapped < page_size) {
975
976 pte = fetch_pte(dom, bus_addr);
977
978 if (!pte) {
979 /*
980 * No PTE for this address
981 * move forward in 4kb steps
982 */
983 unmap_size = PAGE_SIZE;
984 } else if (PM_PTE_LEVEL(*pte) == 0) {
985 /* 4kb PTE found for this address */
986 unmap_size = PAGE_SIZE;
987 *pte = 0ULL;
988 } else {
989 int count, i;
990
991 /* Large PTE found which maps this address */
992 unmap_size = PTE_PAGE_SIZE(*pte);
993 count = PAGE_SIZE_PTE_COUNT(unmap_size);
994 for (i = 0; i < count; i++)
995 pte[i] = 0ULL;
996 }
997
998 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
999 unmapped += unmap_size;
1000 }
1001
1002 BUG_ON(!is_power_of_2(unmapped));
1003
1004 return unmapped;
1005 }
1006
1007 /*
1008 * This function checks if a specific unity mapping entry is needed for
1009 * this specific IOMMU.
1010 */
1011 static int iommu_for_unity_map(struct amd_iommu *iommu,
1012 struct unity_map_entry *entry)
1013 {
1014 u16 bdf, i;
1015
1016 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1017 bdf = amd_iommu_alias_table[i];
1018 if (amd_iommu_rlookup_table[bdf] == iommu)
1019 return 1;
1020 }
1021
1022 return 0;
1023 }
1024
1025 /*
1026 * This function actually applies the mapping to the page table of the
1027 * dma_ops domain.
1028 */
1029 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1030 struct unity_map_entry *e)
1031 {
1032 u64 addr;
1033 int ret;
1034
1035 for (addr = e->address_start; addr < e->address_end;
1036 addr += PAGE_SIZE) {
1037 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1038 PAGE_SIZE);
1039 if (ret)
1040 return ret;
1041 /*
1042 * if unity mapping is in aperture range mark the page
1043 * as allocated in the aperture
1044 */
1045 if (addr < dma_dom->aperture_size)
1046 __set_bit(addr >> PAGE_SHIFT,
1047 dma_dom->aperture[0]->bitmap);
1048 }
1049
1050 return 0;
1051 }
1052
1053 /*
1054 * Init the unity mappings for a specific IOMMU in the system
1055 *
1056 * Basically iterates over all unity mapping entries and applies them to
1057 * the default domain DMA of that IOMMU if necessary.
1058 */
1059 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1060 {
1061 struct unity_map_entry *entry;
1062 int ret;
1063
1064 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1065 if (!iommu_for_unity_map(iommu, entry))
1066 continue;
1067 ret = dma_ops_unity_map(iommu->default_dom, entry);
1068 if (ret)
1069 return ret;
1070 }
1071
1072 return 0;
1073 }
1074
1075 /*
1076 * Inits the unity mappings required for a specific device
1077 */
1078 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1079 u16 devid)
1080 {
1081 struct unity_map_entry *e;
1082 int ret;
1083
1084 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1085 if (!(devid >= e->devid_start && devid <= e->devid_end))
1086 continue;
1087 ret = dma_ops_unity_map(dma_dom, e);
1088 if (ret)
1089 return ret;
1090 }
1091
1092 return 0;
1093 }
1094
1095 /****************************************************************************
1096 *
1097 * The next functions belong to the address allocator for the dma_ops
1098 * interface functions. They work like the allocators in the other IOMMU
1099 * drivers. Its basically a bitmap which marks the allocated pages in
1100 * the aperture. Maybe it could be enhanced in the future to a more
1101 * efficient allocator.
1102 *
1103 ****************************************************************************/
1104
1105 /*
1106 * The address allocator core functions.
1107 *
1108 * called with domain->lock held
1109 */
1110
1111 /*
1112 * Used to reserve address ranges in the aperture (e.g. for exclusion
1113 * ranges.
1114 */
1115 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1116 unsigned long start_page,
1117 unsigned int pages)
1118 {
1119 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1120
1121 if (start_page + pages > last_page)
1122 pages = last_page - start_page;
1123
1124 for (i = start_page; i < start_page + pages; ++i) {
1125 int index = i / APERTURE_RANGE_PAGES;
1126 int page = i % APERTURE_RANGE_PAGES;
1127 __set_bit(page, dom->aperture[index]->bitmap);
1128 }
1129 }
1130
1131 /*
1132 * This function is used to add a new aperture range to an existing
1133 * aperture in case of dma_ops domain allocation or address allocation
1134 * failure.
1135 */
1136 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1137 bool populate, gfp_t gfp)
1138 {
1139 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1140 struct amd_iommu *iommu;
1141 unsigned long i;
1142
1143 #ifdef CONFIG_IOMMU_STRESS
1144 populate = false;
1145 #endif
1146
1147 if (index >= APERTURE_MAX_RANGES)
1148 return -ENOMEM;
1149
1150 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1151 if (!dma_dom->aperture[index])
1152 return -ENOMEM;
1153
1154 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1155 if (!dma_dom->aperture[index]->bitmap)
1156 goto out_free;
1157
1158 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1159
1160 if (populate) {
1161 unsigned long address = dma_dom->aperture_size;
1162 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1163 u64 *pte, *pte_page;
1164
1165 for (i = 0; i < num_ptes; ++i) {
1166 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1167 &pte_page, gfp);
1168 if (!pte)
1169 goto out_free;
1170
1171 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1172
1173 address += APERTURE_RANGE_SIZE / 64;
1174 }
1175 }
1176
1177 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1178
1179 /* Initialize the exclusion range if necessary */
1180 for_each_iommu(iommu) {
1181 if (iommu->exclusion_start &&
1182 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1183 && iommu->exclusion_start < dma_dom->aperture_size) {
1184 unsigned long startpage;
1185 int pages = iommu_num_pages(iommu->exclusion_start,
1186 iommu->exclusion_length,
1187 PAGE_SIZE);
1188 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1189 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1190 }
1191 }
1192
1193 /*
1194 * Check for areas already mapped as present in the new aperture
1195 * range and mark those pages as reserved in the allocator. Such
1196 * mappings may already exist as a result of requested unity
1197 * mappings for devices.
1198 */
1199 for (i = dma_dom->aperture[index]->offset;
1200 i < dma_dom->aperture_size;
1201 i += PAGE_SIZE) {
1202 u64 *pte = fetch_pte(&dma_dom->domain, i);
1203 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1204 continue;
1205
1206 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT, 1);
1207 }
1208
1209 update_domain(&dma_dom->domain);
1210
1211 return 0;
1212
1213 out_free:
1214 update_domain(&dma_dom->domain);
1215
1216 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1217
1218 kfree(dma_dom->aperture[index]);
1219 dma_dom->aperture[index] = NULL;
1220
1221 return -ENOMEM;
1222 }
1223
1224 static unsigned long dma_ops_area_alloc(struct device *dev,
1225 struct dma_ops_domain *dom,
1226 unsigned int pages,
1227 unsigned long align_mask,
1228 u64 dma_mask,
1229 unsigned long start)
1230 {
1231 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1232 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1233 int i = start >> APERTURE_RANGE_SHIFT;
1234 unsigned long boundary_size;
1235 unsigned long address = -1;
1236 unsigned long limit;
1237
1238 next_bit >>= PAGE_SHIFT;
1239
1240 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1241 PAGE_SIZE) >> PAGE_SHIFT;
1242
1243 for (;i < max_index; ++i) {
1244 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1245
1246 if (dom->aperture[i]->offset >= dma_mask)
1247 break;
1248
1249 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1250 dma_mask >> PAGE_SHIFT);
1251
1252 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1253 limit, next_bit, pages, 0,
1254 boundary_size, align_mask);
1255 if (address != -1) {
1256 address = dom->aperture[i]->offset +
1257 (address << PAGE_SHIFT);
1258 dom->next_address = address + (pages << PAGE_SHIFT);
1259 break;
1260 }
1261
1262 next_bit = 0;
1263 }
1264
1265 return address;
1266 }
1267
1268 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1269 struct dma_ops_domain *dom,
1270 unsigned int pages,
1271 unsigned long align_mask,
1272 u64 dma_mask)
1273 {
1274 unsigned long address;
1275
1276 #ifdef CONFIG_IOMMU_STRESS
1277 dom->next_address = 0;
1278 dom->need_flush = true;
1279 #endif
1280
1281 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1282 dma_mask, dom->next_address);
1283
1284 if (address == -1) {
1285 dom->next_address = 0;
1286 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1287 dma_mask, 0);
1288 dom->need_flush = true;
1289 }
1290
1291 if (unlikely(address == -1))
1292 address = DMA_ERROR_CODE;
1293
1294 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1295
1296 return address;
1297 }
1298
1299 /*
1300 * The address free function.
1301 *
1302 * called with domain->lock held
1303 */
1304 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1305 unsigned long address,
1306 unsigned int pages)
1307 {
1308 unsigned i = address >> APERTURE_RANGE_SHIFT;
1309 struct aperture_range *range = dom->aperture[i];
1310
1311 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1312
1313 #ifdef CONFIG_IOMMU_STRESS
1314 if (i < 4)
1315 return;
1316 #endif
1317
1318 if (address >= dom->next_address)
1319 dom->need_flush = true;
1320
1321 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1322
1323 bitmap_clear(range->bitmap, address, pages);
1324
1325 }
1326
1327 /****************************************************************************
1328 *
1329 * The next functions belong to the domain allocation. A domain is
1330 * allocated for every IOMMU as the default domain. If device isolation
1331 * is enabled, every device get its own domain. The most important thing
1332 * about domains is the page table mapping the DMA address space they
1333 * contain.
1334 *
1335 ****************************************************************************/
1336
1337 /*
1338 * This function adds a protection domain to the global protection domain list
1339 */
1340 static void add_domain_to_list(struct protection_domain *domain)
1341 {
1342 unsigned long flags;
1343
1344 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1345 list_add(&domain->list, &amd_iommu_pd_list);
1346 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1347 }
1348
1349 /*
1350 * This function removes a protection domain to the global
1351 * protection domain list
1352 */
1353 static void del_domain_from_list(struct protection_domain *domain)
1354 {
1355 unsigned long flags;
1356
1357 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1358 list_del(&domain->list);
1359 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1360 }
1361
1362 static u16 domain_id_alloc(void)
1363 {
1364 unsigned long flags;
1365 int id;
1366
1367 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1368 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1369 BUG_ON(id == 0);
1370 if (id > 0 && id < MAX_DOMAIN_ID)
1371 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1372 else
1373 id = 0;
1374 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1375
1376 return id;
1377 }
1378
1379 static void domain_id_free(int id)
1380 {
1381 unsigned long flags;
1382
1383 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1384 if (id > 0 && id < MAX_DOMAIN_ID)
1385 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1386 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1387 }
1388
1389 static void free_pagetable(struct protection_domain *domain)
1390 {
1391 int i, j;
1392 u64 *p1, *p2, *p3;
1393
1394 p1 = domain->pt_root;
1395
1396 if (!p1)
1397 return;
1398
1399 for (i = 0; i < 512; ++i) {
1400 if (!IOMMU_PTE_PRESENT(p1[i]))
1401 continue;
1402
1403 p2 = IOMMU_PTE_PAGE(p1[i]);
1404 for (j = 0; j < 512; ++j) {
1405 if (!IOMMU_PTE_PRESENT(p2[j]))
1406 continue;
1407 p3 = IOMMU_PTE_PAGE(p2[j]);
1408 free_page((unsigned long)p3);
1409 }
1410
1411 free_page((unsigned long)p2);
1412 }
1413
1414 free_page((unsigned long)p1);
1415
1416 domain->pt_root = NULL;
1417 }
1418
1419 /*
1420 * Free a domain, only used if something went wrong in the
1421 * allocation path and we need to free an already allocated page table
1422 */
1423 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1424 {
1425 int i;
1426
1427 if (!dom)
1428 return;
1429
1430 del_domain_from_list(&dom->domain);
1431
1432 free_pagetable(&dom->domain);
1433
1434 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1435 if (!dom->aperture[i])
1436 continue;
1437 free_page((unsigned long)dom->aperture[i]->bitmap);
1438 kfree(dom->aperture[i]);
1439 }
1440
1441 kfree(dom);
1442 }
1443
1444 /*
1445 * Allocates a new protection domain usable for the dma_ops functions.
1446 * It also initializes the page table and the address allocator data
1447 * structures required for the dma_ops interface
1448 */
1449 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1450 {
1451 struct dma_ops_domain *dma_dom;
1452
1453 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1454 if (!dma_dom)
1455 return NULL;
1456
1457 spin_lock_init(&dma_dom->domain.lock);
1458
1459 dma_dom->domain.id = domain_id_alloc();
1460 if (dma_dom->domain.id == 0)
1461 goto free_dma_dom;
1462 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1463 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1464 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1465 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1466 dma_dom->domain.priv = dma_dom;
1467 if (!dma_dom->domain.pt_root)
1468 goto free_dma_dom;
1469
1470 dma_dom->need_flush = false;
1471 dma_dom->target_dev = 0xffff;
1472
1473 add_domain_to_list(&dma_dom->domain);
1474
1475 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1476 goto free_dma_dom;
1477
1478 /*
1479 * mark the first page as allocated so we never return 0 as
1480 * a valid dma-address. So we can use 0 as error value
1481 */
1482 dma_dom->aperture[0]->bitmap[0] = 1;
1483 dma_dom->next_address = 0;
1484
1485
1486 return dma_dom;
1487
1488 free_dma_dom:
1489 dma_ops_domain_free(dma_dom);
1490
1491 return NULL;
1492 }
1493
1494 /*
1495 * little helper function to check whether a given protection domain is a
1496 * dma_ops domain
1497 */
1498 static bool dma_ops_domain(struct protection_domain *domain)
1499 {
1500 return domain->flags & PD_DMA_OPS_MASK;
1501 }
1502
1503 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1504 {
1505 u64 pte_root = virt_to_phys(domain->pt_root);
1506 u32 flags = 0;
1507
1508 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1509 << DEV_ENTRY_MODE_SHIFT;
1510 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1511
1512 if (ats)
1513 flags |= DTE_FLAG_IOTLB;
1514
1515 amd_iommu_dev_table[devid].data[3] |= flags;
1516 amd_iommu_dev_table[devid].data[2] = domain->id;
1517 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1518 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1519 }
1520
1521 static void clear_dte_entry(u16 devid)
1522 {
1523 /* remove entry from the device table seen by the hardware */
1524 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1525 amd_iommu_dev_table[devid].data[1] = 0;
1526 amd_iommu_dev_table[devid].data[2] = 0;
1527
1528 amd_iommu_apply_erratum_63(devid);
1529 }
1530
1531 static void do_attach(struct device *dev, struct protection_domain *domain)
1532 {
1533 struct iommu_dev_data *dev_data;
1534 struct amd_iommu *iommu;
1535 struct pci_dev *pdev;
1536 bool ats = false;
1537 u16 devid;
1538
1539 devid = get_device_id(dev);
1540 iommu = amd_iommu_rlookup_table[devid];
1541 dev_data = get_dev_data(dev);
1542 pdev = to_pci_dev(dev);
1543
1544 if (amd_iommu_iotlb_sup)
1545 ats = pci_ats_enabled(pdev);
1546
1547 /* Update data structures */
1548 dev_data->domain = domain;
1549 list_add(&dev_data->list, &domain->dev_list);
1550 set_dte_entry(devid, domain, ats);
1551
1552 /* Do reference counting */
1553 domain->dev_iommu[iommu->index] += 1;
1554 domain->dev_cnt += 1;
1555
1556 /* Flush the DTE entry */
1557 device_flush_dte(dev);
1558 }
1559
1560 static void do_detach(struct device *dev)
1561 {
1562 struct iommu_dev_data *dev_data;
1563 struct amd_iommu *iommu;
1564 u16 devid;
1565
1566 devid = get_device_id(dev);
1567 iommu = amd_iommu_rlookup_table[devid];
1568 dev_data = get_dev_data(dev);
1569
1570 /* decrease reference counters */
1571 dev_data->domain->dev_iommu[iommu->index] -= 1;
1572 dev_data->domain->dev_cnt -= 1;
1573
1574 /* Update data structures */
1575 dev_data->domain = NULL;
1576 list_del(&dev_data->list);
1577 clear_dte_entry(devid);
1578
1579 /* Flush the DTE entry */
1580 device_flush_dte(dev);
1581 }
1582
1583 /*
1584 * If a device is not yet associated with a domain, this function does
1585 * assigns it visible for the hardware
1586 */
1587 static int __attach_device(struct device *dev,
1588 struct protection_domain *domain)
1589 {
1590 struct iommu_dev_data *dev_data, *alias_data;
1591 int ret;
1592
1593 dev_data = get_dev_data(dev);
1594 alias_data = get_dev_data(dev_data->alias);
1595
1596 if (!alias_data)
1597 return -EINVAL;
1598
1599 /* lock domain */
1600 spin_lock(&domain->lock);
1601
1602 /* Some sanity checks */
1603 ret = -EBUSY;
1604 if (alias_data->domain != NULL &&
1605 alias_data->domain != domain)
1606 goto out_unlock;
1607
1608 if (dev_data->domain != NULL &&
1609 dev_data->domain != domain)
1610 goto out_unlock;
1611
1612 /* Do real assignment */
1613 if (dev_data->alias != dev) {
1614 alias_data = get_dev_data(dev_data->alias);
1615 if (alias_data->domain == NULL)
1616 do_attach(dev_data->alias, domain);
1617
1618 atomic_inc(&alias_data->bind);
1619 }
1620
1621 if (dev_data->domain == NULL)
1622 do_attach(dev, domain);
1623
1624 atomic_inc(&dev_data->bind);
1625
1626 ret = 0;
1627
1628 out_unlock:
1629
1630 /* ready */
1631 spin_unlock(&domain->lock);
1632
1633 return ret;
1634 }
1635
1636 /*
1637 * If a device is not yet associated with a domain, this function does
1638 * assigns it visible for the hardware
1639 */
1640 static int attach_device(struct device *dev,
1641 struct protection_domain *domain)
1642 {
1643 struct pci_dev *pdev = to_pci_dev(dev);
1644 unsigned long flags;
1645 int ret;
1646
1647 if (amd_iommu_iotlb_sup)
1648 pci_enable_ats(pdev, PAGE_SHIFT);
1649
1650 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1651 ret = __attach_device(dev, domain);
1652 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1653
1654 /*
1655 * We might boot into a crash-kernel here. The crashed kernel
1656 * left the caches in the IOMMU dirty. So we have to flush
1657 * here to evict all dirty stuff.
1658 */
1659 domain_flush_tlb_pde(domain);
1660
1661 return ret;
1662 }
1663
1664 /*
1665 * Removes a device from a protection domain (unlocked)
1666 */
1667 static void __detach_device(struct device *dev)
1668 {
1669 struct iommu_dev_data *dev_data = get_dev_data(dev);
1670 struct iommu_dev_data *alias_data;
1671 struct protection_domain *domain;
1672 unsigned long flags;
1673
1674 BUG_ON(!dev_data->domain);
1675
1676 domain = dev_data->domain;
1677
1678 spin_lock_irqsave(&domain->lock, flags);
1679
1680 if (dev_data->alias != dev) {
1681 alias_data = get_dev_data(dev_data->alias);
1682 if (atomic_dec_and_test(&alias_data->bind))
1683 do_detach(dev_data->alias);
1684 }
1685
1686 if (atomic_dec_and_test(&dev_data->bind))
1687 do_detach(dev);
1688
1689 spin_unlock_irqrestore(&domain->lock, flags);
1690
1691 /*
1692 * If we run in passthrough mode the device must be assigned to the
1693 * passthrough domain if it is detached from any other domain.
1694 * Make sure we can deassign from the pt_domain itself.
1695 */
1696 if (iommu_pass_through &&
1697 (dev_data->domain == NULL && domain != pt_domain))
1698 __attach_device(dev, pt_domain);
1699 }
1700
1701 /*
1702 * Removes a device from a protection domain (with devtable_lock held)
1703 */
1704 static void detach_device(struct device *dev)
1705 {
1706 struct pci_dev *pdev = to_pci_dev(dev);
1707 unsigned long flags;
1708
1709 /* lock device table */
1710 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1711 __detach_device(dev);
1712 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1713
1714 if (amd_iommu_iotlb_sup && pci_ats_enabled(pdev))
1715 pci_disable_ats(pdev);
1716 }
1717
1718 /*
1719 * Find out the protection domain structure for a given PCI device. This
1720 * will give us the pointer to the page table root for example.
1721 */
1722 static struct protection_domain *domain_for_device(struct device *dev)
1723 {
1724 struct protection_domain *dom;
1725 struct iommu_dev_data *dev_data, *alias_data;
1726 unsigned long flags;
1727 u16 devid;
1728
1729 devid = get_device_id(dev);
1730 dev_data = get_dev_data(dev);
1731 alias_data = get_dev_data(dev_data->alias);
1732 if (!alias_data)
1733 return NULL;
1734
1735 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1736 dom = dev_data->domain;
1737 if (dom == NULL &&
1738 alias_data->domain != NULL) {
1739 __attach_device(dev, alias_data->domain);
1740 dom = alias_data->domain;
1741 }
1742
1743 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1744
1745 return dom;
1746 }
1747
1748 static int device_change_notifier(struct notifier_block *nb,
1749 unsigned long action, void *data)
1750 {
1751 struct device *dev = data;
1752 u16 devid;
1753 struct protection_domain *domain;
1754 struct dma_ops_domain *dma_domain;
1755 struct amd_iommu *iommu;
1756 unsigned long flags;
1757
1758 if (!check_device(dev))
1759 return 0;
1760
1761 devid = get_device_id(dev);
1762 iommu = amd_iommu_rlookup_table[devid];
1763
1764 switch (action) {
1765 case BUS_NOTIFY_UNBOUND_DRIVER:
1766
1767 domain = domain_for_device(dev);
1768
1769 if (!domain)
1770 goto out;
1771 if (iommu_pass_through)
1772 break;
1773 detach_device(dev);
1774 break;
1775 case BUS_NOTIFY_ADD_DEVICE:
1776
1777 iommu_init_device(dev);
1778
1779 domain = domain_for_device(dev);
1780
1781 /* allocate a protection domain if a device is added */
1782 dma_domain = find_protection_domain(devid);
1783 if (dma_domain)
1784 goto out;
1785 dma_domain = dma_ops_domain_alloc();
1786 if (!dma_domain)
1787 goto out;
1788 dma_domain->target_dev = devid;
1789
1790 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1791 list_add_tail(&dma_domain->list, &iommu_pd_list);
1792 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1793
1794 break;
1795 case BUS_NOTIFY_DEL_DEVICE:
1796
1797 iommu_uninit_device(dev);
1798
1799 default:
1800 goto out;
1801 }
1802
1803 device_flush_dte(dev);
1804 iommu_completion_wait(iommu);
1805
1806 out:
1807 return 0;
1808 }
1809
1810 static struct notifier_block device_nb = {
1811 .notifier_call = device_change_notifier,
1812 };
1813
1814 void amd_iommu_init_notifier(void)
1815 {
1816 bus_register_notifier(&pci_bus_type, &device_nb);
1817 }
1818
1819 /*****************************************************************************
1820 *
1821 * The next functions belong to the dma_ops mapping/unmapping code.
1822 *
1823 *****************************************************************************/
1824
1825 /*
1826 * In the dma_ops path we only have the struct device. This function
1827 * finds the corresponding IOMMU, the protection domain and the
1828 * requestor id for a given device.
1829 * If the device is not yet associated with a domain this is also done
1830 * in this function.
1831 */
1832 static struct protection_domain *get_domain(struct device *dev)
1833 {
1834 struct protection_domain *domain;
1835 struct dma_ops_domain *dma_dom;
1836 u16 devid = get_device_id(dev);
1837
1838 if (!check_device(dev))
1839 return ERR_PTR(-EINVAL);
1840
1841 domain = domain_for_device(dev);
1842 if (domain != NULL && !dma_ops_domain(domain))
1843 return ERR_PTR(-EBUSY);
1844
1845 if (domain != NULL)
1846 return domain;
1847
1848 /* Device not bount yet - bind it */
1849 dma_dom = find_protection_domain(devid);
1850 if (!dma_dom)
1851 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1852 attach_device(dev, &dma_dom->domain);
1853 DUMP_printk("Using protection domain %d for device %s\n",
1854 dma_dom->domain.id, dev_name(dev));
1855
1856 return &dma_dom->domain;
1857 }
1858
1859 static void update_device_table(struct protection_domain *domain)
1860 {
1861 struct iommu_dev_data *dev_data;
1862
1863 list_for_each_entry(dev_data, &domain->dev_list, list) {
1864 struct pci_dev *pdev = to_pci_dev(dev_data->dev);
1865 u16 devid = get_device_id(dev_data->dev);
1866 set_dte_entry(devid, domain, pci_ats_enabled(pdev));
1867 }
1868 }
1869
1870 static void update_domain(struct protection_domain *domain)
1871 {
1872 if (!domain->updated)
1873 return;
1874
1875 update_device_table(domain);
1876
1877 domain_flush_devices(domain);
1878 domain_flush_tlb_pde(domain);
1879
1880 domain->updated = false;
1881 }
1882
1883 /*
1884 * This function fetches the PTE for a given address in the aperture
1885 */
1886 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1887 unsigned long address)
1888 {
1889 struct aperture_range *aperture;
1890 u64 *pte, *pte_page;
1891
1892 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1893 if (!aperture)
1894 return NULL;
1895
1896 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1897 if (!pte) {
1898 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1899 GFP_ATOMIC);
1900 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1901 } else
1902 pte += PM_LEVEL_INDEX(0, address);
1903
1904 update_domain(&dom->domain);
1905
1906 return pte;
1907 }
1908
1909 /*
1910 * This is the generic map function. It maps one 4kb page at paddr to
1911 * the given address in the DMA address space for the domain.
1912 */
1913 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1914 unsigned long address,
1915 phys_addr_t paddr,
1916 int direction)
1917 {
1918 u64 *pte, __pte;
1919
1920 WARN_ON(address > dom->aperture_size);
1921
1922 paddr &= PAGE_MASK;
1923
1924 pte = dma_ops_get_pte(dom, address);
1925 if (!pte)
1926 return DMA_ERROR_CODE;
1927
1928 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1929
1930 if (direction == DMA_TO_DEVICE)
1931 __pte |= IOMMU_PTE_IR;
1932 else if (direction == DMA_FROM_DEVICE)
1933 __pte |= IOMMU_PTE_IW;
1934 else if (direction == DMA_BIDIRECTIONAL)
1935 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1936
1937 WARN_ON(*pte);
1938
1939 *pte = __pte;
1940
1941 return (dma_addr_t)address;
1942 }
1943
1944 /*
1945 * The generic unmapping function for on page in the DMA address space.
1946 */
1947 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1948 unsigned long address)
1949 {
1950 struct aperture_range *aperture;
1951 u64 *pte;
1952
1953 if (address >= dom->aperture_size)
1954 return;
1955
1956 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1957 if (!aperture)
1958 return;
1959
1960 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1961 if (!pte)
1962 return;
1963
1964 pte += PM_LEVEL_INDEX(0, address);
1965
1966 WARN_ON(!*pte);
1967
1968 *pte = 0ULL;
1969 }
1970
1971 /*
1972 * This function contains common code for mapping of a physically
1973 * contiguous memory region into DMA address space. It is used by all
1974 * mapping functions provided with this IOMMU driver.
1975 * Must be called with the domain lock held.
1976 */
1977 static dma_addr_t __map_single(struct device *dev,
1978 struct dma_ops_domain *dma_dom,
1979 phys_addr_t paddr,
1980 size_t size,
1981 int dir,
1982 bool align,
1983 u64 dma_mask)
1984 {
1985 dma_addr_t offset = paddr & ~PAGE_MASK;
1986 dma_addr_t address, start, ret;
1987 unsigned int pages;
1988 unsigned long align_mask = 0;
1989 int i;
1990
1991 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1992 paddr &= PAGE_MASK;
1993
1994 INC_STATS_COUNTER(total_map_requests);
1995
1996 if (pages > 1)
1997 INC_STATS_COUNTER(cross_page);
1998
1999 if (align)
2000 align_mask = (1UL << get_order(size)) - 1;
2001
2002 retry:
2003 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2004 dma_mask);
2005 if (unlikely(address == DMA_ERROR_CODE)) {
2006 /*
2007 * setting next_address here will let the address
2008 * allocator only scan the new allocated range in the
2009 * first run. This is a small optimization.
2010 */
2011 dma_dom->next_address = dma_dom->aperture_size;
2012
2013 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2014 goto out;
2015
2016 /*
2017 * aperture was successfully enlarged by 128 MB, try
2018 * allocation again
2019 */
2020 goto retry;
2021 }
2022
2023 start = address;
2024 for (i = 0; i < pages; ++i) {
2025 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2026 if (ret == DMA_ERROR_CODE)
2027 goto out_unmap;
2028
2029 paddr += PAGE_SIZE;
2030 start += PAGE_SIZE;
2031 }
2032 address += offset;
2033
2034 ADD_STATS_COUNTER(alloced_io_mem, size);
2035
2036 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2037 domain_flush_tlb(&dma_dom->domain);
2038 dma_dom->need_flush = false;
2039 } else if (unlikely(amd_iommu_np_cache))
2040 domain_flush_pages(&dma_dom->domain, address, size);
2041
2042 out:
2043 return address;
2044
2045 out_unmap:
2046
2047 for (--i; i >= 0; --i) {
2048 start -= PAGE_SIZE;
2049 dma_ops_domain_unmap(dma_dom, start);
2050 }
2051
2052 dma_ops_free_addresses(dma_dom, address, pages);
2053
2054 return DMA_ERROR_CODE;
2055 }
2056
2057 /*
2058 * Does the reverse of the __map_single function. Must be called with
2059 * the domain lock held too
2060 */
2061 static void __unmap_single(struct dma_ops_domain *dma_dom,
2062 dma_addr_t dma_addr,
2063 size_t size,
2064 int dir)
2065 {
2066 dma_addr_t flush_addr;
2067 dma_addr_t i, start;
2068 unsigned int pages;
2069
2070 if ((dma_addr == DMA_ERROR_CODE) ||
2071 (dma_addr + size > dma_dom->aperture_size))
2072 return;
2073
2074 flush_addr = dma_addr;
2075 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2076 dma_addr &= PAGE_MASK;
2077 start = dma_addr;
2078
2079 for (i = 0; i < pages; ++i) {
2080 dma_ops_domain_unmap(dma_dom, start);
2081 start += PAGE_SIZE;
2082 }
2083
2084 SUB_STATS_COUNTER(alloced_io_mem, size);
2085
2086 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2087
2088 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2089 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2090 dma_dom->need_flush = false;
2091 }
2092 }
2093
2094 /*
2095 * The exported map_single function for dma_ops.
2096 */
2097 static dma_addr_t map_page(struct device *dev, struct page *page,
2098 unsigned long offset, size_t size,
2099 enum dma_data_direction dir,
2100 struct dma_attrs *attrs)
2101 {
2102 unsigned long flags;
2103 struct protection_domain *domain;
2104 dma_addr_t addr;
2105 u64 dma_mask;
2106 phys_addr_t paddr = page_to_phys(page) + offset;
2107
2108 INC_STATS_COUNTER(cnt_map_single);
2109
2110 domain = get_domain(dev);
2111 if (PTR_ERR(domain) == -EINVAL)
2112 return (dma_addr_t)paddr;
2113 else if (IS_ERR(domain))
2114 return DMA_ERROR_CODE;
2115
2116 dma_mask = *dev->dma_mask;
2117
2118 spin_lock_irqsave(&domain->lock, flags);
2119
2120 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2121 dma_mask);
2122 if (addr == DMA_ERROR_CODE)
2123 goto out;
2124
2125 domain_flush_complete(domain);
2126
2127 out:
2128 spin_unlock_irqrestore(&domain->lock, flags);
2129
2130 return addr;
2131 }
2132
2133 /*
2134 * The exported unmap_single function for dma_ops.
2135 */
2136 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2137 enum dma_data_direction dir, struct dma_attrs *attrs)
2138 {
2139 unsigned long flags;
2140 struct protection_domain *domain;
2141
2142 INC_STATS_COUNTER(cnt_unmap_single);
2143
2144 domain = get_domain(dev);
2145 if (IS_ERR(domain))
2146 return;
2147
2148 spin_lock_irqsave(&domain->lock, flags);
2149
2150 __unmap_single(domain->priv, dma_addr, size, dir);
2151
2152 domain_flush_complete(domain);
2153
2154 spin_unlock_irqrestore(&domain->lock, flags);
2155 }
2156
2157 /*
2158 * This is a special map_sg function which is used if we should map a
2159 * device which is not handled by an AMD IOMMU in the system.
2160 */
2161 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2162 int nelems, int dir)
2163 {
2164 struct scatterlist *s;
2165 int i;
2166
2167 for_each_sg(sglist, s, nelems, i) {
2168 s->dma_address = (dma_addr_t)sg_phys(s);
2169 s->dma_length = s->length;
2170 }
2171
2172 return nelems;
2173 }
2174
2175 /*
2176 * The exported map_sg function for dma_ops (handles scatter-gather
2177 * lists).
2178 */
2179 static int map_sg(struct device *dev, struct scatterlist *sglist,
2180 int nelems, enum dma_data_direction dir,
2181 struct dma_attrs *attrs)
2182 {
2183 unsigned long flags;
2184 struct protection_domain *domain;
2185 int i;
2186 struct scatterlist *s;
2187 phys_addr_t paddr;
2188 int mapped_elems = 0;
2189 u64 dma_mask;
2190
2191 INC_STATS_COUNTER(cnt_map_sg);
2192
2193 domain = get_domain(dev);
2194 if (PTR_ERR(domain) == -EINVAL)
2195 return map_sg_no_iommu(dev, sglist, nelems, dir);
2196 else if (IS_ERR(domain))
2197 return 0;
2198
2199 dma_mask = *dev->dma_mask;
2200
2201 spin_lock_irqsave(&domain->lock, flags);
2202
2203 for_each_sg(sglist, s, nelems, i) {
2204 paddr = sg_phys(s);
2205
2206 s->dma_address = __map_single(dev, domain->priv,
2207 paddr, s->length, dir, false,
2208 dma_mask);
2209
2210 if (s->dma_address) {
2211 s->dma_length = s->length;
2212 mapped_elems++;
2213 } else
2214 goto unmap;
2215 }
2216
2217 domain_flush_complete(domain);
2218
2219 out:
2220 spin_unlock_irqrestore(&domain->lock, flags);
2221
2222 return mapped_elems;
2223 unmap:
2224 for_each_sg(sglist, s, mapped_elems, i) {
2225 if (s->dma_address)
2226 __unmap_single(domain->priv, s->dma_address,
2227 s->dma_length, dir);
2228 s->dma_address = s->dma_length = 0;
2229 }
2230
2231 mapped_elems = 0;
2232
2233 goto out;
2234 }
2235
2236 /*
2237 * The exported map_sg function for dma_ops (handles scatter-gather
2238 * lists).
2239 */
2240 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2241 int nelems, enum dma_data_direction dir,
2242 struct dma_attrs *attrs)
2243 {
2244 unsigned long flags;
2245 struct protection_domain *domain;
2246 struct scatterlist *s;
2247 int i;
2248
2249 INC_STATS_COUNTER(cnt_unmap_sg);
2250
2251 domain = get_domain(dev);
2252 if (IS_ERR(domain))
2253 return;
2254
2255 spin_lock_irqsave(&domain->lock, flags);
2256
2257 for_each_sg(sglist, s, nelems, i) {
2258 __unmap_single(domain->priv, s->dma_address,
2259 s->dma_length, dir);
2260 s->dma_address = s->dma_length = 0;
2261 }
2262
2263 domain_flush_complete(domain);
2264
2265 spin_unlock_irqrestore(&domain->lock, flags);
2266 }
2267
2268 /*
2269 * The exported alloc_coherent function for dma_ops.
2270 */
2271 static void *alloc_coherent(struct device *dev, size_t size,
2272 dma_addr_t *dma_addr, gfp_t flag)
2273 {
2274 unsigned long flags;
2275 void *virt_addr;
2276 struct protection_domain *domain;
2277 phys_addr_t paddr;
2278 u64 dma_mask = dev->coherent_dma_mask;
2279
2280 INC_STATS_COUNTER(cnt_alloc_coherent);
2281
2282 domain = get_domain(dev);
2283 if (PTR_ERR(domain) == -EINVAL) {
2284 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2285 *dma_addr = __pa(virt_addr);
2286 return virt_addr;
2287 } else if (IS_ERR(domain))
2288 return NULL;
2289
2290 dma_mask = dev->coherent_dma_mask;
2291 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2292 flag |= __GFP_ZERO;
2293
2294 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2295 if (!virt_addr)
2296 return NULL;
2297
2298 paddr = virt_to_phys(virt_addr);
2299
2300 if (!dma_mask)
2301 dma_mask = *dev->dma_mask;
2302
2303 spin_lock_irqsave(&domain->lock, flags);
2304
2305 *dma_addr = __map_single(dev, domain->priv, paddr,
2306 size, DMA_BIDIRECTIONAL, true, dma_mask);
2307
2308 if (*dma_addr == DMA_ERROR_CODE) {
2309 spin_unlock_irqrestore(&domain->lock, flags);
2310 goto out_free;
2311 }
2312
2313 domain_flush_complete(domain);
2314
2315 spin_unlock_irqrestore(&domain->lock, flags);
2316
2317 return virt_addr;
2318
2319 out_free:
2320
2321 free_pages((unsigned long)virt_addr, get_order(size));
2322
2323 return NULL;
2324 }
2325
2326 /*
2327 * The exported free_coherent function for dma_ops.
2328 */
2329 static void free_coherent(struct device *dev, size_t size,
2330 void *virt_addr, dma_addr_t dma_addr)
2331 {
2332 unsigned long flags;
2333 struct protection_domain *domain;
2334
2335 INC_STATS_COUNTER(cnt_free_coherent);
2336
2337 domain = get_domain(dev);
2338 if (IS_ERR(domain))
2339 goto free_mem;
2340
2341 spin_lock_irqsave(&domain->lock, flags);
2342
2343 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2344
2345 domain_flush_complete(domain);
2346
2347 spin_unlock_irqrestore(&domain->lock, flags);
2348
2349 free_mem:
2350 free_pages((unsigned long)virt_addr, get_order(size));
2351 }
2352
2353 /*
2354 * This function is called by the DMA layer to find out if we can handle a
2355 * particular device. It is part of the dma_ops.
2356 */
2357 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2358 {
2359 return check_device(dev);
2360 }
2361
2362 /*
2363 * The function for pre-allocating protection domains.
2364 *
2365 * If the driver core informs the DMA layer if a driver grabs a device
2366 * we don't need to preallocate the protection domains anymore.
2367 * For now we have to.
2368 */
2369 static void prealloc_protection_domains(void)
2370 {
2371 struct pci_dev *dev = NULL;
2372 struct dma_ops_domain *dma_dom;
2373 u16 devid;
2374
2375 for_each_pci_dev(dev) {
2376
2377 /* Do we handle this device? */
2378 if (!check_device(&dev->dev))
2379 continue;
2380
2381 /* Is there already any domain for it? */
2382 if (domain_for_device(&dev->dev))
2383 continue;
2384
2385 devid = get_device_id(&dev->dev);
2386
2387 dma_dom = dma_ops_domain_alloc();
2388 if (!dma_dom)
2389 continue;
2390 init_unity_mappings_for_device(dma_dom, devid);
2391 dma_dom->target_dev = devid;
2392
2393 attach_device(&dev->dev, &dma_dom->domain);
2394
2395 list_add_tail(&dma_dom->list, &iommu_pd_list);
2396 }
2397 }
2398
2399 static struct dma_map_ops amd_iommu_dma_ops = {
2400 .alloc_coherent = alloc_coherent,
2401 .free_coherent = free_coherent,
2402 .map_page = map_page,
2403 .unmap_page = unmap_page,
2404 .map_sg = map_sg,
2405 .unmap_sg = unmap_sg,
2406 .dma_supported = amd_iommu_dma_supported,
2407 };
2408
2409 static unsigned device_dma_ops_init(void)
2410 {
2411 struct pci_dev *pdev = NULL;
2412 unsigned unhandled = 0;
2413
2414 for_each_pci_dev(pdev) {
2415 if (!check_device(&pdev->dev)) {
2416 unhandled += 1;
2417 continue;
2418 }
2419
2420 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
2421 }
2422
2423 return unhandled;
2424 }
2425
2426 /*
2427 * The function which clues the AMD IOMMU driver into dma_ops.
2428 */
2429
2430 void __init amd_iommu_init_api(void)
2431 {
2432 register_iommu(&amd_iommu_ops);
2433 }
2434
2435 int __init amd_iommu_init_dma_ops(void)
2436 {
2437 struct amd_iommu *iommu;
2438 int ret, unhandled;
2439
2440 /*
2441 * first allocate a default protection domain for every IOMMU we
2442 * found in the system. Devices not assigned to any other
2443 * protection domain will be assigned to the default one.
2444 */
2445 for_each_iommu(iommu) {
2446 iommu->default_dom = dma_ops_domain_alloc();
2447 if (iommu->default_dom == NULL)
2448 return -ENOMEM;
2449 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2450 ret = iommu_init_unity_mappings(iommu);
2451 if (ret)
2452 goto free_domains;
2453 }
2454
2455 /*
2456 * Pre-allocate the protection domains for each device.
2457 */
2458 prealloc_protection_domains();
2459
2460 iommu_detected = 1;
2461 swiotlb = 0;
2462
2463 /* Make the driver finally visible to the drivers */
2464 unhandled = device_dma_ops_init();
2465 if (unhandled && max_pfn > MAX_DMA32_PFN) {
2466 /* There are unhandled devices - initialize swiotlb for them */
2467 swiotlb = 1;
2468 }
2469
2470 amd_iommu_stats_init();
2471
2472 return 0;
2473
2474 free_domains:
2475
2476 for_each_iommu(iommu) {
2477 if (iommu->default_dom)
2478 dma_ops_domain_free(iommu->default_dom);
2479 }
2480
2481 return ret;
2482 }
2483
2484 /*****************************************************************************
2485 *
2486 * The following functions belong to the exported interface of AMD IOMMU
2487 *
2488 * This interface allows access to lower level functions of the IOMMU
2489 * like protection domain handling and assignement of devices to domains
2490 * which is not possible with the dma_ops interface.
2491 *
2492 *****************************************************************************/
2493
2494 static void cleanup_domain(struct protection_domain *domain)
2495 {
2496 struct iommu_dev_data *dev_data, *next;
2497 unsigned long flags;
2498
2499 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2500
2501 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2502 struct device *dev = dev_data->dev;
2503
2504 __detach_device(dev);
2505 atomic_set(&dev_data->bind, 0);
2506 }
2507
2508 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2509 }
2510
2511 static void protection_domain_free(struct protection_domain *domain)
2512 {
2513 if (!domain)
2514 return;
2515
2516 del_domain_from_list(domain);
2517
2518 if (domain->id)
2519 domain_id_free(domain->id);
2520
2521 kfree(domain);
2522 }
2523
2524 static struct protection_domain *protection_domain_alloc(void)
2525 {
2526 struct protection_domain *domain;
2527
2528 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2529 if (!domain)
2530 return NULL;
2531
2532 spin_lock_init(&domain->lock);
2533 mutex_init(&domain->api_lock);
2534 domain->id = domain_id_alloc();
2535 if (!domain->id)
2536 goto out_err;
2537 INIT_LIST_HEAD(&domain->dev_list);
2538
2539 add_domain_to_list(domain);
2540
2541 return domain;
2542
2543 out_err:
2544 kfree(domain);
2545
2546 return NULL;
2547 }
2548
2549 static int amd_iommu_domain_init(struct iommu_domain *dom)
2550 {
2551 struct protection_domain *domain;
2552
2553 domain = protection_domain_alloc();
2554 if (!domain)
2555 goto out_free;
2556
2557 domain->mode = PAGE_MODE_3_LEVEL;
2558 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2559 if (!domain->pt_root)
2560 goto out_free;
2561
2562 dom->priv = domain;
2563
2564 return 0;
2565
2566 out_free:
2567 protection_domain_free(domain);
2568
2569 return -ENOMEM;
2570 }
2571
2572 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2573 {
2574 struct protection_domain *domain = dom->priv;
2575
2576 if (!domain)
2577 return;
2578
2579 if (domain->dev_cnt > 0)
2580 cleanup_domain(domain);
2581
2582 BUG_ON(domain->dev_cnt != 0);
2583
2584 free_pagetable(domain);
2585
2586 protection_domain_free(domain);
2587
2588 dom->priv = NULL;
2589 }
2590
2591 static void amd_iommu_detach_device(struct iommu_domain *dom,
2592 struct device *dev)
2593 {
2594 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2595 struct amd_iommu *iommu;
2596 u16 devid;
2597
2598 if (!check_device(dev))
2599 return;
2600
2601 devid = get_device_id(dev);
2602
2603 if (dev_data->domain != NULL)
2604 detach_device(dev);
2605
2606 iommu = amd_iommu_rlookup_table[devid];
2607 if (!iommu)
2608 return;
2609
2610 device_flush_dte(dev);
2611 iommu_completion_wait(iommu);
2612 }
2613
2614 static int amd_iommu_attach_device(struct iommu_domain *dom,
2615 struct device *dev)
2616 {
2617 struct protection_domain *domain = dom->priv;
2618 struct iommu_dev_data *dev_data;
2619 struct amd_iommu *iommu;
2620 int ret;
2621 u16 devid;
2622
2623 if (!check_device(dev))
2624 return -EINVAL;
2625
2626 dev_data = dev->archdata.iommu;
2627
2628 devid = get_device_id(dev);
2629
2630 iommu = amd_iommu_rlookup_table[devid];
2631 if (!iommu)
2632 return -EINVAL;
2633
2634 if (dev_data->domain)
2635 detach_device(dev);
2636
2637 ret = attach_device(dev, domain);
2638
2639 iommu_completion_wait(iommu);
2640
2641 return ret;
2642 }
2643
2644 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2645 phys_addr_t paddr, int gfp_order, int iommu_prot)
2646 {
2647 unsigned long page_size = 0x1000UL << gfp_order;
2648 struct protection_domain *domain = dom->priv;
2649 int prot = 0;
2650 int ret;
2651
2652 if (iommu_prot & IOMMU_READ)
2653 prot |= IOMMU_PROT_IR;
2654 if (iommu_prot & IOMMU_WRITE)
2655 prot |= IOMMU_PROT_IW;
2656
2657 mutex_lock(&domain->api_lock);
2658 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2659 mutex_unlock(&domain->api_lock);
2660
2661 return ret;
2662 }
2663
2664 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2665 int gfp_order)
2666 {
2667 struct protection_domain *domain = dom->priv;
2668 unsigned long page_size, unmap_size;
2669
2670 page_size = 0x1000UL << gfp_order;
2671
2672 mutex_lock(&domain->api_lock);
2673 unmap_size = iommu_unmap_page(domain, iova, page_size);
2674 mutex_unlock(&domain->api_lock);
2675
2676 domain_flush_tlb_pde(domain);
2677
2678 return get_order(unmap_size);
2679 }
2680
2681 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2682 unsigned long iova)
2683 {
2684 struct protection_domain *domain = dom->priv;
2685 unsigned long offset_mask;
2686 phys_addr_t paddr;
2687 u64 *pte, __pte;
2688
2689 pte = fetch_pte(domain, iova);
2690
2691 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2692 return 0;
2693
2694 if (PM_PTE_LEVEL(*pte) == 0)
2695 offset_mask = PAGE_SIZE - 1;
2696 else
2697 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2698
2699 __pte = *pte & PM_ADDR_MASK;
2700 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2701
2702 return paddr;
2703 }
2704
2705 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2706 unsigned long cap)
2707 {
2708 switch (cap) {
2709 case IOMMU_CAP_CACHE_COHERENCY:
2710 return 1;
2711 }
2712
2713 return 0;
2714 }
2715
2716 static struct iommu_ops amd_iommu_ops = {
2717 .domain_init = amd_iommu_domain_init,
2718 .domain_destroy = amd_iommu_domain_destroy,
2719 .attach_dev = amd_iommu_attach_device,
2720 .detach_dev = amd_iommu_detach_device,
2721 .map = amd_iommu_map,
2722 .unmap = amd_iommu_unmap,
2723 .iova_to_phys = amd_iommu_iova_to_phys,
2724 .domain_has_cap = amd_iommu_domain_has_cap,
2725 };
2726
2727 /*****************************************************************************
2728 *
2729 * The next functions do a basic initialization of IOMMU for pass through
2730 * mode
2731 *
2732 * In passthrough mode the IOMMU is initialized and enabled but not used for
2733 * DMA-API translation.
2734 *
2735 *****************************************************************************/
2736
2737 int __init amd_iommu_init_passthrough(void)
2738 {
2739 struct amd_iommu *iommu;
2740 struct pci_dev *dev = NULL;
2741 u16 devid;
2742
2743 /* allocate passthrough domain */
2744 pt_domain = protection_domain_alloc();
2745 if (!pt_domain)
2746 return -ENOMEM;
2747
2748 pt_domain->mode |= PAGE_MODE_NONE;
2749
2750 for_each_pci_dev(dev) {
2751 if (!check_device(&dev->dev))
2752 continue;
2753
2754 devid = get_device_id(&dev->dev);
2755
2756 iommu = amd_iommu_rlookup_table[devid];
2757 if (!iommu)
2758 continue;
2759
2760 attach_device(&dev->dev, pt_domain);
2761 }
2762
2763 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2764
2765 return 0;
2766 }
Linux with added FPC-III support