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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / arch / x86 / kernel / amd_iommu_init.c
blob33df6e82f653d74db2496d783c9fd78b067c9380
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/slab.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_proto.h>
29 #include <asm/amd_iommu_types.h>
30 #include <asm/amd_iommu.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/x86_init.h>
34 #include <asm/iommu_table.h>
35 /*
36 * definitions for the ACPI scanning code
37 */
38 #define IVRS_HEADER_LENGTH 48
39
40 #define ACPI_IVHD_TYPE 0x10
41 #define ACPI_IVMD_TYPE_ALL 0x20
42 #define ACPI_IVMD_TYPE 0x21
43 #define ACPI_IVMD_TYPE_RANGE 0x22
44
45 #define IVHD_DEV_ALL 0x01
46 #define IVHD_DEV_SELECT 0x02
47 #define IVHD_DEV_SELECT_RANGE_START 0x03
48 #define IVHD_DEV_RANGE_END 0x04
49 #define IVHD_DEV_ALIAS 0x42
50 #define IVHD_DEV_ALIAS_RANGE 0x43
51 #define IVHD_DEV_EXT_SELECT 0x46
52 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
53
54 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
55 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
56 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
57 #define IVHD_FLAG_ISOC_EN_MASK 0x08
58
59 #define IVMD_FLAG_EXCL_RANGE 0x08
60 #define IVMD_FLAG_UNITY_MAP 0x01
61
62 #define ACPI_DEVFLAG_INITPASS 0x01
63 #define ACPI_DEVFLAG_EXTINT 0x02
64 #define ACPI_DEVFLAG_NMI 0x04
65 #define ACPI_DEVFLAG_SYSMGT1 0x10
66 #define ACPI_DEVFLAG_SYSMGT2 0x20
67 #define ACPI_DEVFLAG_LINT0 0x40
68 #define ACPI_DEVFLAG_LINT1 0x80
69 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70
71 /*
72 * ACPI table definitions
73 *
74 * These data structures are laid over the table to parse the important values
75 * out of it.
76 */
77
78 /*
79 * structure describing one IOMMU in the ACPI table. Typically followed by one
80 * or more ivhd_entrys.
81 */
82 struct ivhd_header {
83 u8 type;
84 u8 flags;
85 u16 length;
86 u16 devid;
87 u16 cap_ptr;
88 u64 mmio_phys;
89 u16 pci_seg;
90 u16 info;
91 u32 reserved;
92 } __attribute__((packed));
93
94 /*
95 * A device entry describing which devices a specific IOMMU translates and
96 * which requestor ids they use.
97 */
98 struct ivhd_entry {
99 u8 type;
100 u16 devid;
101 u8 flags;
102 u32 ext;
103 } __attribute__((packed));
104
105 /*
106 * An AMD IOMMU memory definition structure. It defines things like exclusion
107 * ranges for devices and regions that should be unity mapped.
108 */
109 struct ivmd_header {
110 u8 type;
111 u8 flags;
112 u16 length;
113 u16 devid;
114 u16 aux;
115 u64 resv;
116 u64 range_start;
117 u64 range_length;
118 } __attribute__((packed));
119
120 bool amd_iommu_dump;
121
122 static int __initdata amd_iommu_detected;
123 static bool __initdata amd_iommu_disabled;
124
125 u16 amd_iommu_last_bdf; /* largest PCI device id we have
126 to handle */
127 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
128 we find in ACPI */
129 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
130
131 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
132 system */
133
134 /* Array to assign indices to IOMMUs*/
135 struct amd_iommu *amd_iommus[MAX_IOMMUS];
136 int amd_iommus_present;
137
138 /* IOMMUs have a non-present cache? */
139 bool amd_iommu_np_cache __read_mostly;
140 bool amd_iommu_iotlb_sup __read_mostly = true;
141
142 /*
143 * The ACPI table parsing functions set this variable on an error
144 */
145 static int __initdata amd_iommu_init_err;
146
147 /*
148 * List of protection domains - used during resume
149 */
150 LIST_HEAD(amd_iommu_pd_list);
151 spinlock_t amd_iommu_pd_lock;
152
153 /*
154 * Pointer to the device table which is shared by all AMD IOMMUs
155 * it is indexed by the PCI device id or the HT unit id and contains
156 * information about the domain the device belongs to as well as the
157 * page table root pointer.
158 */
159 struct dev_table_entry *amd_iommu_dev_table;
160
161 /*
162 * The alias table is a driver specific data structure which contains the
163 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
164 * More than one device can share the same requestor id.
165 */
166 u16 *amd_iommu_alias_table;
167
168 /*
169 * The rlookup table is used to find the IOMMU which is responsible
170 * for a specific device. It is also indexed by the PCI device id.
171 */
172 struct amd_iommu **amd_iommu_rlookup_table;
173
174 /*
175 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
176 * to know which ones are already in use.
177 */
178 unsigned long *amd_iommu_pd_alloc_bitmap;
179
180 static u32 dev_table_size; /* size of the device table */
181 static u32 alias_table_size; /* size of the alias table */
182 static u32 rlookup_table_size; /* size if the rlookup table */
183
184 /*
185 * This function flushes all internal caches of
186 * the IOMMU used by this driver.
187 */
188 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
189
190 static inline void update_last_devid(u16 devid)
191 {
192 if (devid > amd_iommu_last_bdf)
193 amd_iommu_last_bdf = devid;
194 }
195
196 static inline unsigned long tbl_size(int entry_size)
197 {
198 unsigned shift = PAGE_SHIFT +
199 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
200
201 return 1UL << shift;
202 }
203
204 /* Access to l1 and l2 indexed register spaces */
205
206 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
207 {
208 u32 val;
209
210 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
211 pci_read_config_dword(iommu->dev, 0xfc, &val);
212 return val;
213 }
214
215 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
216 {
217 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
218 pci_write_config_dword(iommu->dev, 0xfc, val);
219 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
220 }
221
222 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
223 {
224 u32 val;
225
226 pci_write_config_dword(iommu->dev, 0xf0, address);
227 pci_read_config_dword(iommu->dev, 0xf4, &val);
228 return val;
229 }
230
231 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
232 {
233 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
234 pci_write_config_dword(iommu->dev, 0xf4, val);
235 }
236
237 /****************************************************************************
238 *
239 * AMD IOMMU MMIO register space handling functions
240 *
241 * These functions are used to program the IOMMU device registers in
242 * MMIO space required for that driver.
243 *
244 ****************************************************************************/
245
246 /*
247 * This function set the exclusion range in the IOMMU. DMA accesses to the
248 * exclusion range are passed through untranslated
249 */
250 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
251 {
252 u64 start = iommu->exclusion_start & PAGE_MASK;
253 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
254 u64 entry;
255
256 if (!iommu->exclusion_start)
257 return;
258
259 entry = start | MMIO_EXCL_ENABLE_MASK;
260 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
261 &entry, sizeof(entry));
262
263 entry = limit;
264 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
265 &entry, sizeof(entry));
266 }
267
268 /* Programs the physical address of the device table into the IOMMU hardware */
269 static void __init iommu_set_device_table(struct amd_iommu *iommu)
270 {
271 u64 entry;
272
273 BUG_ON(iommu->mmio_base == NULL);
274
275 entry = virt_to_phys(amd_iommu_dev_table);
276 entry |= (dev_table_size >> 12) - 1;
277 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
278 &entry, sizeof(entry));
279 }
280
281 /* Generic functions to enable/disable certain features of the IOMMU. */
282 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
283 {
284 u32 ctrl;
285
286 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
287 ctrl |= (1 << bit);
288 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
289 }
290
291 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
292 {
293 u32 ctrl;
294
295 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
296 ctrl &= ~(1 << bit);
297 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
298 }
299
300 /* Function to enable the hardware */
301 static void iommu_enable(struct amd_iommu *iommu)
302 {
303 static const char * const feat_str[] = {
304 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
305 "IA", "GA", "HE", "PC", NULL
306 };
307 int i;
308
309 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx",
310 dev_name(&iommu->dev->dev), iommu->cap_ptr);
311
312 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
313 printk(KERN_CONT " extended features: ");
314 for (i = 0; feat_str[i]; ++i)
315 if (iommu_feature(iommu, (1ULL << i)))
316 printk(KERN_CONT " %s", feat_str[i]);
317 }
318 printk(KERN_CONT "\n");
319
320 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
321 }
322
323 static void iommu_disable(struct amd_iommu *iommu)
324 {
325 /* Disable command buffer */
326 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
327
328 /* Disable event logging and event interrupts */
329 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
330 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
331
332 /* Disable IOMMU hardware itself */
333 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
334 }
335
336 /*
337 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
338 * the system has one.
339 */
340 static u8 * __init iommu_map_mmio_space(u64 address)
341 {
342 u8 *ret;
343
344 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
345 pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
346 address);
347 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
348 return NULL;
349 }
350
351 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
352 if (ret != NULL)
353 return ret;
354
355 release_mem_region(address, MMIO_REGION_LENGTH);
356
357 return NULL;
358 }
359
360 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
361 {
362 if (iommu->mmio_base)
363 iounmap(iommu->mmio_base);
364 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
365 }
366
367 /****************************************************************************
368 *
369 * The functions below belong to the first pass of AMD IOMMU ACPI table
370 * parsing. In this pass we try to find out the highest device id this
371 * code has to handle. Upon this information the size of the shared data
372 * structures is determined later.
373 *
374 ****************************************************************************/
375
376 /*
377 * This function calculates the length of a given IVHD entry
378 */
379 static inline int ivhd_entry_length(u8 *ivhd)
380 {
381 return 0x04 << (*ivhd >> 6);
382 }
383
384 /*
385 * This function reads the last device id the IOMMU has to handle from the PCI
386 * capability header for this IOMMU
387 */
388 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
389 {
390 u32 cap;
391
392 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
393 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
394
395 return 0;
396 }
397
398 /*
399 * After reading the highest device id from the IOMMU PCI capability header
400 * this function looks if there is a higher device id defined in the ACPI table
401 */
402 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
403 {
404 u8 *p = (void *)h, *end = (void *)h;
405 struct ivhd_entry *dev;
406
407 p += sizeof(*h);
408 end += h->length;
409
410 find_last_devid_on_pci(PCI_BUS(h->devid),
411 PCI_SLOT(h->devid),
412 PCI_FUNC(h->devid),
413 h->cap_ptr);
414
415 while (p < end) {
416 dev = (struct ivhd_entry *)p;
417 switch (dev->type) {
418 case IVHD_DEV_SELECT:
419 case IVHD_DEV_RANGE_END:
420 case IVHD_DEV_ALIAS:
421 case IVHD_DEV_EXT_SELECT:
422 /* all the above subfield types refer to device ids */
423 update_last_devid(dev->devid);
424 break;
425 default:
426 break;
427 }
428 p += ivhd_entry_length(p);
429 }
430
431 WARN_ON(p != end);
432
433 return 0;
434 }
435
436 /*
437 * Iterate over all IVHD entries in the ACPI table and find the highest device
438 * id which we need to handle. This is the first of three functions which parse
439 * the ACPI table. So we check the checksum here.
440 */
441 static int __init find_last_devid_acpi(struct acpi_table_header *table)
442 {
443 int i;
444 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
445 struct ivhd_header *h;
446
447 /*
448 * Validate checksum here so we don't need to do it when
449 * we actually parse the table
450 */
451 for (i = 0; i < table->length; ++i)
452 checksum += p[i];
453 if (checksum != 0) {
454 /* ACPI table corrupt */
455 amd_iommu_init_err = -ENODEV;
456 return 0;
457 }
458
459 p += IVRS_HEADER_LENGTH;
460
461 end += table->length;
462 while (p < end) {
463 h = (struct ivhd_header *)p;
464 switch (h->type) {
465 case ACPI_IVHD_TYPE:
466 find_last_devid_from_ivhd(h);
467 break;
468 default:
469 break;
470 }
471 p += h->length;
472 }
473 WARN_ON(p != end);
474
475 return 0;
476 }
477
478 /****************************************************************************
479 *
480 * The following functions belong the the code path which parses the ACPI table
481 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
482 * data structures, initialize the device/alias/rlookup table and also
483 * basically initialize the hardware.
484 *
485 ****************************************************************************/
486
487 /*
488 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
489 * write commands to that buffer later and the IOMMU will execute them
490 * asynchronously
491 */
492 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
493 {
494 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
495 get_order(CMD_BUFFER_SIZE));
496
497 if (cmd_buf == NULL)
498 return NULL;
499
500 iommu->cmd_buf_size = CMD_BUFFER_SIZE | CMD_BUFFER_UNINITIALIZED;
501
502 return cmd_buf;
503 }
504
505 /*
506 * This function resets the command buffer if the IOMMU stopped fetching
507 * commands from it.
508 */
509 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
510 {
511 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
512
513 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
514 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
515
516 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
517 }
518
519 /*
520 * This function writes the command buffer address to the hardware and
521 * enables it.
522 */
523 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
524 {
525 u64 entry;
526
527 BUG_ON(iommu->cmd_buf == NULL);
528
529 entry = (u64)virt_to_phys(iommu->cmd_buf);
530 entry |= MMIO_CMD_SIZE_512;
531
532 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
533 &entry, sizeof(entry));
534
535 amd_iommu_reset_cmd_buffer(iommu);
536 iommu->cmd_buf_size &= ~(CMD_BUFFER_UNINITIALIZED);
537 }
538
539 static void __init free_command_buffer(struct amd_iommu *iommu)
540 {
541 free_pages((unsigned long)iommu->cmd_buf,
542 get_order(iommu->cmd_buf_size & ~(CMD_BUFFER_UNINITIALIZED)));
543 }
544
545 /* allocates the memory where the IOMMU will log its events to */
546 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
547 {
548 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
549 get_order(EVT_BUFFER_SIZE));
550
551 if (iommu->evt_buf == NULL)
552 return NULL;
553
554 iommu->evt_buf_size = EVT_BUFFER_SIZE;
555
556 return iommu->evt_buf;
557 }
558
559 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
560 {
561 u64 entry;
562
563 BUG_ON(iommu->evt_buf == NULL);
564
565 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
566
567 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
568 &entry, sizeof(entry));
569
570 /* set head and tail to zero manually */
571 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
572 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
573
574 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
575 }
576
577 static void __init free_event_buffer(struct amd_iommu *iommu)
578 {
579 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
580 }
581
582 /* sets a specific bit in the device table entry. */
583 static void set_dev_entry_bit(u16 devid, u8 bit)
584 {
585 int i = (bit >> 5) & 0x07;
586 int _bit = bit & 0x1f;
587
588 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
589 }
590
591 static int get_dev_entry_bit(u16 devid, u8 bit)
592 {
593 int i = (bit >> 5) & 0x07;
594 int _bit = bit & 0x1f;
595
596 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
597 }
598
599
600 void amd_iommu_apply_erratum_63(u16 devid)
601 {
602 int sysmgt;
603
604 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
605 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
606
607 if (sysmgt == 0x01)
608 set_dev_entry_bit(devid, DEV_ENTRY_IW);
609 }
610
611 /* Writes the specific IOMMU for a device into the rlookup table */
612 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
613 {
614 amd_iommu_rlookup_table[devid] = iommu;
615 }
616
617 /*
618 * This function takes the device specific flags read from the ACPI
619 * table and sets up the device table entry with that information
620 */
621 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
622 u16 devid, u32 flags, u32 ext_flags)
623 {
624 if (flags & ACPI_DEVFLAG_INITPASS)
625 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
626 if (flags & ACPI_DEVFLAG_EXTINT)
627 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
628 if (flags & ACPI_DEVFLAG_NMI)
629 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
630 if (flags & ACPI_DEVFLAG_SYSMGT1)
631 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
632 if (flags & ACPI_DEVFLAG_SYSMGT2)
633 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
634 if (flags & ACPI_DEVFLAG_LINT0)
635 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
636 if (flags & ACPI_DEVFLAG_LINT1)
637 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
638
639 amd_iommu_apply_erratum_63(devid);
640
641 set_iommu_for_device(iommu, devid);
642 }
643
644 /*
645 * Reads the device exclusion range from ACPI and initialize IOMMU with
646 * it
647 */
648 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
649 {
650 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
651
652 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
653 return;
654
655 if (iommu) {
656 /*
657 * We only can configure exclusion ranges per IOMMU, not
658 * per device. But we can enable the exclusion range per
659 * device. This is done here
660 */
661 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
662 iommu->exclusion_start = m->range_start;
663 iommu->exclusion_length = m->range_length;
664 }
665 }
666
667 /*
668 * This function reads some important data from the IOMMU PCI space and
669 * initializes the driver data structure with it. It reads the hardware
670 * capabilities and the first/last device entries
671 */
672 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
673 {
674 int cap_ptr = iommu->cap_ptr;
675 u32 range, misc, low, high;
676 int i, j;
677
678 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
679 &iommu->cap);
680 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
681 &range);
682 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
683 &misc);
684
685 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
686 MMIO_GET_FD(range));
687 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
688 MMIO_GET_LD(range));
689 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
690
691 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
692 amd_iommu_iotlb_sup = false;
693
694 /* read extended feature bits */
695 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
696 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
697
698 iommu->features = ((u64)high << 32) | low;
699
700 if (!is_rd890_iommu(iommu->dev))
701 return;
702
703 /*
704 * Some rd890 systems may not be fully reconfigured by the BIOS, so
705 * it's necessary for us to store this information so it can be
706 * reprogrammed on resume
707 */
708
709 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
710 &iommu->stored_addr_lo);
711 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
712 &iommu->stored_addr_hi);
713
714 /* Low bit locks writes to configuration space */
715 iommu->stored_addr_lo &= ~1;
716
717 for (i = 0; i < 6; i++)
718 for (j = 0; j < 0x12; j++)
719 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
720
721 for (i = 0; i < 0x83; i++)
722 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
723 }
724
725 /*
726 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
727 * initializes the hardware and our data structures with it.
728 */
729 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
730 struct ivhd_header *h)
731 {
732 u8 *p = (u8 *)h;
733 u8 *end = p, flags = 0;
734 u16 devid = 0, devid_start = 0, devid_to = 0;
735 u32 dev_i, ext_flags = 0;
736 bool alias = false;
737 struct ivhd_entry *e;
738
739 /*
740 * First save the recommended feature enable bits from ACPI
741 */
742 iommu->acpi_flags = h->flags;
743
744 /*
745 * Done. Now parse the device entries
746 */
747 p += sizeof(struct ivhd_header);
748 end += h->length;
749
750
751 while (p < end) {
752 e = (struct ivhd_entry *)p;
753 switch (e->type) {
754 case IVHD_DEV_ALL:
755
756 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
757 " last device %02x:%02x.%x flags: %02x\n",
758 PCI_BUS(iommu->first_device),
759 PCI_SLOT(iommu->first_device),
760 PCI_FUNC(iommu->first_device),
761 PCI_BUS(iommu->last_device),
762 PCI_SLOT(iommu->last_device),
763 PCI_FUNC(iommu->last_device),
764 e->flags);
765
766 for (dev_i = iommu->first_device;
767 dev_i <= iommu->last_device; ++dev_i)
768 set_dev_entry_from_acpi(iommu, dev_i,
769 e->flags, 0);
770 break;
771 case IVHD_DEV_SELECT:
772
773 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
774 "flags: %02x\n",
775 PCI_BUS(e->devid),
776 PCI_SLOT(e->devid),
777 PCI_FUNC(e->devid),
778 e->flags);
779
780 devid = e->devid;
781 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
782 break;
783 case IVHD_DEV_SELECT_RANGE_START:
784
785 DUMP_printk(" DEV_SELECT_RANGE_START\t "
786 "devid: %02x:%02x.%x flags: %02x\n",
787 PCI_BUS(e->devid),
788 PCI_SLOT(e->devid),
789 PCI_FUNC(e->devid),
790 e->flags);
791
792 devid_start = e->devid;
793 flags = e->flags;
794 ext_flags = 0;
795 alias = false;
796 break;
797 case IVHD_DEV_ALIAS:
798
799 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
800 "flags: %02x devid_to: %02x:%02x.%x\n",
801 PCI_BUS(e->devid),
802 PCI_SLOT(e->devid),
803 PCI_FUNC(e->devid),
804 e->flags,
805 PCI_BUS(e->ext >> 8),
806 PCI_SLOT(e->ext >> 8),
807 PCI_FUNC(e->ext >> 8));
808
809 devid = e->devid;
810 devid_to = e->ext >> 8;
811 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
812 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
813 amd_iommu_alias_table[devid] = devid_to;
814 break;
815 case IVHD_DEV_ALIAS_RANGE:
816
817 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
818 "devid: %02x:%02x.%x flags: %02x "
819 "devid_to: %02x:%02x.%x\n",
820 PCI_BUS(e->devid),
821 PCI_SLOT(e->devid),
822 PCI_FUNC(e->devid),
823 e->flags,
824 PCI_BUS(e->ext >> 8),
825 PCI_SLOT(e->ext >> 8),
826 PCI_FUNC(e->ext >> 8));
827
828 devid_start = e->devid;
829 flags = e->flags;
830 devid_to = e->ext >> 8;
831 ext_flags = 0;
832 alias = true;
833 break;
834 case IVHD_DEV_EXT_SELECT:
835
836 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
837 "flags: %02x ext: %08x\n",
838 PCI_BUS(e->devid),
839 PCI_SLOT(e->devid),
840 PCI_FUNC(e->devid),
841 e->flags, e->ext);
842
843 devid = e->devid;
844 set_dev_entry_from_acpi(iommu, devid, e->flags,
845 e->ext);
846 break;
847 case IVHD_DEV_EXT_SELECT_RANGE:
848
849 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
850 "%02x:%02x.%x flags: %02x ext: %08x\n",
851 PCI_BUS(e->devid),
852 PCI_SLOT(e->devid),
853 PCI_FUNC(e->devid),
854 e->flags, e->ext);
855
856 devid_start = e->devid;
857 flags = e->flags;
858 ext_flags = e->ext;
859 alias = false;
860 break;
861 case IVHD_DEV_RANGE_END:
862
863 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
864 PCI_BUS(e->devid),
865 PCI_SLOT(e->devid),
866 PCI_FUNC(e->devid));
867
868 devid = e->devid;
869 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
870 if (alias) {
871 amd_iommu_alias_table[dev_i] = devid_to;
872 set_dev_entry_from_acpi(iommu,
873 devid_to, flags, ext_flags);
874 }
875 set_dev_entry_from_acpi(iommu, dev_i,
876 flags, ext_flags);
877 }
878 break;
879 default:
880 break;
881 }
882
883 p += ivhd_entry_length(p);
884 }
885 }
886
887 /* Initializes the device->iommu mapping for the driver */
888 static int __init init_iommu_devices(struct amd_iommu *iommu)
889 {
890 u32 i;
891
892 for (i = iommu->first_device; i <= iommu->last_device; ++i)
893 set_iommu_for_device(iommu, i);
894
895 return 0;
896 }
897
898 static void __init free_iommu_one(struct amd_iommu *iommu)
899 {
900 free_command_buffer(iommu);
901 free_event_buffer(iommu);
902 iommu_unmap_mmio_space(iommu);
903 }
904
905 static void __init free_iommu_all(void)
906 {
907 struct amd_iommu *iommu, *next;
908
909 for_each_iommu_safe(iommu, next) {
910 list_del(&iommu->list);
911 free_iommu_one(iommu);
912 kfree(iommu);
913 }
914 }
915
916 /*
917 * This function clues the initialization function for one IOMMU
918 * together and also allocates the command buffer and programs the
919 * hardware. It does NOT enable the IOMMU. This is done afterwards.
920 */
921 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
922 {
923 spin_lock_init(&iommu->lock);
924
925 /* Add IOMMU to internal data structures */
926 list_add_tail(&iommu->list, &amd_iommu_list);
927 iommu->index = amd_iommus_present++;
928
929 if (unlikely(iommu->index >= MAX_IOMMUS)) {
930 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
931 return -ENOSYS;
932 }
933
934 /* Index is fine - add IOMMU to the array */
935 amd_iommus[iommu->index] = iommu;
936
937 /*
938 * Copy data from ACPI table entry to the iommu struct
939 */
940 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
941 if (!iommu->dev)
942 return 1;
943
944 iommu->cap_ptr = h->cap_ptr;
945 iommu->pci_seg = h->pci_seg;
946 iommu->mmio_phys = h->mmio_phys;
947 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
948 if (!iommu->mmio_base)
949 return -ENOMEM;
950
951 iommu->cmd_buf = alloc_command_buffer(iommu);
952 if (!iommu->cmd_buf)
953 return -ENOMEM;
954
955 iommu->evt_buf = alloc_event_buffer(iommu);
956 if (!iommu->evt_buf)
957 return -ENOMEM;
958
959 iommu->int_enabled = false;
960
961 init_iommu_from_pci(iommu);
962 init_iommu_from_acpi(iommu, h);
963 init_iommu_devices(iommu);
964
965 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
966 amd_iommu_np_cache = true;
967
968 return pci_enable_device(iommu->dev);
969 }
970
971 /*
972 * Iterates over all IOMMU entries in the ACPI table, allocates the
973 * IOMMU structure and initializes it with init_iommu_one()
974 */
975 static int __init init_iommu_all(struct acpi_table_header *table)
976 {
977 u8 *p = (u8 *)table, *end = (u8 *)table;
978 struct ivhd_header *h;
979 struct amd_iommu *iommu;
980 int ret;
981
982 end += table->length;
983 p += IVRS_HEADER_LENGTH;
984
985 while (p < end) {
986 h = (struct ivhd_header *)p;
987 switch (*p) {
988 case ACPI_IVHD_TYPE:
989
990 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
991 "seg: %d flags: %01x info %04x\n",
992 PCI_BUS(h->devid), PCI_SLOT(h->devid),
993 PCI_FUNC(h->devid), h->cap_ptr,
994 h->pci_seg, h->flags, h->info);
995 DUMP_printk(" mmio-addr: %016llx\n",
996 h->mmio_phys);
997
998 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
999 if (iommu == NULL) {
1000 amd_iommu_init_err = -ENOMEM;
1001 return 0;
1002 }
1003
1004 ret = init_iommu_one(iommu, h);
1005 if (ret) {
1006 amd_iommu_init_err = ret;
1007 return 0;
1008 }
1009 break;
1010 default:
1011 break;
1012 }
1013 p += h->length;
1014
1015 }
1016 WARN_ON(p != end);
1017
1018 return 0;
1019 }
1020
1021 /****************************************************************************
1022 *
1023 * The following functions initialize the MSI interrupts for all IOMMUs
1024 * in the system. Its a bit challenging because there could be multiple
1025 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1026 * pci_dev.
1027 *
1028 ****************************************************************************/
1029
1030 static int iommu_setup_msi(struct amd_iommu *iommu)
1031 {
1032 int r;
1033
1034 r = pci_enable_msi(iommu->dev);
1035 if (r)
1036 return r;
1037
1038 r = request_threaded_irq(iommu->dev->irq,
1039 amd_iommu_int_handler,
1040 amd_iommu_int_thread,
1041 0, "AMD-Vi",
1042 iommu->dev);
1043
1044 if (r) {
1045 pci_disable_msi(iommu->dev);
1046 return r;
1047 }
1048
1049 iommu->int_enabled = true;
1050
1051 return 0;
1052 }
1053
1054 static int iommu_init_msi(struct amd_iommu *iommu)
1055 {
1056 int ret;
1057
1058 if (iommu->int_enabled)
1059 goto enable_faults;
1060
1061 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
1062 ret = iommu_setup_msi(iommu);
1063 else
1064 ret = -ENODEV;
1065
1066 if (ret)
1067 return ret;
1068
1069 enable_faults:
1070 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1071
1072 return 0;
1073 }
1074
1075 /****************************************************************************
1076 *
1077 * The next functions belong to the third pass of parsing the ACPI
1078 * table. In this last pass the memory mapping requirements are
1079 * gathered (like exclusion and unity mapping reanges).
1080 *
1081 ****************************************************************************/
1082
1083 static void __init free_unity_maps(void)
1084 {
1085 struct unity_map_entry *entry, *next;
1086
1087 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1088 list_del(&entry->list);
1089 kfree(entry);
1090 }
1091 }
1092
1093 /* called when we find an exclusion range definition in ACPI */
1094 static int __init init_exclusion_range(struct ivmd_header *m)
1095 {
1096 int i;
1097
1098 switch (m->type) {
1099 case ACPI_IVMD_TYPE:
1100 set_device_exclusion_range(m->devid, m);
1101 break;
1102 case ACPI_IVMD_TYPE_ALL:
1103 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1104 set_device_exclusion_range(i, m);
1105 break;
1106 case ACPI_IVMD_TYPE_RANGE:
1107 for (i = m->devid; i <= m->aux; ++i)
1108 set_device_exclusion_range(i, m);
1109 break;
1110 default:
1111 break;
1112 }
1113
1114 return 0;
1115 }
1116
1117 /* called for unity map ACPI definition */
1118 static int __init init_unity_map_range(struct ivmd_header *m)
1119 {
1120 struct unity_map_entry *e = 0;
1121 char *s;
1122
1123 e = kzalloc(sizeof(*e), GFP_KERNEL);
1124 if (e == NULL)
1125 return -ENOMEM;
1126
1127 switch (m->type) {
1128 default:
1129 kfree(e);
1130 return 0;
1131 case ACPI_IVMD_TYPE:
1132 s = "IVMD_TYPEi\t\t\t";
1133 e->devid_start = e->devid_end = m->devid;
1134 break;
1135 case ACPI_IVMD_TYPE_ALL:
1136 s = "IVMD_TYPE_ALL\t\t";
1137 e->devid_start = 0;
1138 e->devid_end = amd_iommu_last_bdf;
1139 break;
1140 case ACPI_IVMD_TYPE_RANGE:
1141 s = "IVMD_TYPE_RANGE\t\t";
1142 e->devid_start = m->devid;
1143 e->devid_end = m->aux;
1144 break;
1145 }
1146 e->address_start = PAGE_ALIGN(m->range_start);
1147 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1148 e->prot = m->flags >> 1;
1149
1150 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1151 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1152 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1153 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1154 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1155 e->address_start, e->address_end, m->flags);
1156
1157 list_add_tail(&e->list, &amd_iommu_unity_map);
1158
1159 return 0;
1160 }
1161
1162 /* iterates over all memory definitions we find in the ACPI table */
1163 static int __init init_memory_definitions(struct acpi_table_header *table)
1164 {
1165 u8 *p = (u8 *)table, *end = (u8 *)table;
1166 struct ivmd_header *m;
1167
1168 end += table->length;
1169 p += IVRS_HEADER_LENGTH;
1170
1171 while (p < end) {
1172 m = (struct ivmd_header *)p;
1173 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1174 init_exclusion_range(m);
1175 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1176 init_unity_map_range(m);
1177
1178 p += m->length;
1179 }
1180
1181 return 0;
1182 }
1183
1184 /*
1185 * Init the device table to not allow DMA access for devices and
1186 * suppress all page faults
1187 */
1188 static void init_device_table(void)
1189 {
1190 u32 devid;
1191
1192 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1193 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1194 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1195 }
1196 }
1197
1198 static void iommu_init_flags(struct amd_iommu *iommu)
1199 {
1200 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1201 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1202 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1203
1204 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1205 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1206 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1207
1208 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1209 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1210 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1211
1212 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1213 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1214 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1215
1216 /*
1217 * make IOMMU memory accesses cache coherent
1218 */
1219 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1220 }
1221
1222 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1223 {
1224 int i, j;
1225 u32 ioc_feature_control;
1226 struct pci_dev *pdev = NULL;
1227
1228 /* RD890 BIOSes may not have completely reconfigured the iommu */
1229 if (!is_rd890_iommu(iommu->dev))
1230 return;
1231
1232 /*
1233 * First, we need to ensure that the iommu is enabled. This is
1234 * controlled by a register in the northbridge
1235 */
1236 pdev = pci_get_bus_and_slot(iommu->dev->bus->number, PCI_DEVFN(0, 0));
1237
1238 if (!pdev)
1239 return;
1240
1241 /* Select Northbridge indirect register 0x75 and enable writing */
1242 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1243 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1244
1245 /* Enable the iommu */
1246 if (!(ioc_feature_control & 0x1))
1247 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1248
1249 pci_dev_put(pdev);
1250
1251 /* Restore the iommu BAR */
1252 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1253 iommu->stored_addr_lo);
1254 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1255 iommu->stored_addr_hi);
1256
1257 /* Restore the l1 indirect regs for each of the 6 l1s */
1258 for (i = 0; i < 6; i++)
1259 for (j = 0; j < 0x12; j++)
1260 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1261
1262 /* Restore the l2 indirect regs */
1263 for (i = 0; i < 0x83; i++)
1264 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1265
1266 /* Lock PCI setup registers */
1267 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1268 iommu->stored_addr_lo | 1);
1269 }
1270
1271 /*
1272 * This function finally enables all IOMMUs found in the system after
1273 * they have been initialized
1274 */
1275 static void enable_iommus(void)
1276 {
1277 struct amd_iommu *iommu;
1278
1279 for_each_iommu(iommu) {
1280 iommu_disable(iommu);
1281 iommu_init_flags(iommu);
1282 iommu_set_device_table(iommu);
1283 iommu_enable_command_buffer(iommu);
1284 iommu_enable_event_buffer(iommu);
1285 iommu_set_exclusion_range(iommu);
1286 iommu_init_msi(iommu);
1287 iommu_enable(iommu);
1288 iommu_flush_all_caches(iommu);
1289 }
1290 }
1291
1292 static void disable_iommus(void)
1293 {
1294 struct amd_iommu *iommu;
1295
1296 for_each_iommu(iommu)
1297 iommu_disable(iommu);
1298 }
1299
1300 /*
1301 * Suspend/Resume support
1302 * disable suspend until real resume implemented
1303 */
1304
1305 static void amd_iommu_resume(void)
1306 {
1307 struct amd_iommu *iommu;
1308
1309 for_each_iommu(iommu)
1310 iommu_apply_resume_quirks(iommu);
1311
1312 /* re-load the hardware */
1313 enable_iommus();
1314
1315 /*
1316 * we have to flush after the IOMMUs are enabled because a
1317 * disabled IOMMU will never execute the commands we send
1318 */
1319 for_each_iommu(iommu)
1320 iommu_flush_all_caches(iommu);
1321 }
1322
1323 static int amd_iommu_suspend(void)
1324 {
1325 /* disable IOMMUs to go out of the way for BIOS */
1326 disable_iommus();
1327
1328 return 0;
1329 }
1330
1331 static struct syscore_ops amd_iommu_syscore_ops = {
1332 .suspend = amd_iommu_suspend,
1333 .resume = amd_iommu_resume,
1334 };
1335
1336 /*
1337 * This is the core init function for AMD IOMMU hardware in the system.
1338 * This function is called from the generic x86 DMA layer initialization
1339 * code.
1340 *
1341 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1342 * three times:
1343 *
1344 * 1 pass) Find the highest PCI device id the driver has to handle.
1345 * Upon this information the size of the data structures is
1346 * determined that needs to be allocated.
1347 *
1348 * 2 pass) Initialize the data structures just allocated with the
1349 * information in the ACPI table about available AMD IOMMUs
1350 * in the system. It also maps the PCI devices in the
1351 * system to specific IOMMUs
1352 *
1353 * 3 pass) After the basic data structures are allocated and
1354 * initialized we update them with information about memory
1355 * remapping requirements parsed out of the ACPI table in
1356 * this last pass.
1357 *
1358 * After that the hardware is initialized and ready to go. In the last
1359 * step we do some Linux specific things like registering the driver in
1360 * the dma_ops interface and initializing the suspend/resume support
1361 * functions. Finally it prints some information about AMD IOMMUs and
1362 * the driver state and enables the hardware.
1363 */
1364 static int __init amd_iommu_init(void)
1365 {
1366 int i, ret = 0;
1367
1368 /*
1369 * First parse ACPI tables to find the largest Bus/Dev/Func
1370 * we need to handle. Upon this information the shared data
1371 * structures for the IOMMUs in the system will be allocated
1372 */
1373 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1374 return -ENODEV;
1375
1376 ret = amd_iommu_init_err;
1377 if (ret)
1378 goto out;
1379
1380 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1381 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1382 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1383
1384 ret = -ENOMEM;
1385
1386 /* Device table - directly used by all IOMMUs */
1387 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1388 get_order(dev_table_size));
1389 if (amd_iommu_dev_table == NULL)
1390 goto out;
1391
1392 /*
1393 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1394 * IOMMU see for that device
1395 */
1396 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1397 get_order(alias_table_size));
1398 if (amd_iommu_alias_table == NULL)
1399 goto free;
1400
1401 /* IOMMU rlookup table - find the IOMMU for a specific device */
1402 amd_iommu_rlookup_table = (void *)__get_free_pages(
1403 GFP_KERNEL | __GFP_ZERO,
1404 get_order(rlookup_table_size));
1405 if (amd_iommu_rlookup_table == NULL)
1406 goto free;
1407
1408 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1409 GFP_KERNEL | __GFP_ZERO,
1410 get_order(MAX_DOMAIN_ID/8));
1411 if (amd_iommu_pd_alloc_bitmap == NULL)
1412 goto free;
1413
1414 /* init the device table */
1415 init_device_table();
1416
1417 /*
1418 * let all alias entries point to itself
1419 */
1420 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1421 amd_iommu_alias_table[i] = i;
1422
1423 /*
1424 * never allocate domain 0 because its used as the non-allocated and
1425 * error value placeholder
1426 */
1427 amd_iommu_pd_alloc_bitmap[0] = 1;
1428
1429 spin_lock_init(&amd_iommu_pd_lock);
1430
1431 /*
1432 * now the data structures are allocated and basically initialized
1433 * start the real acpi table scan
1434 */
1435 ret = -ENODEV;
1436 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1437 goto free;
1438
1439 if (amd_iommu_init_err) {
1440 ret = amd_iommu_init_err;
1441 goto free;
1442 }
1443
1444 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1445 goto free;
1446
1447 if (amd_iommu_init_err) {
1448 ret = amd_iommu_init_err;
1449 goto free;
1450 }
1451
1452 ret = amd_iommu_init_devices();
1453 if (ret)
1454 goto free;
1455
1456 enable_iommus();
1457
1458 if (iommu_pass_through)
1459 ret = amd_iommu_init_passthrough();
1460 else
1461 ret = amd_iommu_init_dma_ops();
1462
1463 if (ret)
1464 goto free_disable;
1465
1466 amd_iommu_init_api();
1467
1468 amd_iommu_init_notifier();
1469
1470 register_syscore_ops(&amd_iommu_syscore_ops);
1471
1472 if (iommu_pass_through)
1473 goto out;
1474
1475 if (amd_iommu_unmap_flush)
1476 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1477 else
1478 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1479
1480 x86_platform.iommu_shutdown = disable_iommus;
1481 out:
1482 return ret;
1483
1484 free_disable:
1485 disable_iommus();
1486
1487 free:
1488 amd_iommu_uninit_devices();
1489
1490 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1491 get_order(MAX_DOMAIN_ID/8));
1492
1493 free_pages((unsigned long)amd_iommu_rlookup_table,
1494 get_order(rlookup_table_size));
1495
1496 free_pages((unsigned long)amd_iommu_alias_table,
1497 get_order(alias_table_size));
1498
1499 free_pages((unsigned long)amd_iommu_dev_table,
1500 get_order(dev_table_size));
1501
1502 free_iommu_all();
1503
1504 free_unity_maps();
1505
1506 #ifdef CONFIG_GART_IOMMU
1507 /*
1508 * We failed to initialize the AMD IOMMU - try fallback to GART
1509 * if possible.
1510 */
1511 gart_iommu_init();
1512
1513 #endif
1514
1515 goto out;
1516 }
1517
1518 /****************************************************************************
1519 *
1520 * Early detect code. This code runs at IOMMU detection time in the DMA
1521 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1522 * IOMMUs
1523 *
1524 ****************************************************************************/
1525 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1526 {
1527 return 0;
1528 }
1529
1530 int __init amd_iommu_detect(void)
1531 {
1532 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
1533 return -ENODEV;
1534
1535 if (amd_iommu_disabled)
1536 return -ENODEV;
1537
1538 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1539 iommu_detected = 1;
1540 amd_iommu_detected = 1;
1541 x86_init.iommu.iommu_init = amd_iommu_init;
1542
1543 /* Make sure ACS will be enabled */
1544 pci_request_acs();
1545 return 1;
1546 }
1547 return -ENODEV;
1548 }
1549
1550 /****************************************************************************
1551 *
1552 * Parsing functions for the AMD IOMMU specific kernel command line
1553 * options.
1554 *
1555 ****************************************************************************/
1556
1557 static int __init parse_amd_iommu_dump(char *str)
1558 {
1559 amd_iommu_dump = true;
1560
1561 return 1;
1562 }
1563
1564 static int __init parse_amd_iommu_options(char *str)
1565 {
1566 for (; *str; ++str) {
1567 if (strncmp(str, "fullflush", 9) == 0)
1568 amd_iommu_unmap_flush = true;
1569 if (strncmp(str, "off", 3) == 0)
1570 amd_iommu_disabled = true;
1571 }
1572
1573 return 1;
1574 }
1575
1576 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1577 __setup("amd_iommu=", parse_amd_iommu_options);
1578
1579 IOMMU_INIT_FINISH(amd_iommu_detect,
1580 gart_iommu_hole_init,
1581 0,
1582 0);
Linux with added FPC-III support