2 * drivers/mtd/nand/ams-delta.c
4 * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
6 * Derived from drivers/mtd/toto.c
7 * Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
8 * Partially stolen from drivers/mtd/nand/plat_nand.c
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 * This is a device driver for the NAND flash device found on the
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/nand.h>
25 #include <linux/mtd/partitions.h>
27 #include <mach/hardware.h>
28 #include <asm/sizes.h>
29 #include <mach/gpio.h>
30 #include <plat/board-ams-delta.h>
33 * MTD structure for E3 (Delta)
35 static struct mtd_info
*ams_delta_mtd
= NULL
;
37 #define NAND_MASK (AMS_DELTA_LATCH2_NAND_NRE | AMS_DELTA_LATCH2_NAND_NWE | AMS_DELTA_LATCH2_NAND_CLE | AMS_DELTA_LATCH2_NAND_ALE | AMS_DELTA_LATCH2_NAND_NCE | AMS_DELTA_LATCH2_NAND_NWP)
40 * Define partitions for flash devices
43 static struct mtd_partition partition_info
[] = {
46 .size
= 3 * SZ_1M
+ SZ_512K
},
48 .offset
= 3 * SZ_1M
+ SZ_512K
,
50 { .name
= "u-boot params",
51 .offset
= 3 * SZ_1M
+ SZ_512K
+ SZ_256K
,
53 { .name
= "Amstrad LDR",
56 { .name
= "File system",
57 .offset
= 4 * SZ_1M
+ 1 * SZ_256K
,
59 { .name
= "PBL reserved",
60 .offset
= 32 * SZ_1M
- 3 * SZ_256K
,
61 .size
= 3 * SZ_256K
},
64 static void ams_delta_write_byte(struct mtd_info
*mtd
, u_char byte
)
66 struct nand_chip
*this = mtd
->priv
;
67 void __iomem
*io_base
= this->priv
;
69 writew(0, io_base
+ OMAP_MPUIO_IO_CNTL
);
70 writew(byte
, this->IO_ADDR_W
);
71 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE
, 0);
73 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE
,
74 AMS_DELTA_LATCH2_NAND_NWE
);
77 static u_char
ams_delta_read_byte(struct mtd_info
*mtd
)
80 struct nand_chip
*this = mtd
->priv
;
81 void __iomem
*io_base
= this->priv
;
83 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE
, 0);
85 writew(~0, io_base
+ OMAP_MPUIO_IO_CNTL
);
86 res
= readw(this->IO_ADDR_R
);
87 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE
,
88 AMS_DELTA_LATCH2_NAND_NRE
);
93 static void ams_delta_write_buf(struct mtd_info
*mtd
, const u_char
*buf
,
99 ams_delta_write_byte(mtd
, buf
[i
]);
102 static void ams_delta_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
106 for (i
=0; i
<len
; i
++)
107 buf
[i
] = ams_delta_read_byte(mtd
);
110 static int ams_delta_verify_buf(struct mtd_info
*mtd
, const u_char
*buf
,
115 for (i
=0; i
<len
; i
++)
116 if (buf
[i
] != ams_delta_read_byte(mtd
))
123 * Command control function
126 * NAND_NCE: bit 0 -> bit 2
127 * NAND_CLE: bit 1 -> bit 7
128 * NAND_ALE: bit 2 -> bit 6
130 static void ams_delta_hwcontrol(struct mtd_info
*mtd
, int cmd
,
134 if (ctrl
& NAND_CTRL_CHANGE
) {
137 bits
= (~ctrl
& NAND_NCE
) ? AMS_DELTA_LATCH2_NAND_NCE
: 0;
138 bits
|= (ctrl
& NAND_CLE
) ? AMS_DELTA_LATCH2_NAND_CLE
: 0;
139 bits
|= (ctrl
& NAND_ALE
) ? AMS_DELTA_LATCH2_NAND_ALE
: 0;
141 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_CLE
|
142 AMS_DELTA_LATCH2_NAND_ALE
|
143 AMS_DELTA_LATCH2_NAND_NCE
, bits
);
146 if (cmd
!= NAND_CMD_NONE
)
147 ams_delta_write_byte(mtd
, cmd
);
150 static int ams_delta_nand_ready(struct mtd_info
*mtd
)
152 return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB
);
156 * Main initialization routine
158 static int __devinit
ams_delta_init(struct platform_device
*pdev
)
160 struct nand_chip
*this;
161 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
162 void __iomem
*io_base
;
168 /* Allocate memory for MTD device structure and private data */
169 ams_delta_mtd
= kmalloc(sizeof(struct mtd_info
) +
170 sizeof(struct nand_chip
), GFP_KERNEL
);
171 if (!ams_delta_mtd
) {
172 printk (KERN_WARNING
"Unable to allocate E3 NAND MTD device structure.\n");
177 ams_delta_mtd
->owner
= THIS_MODULE
;
179 /* Get pointer to private data */
180 this = (struct nand_chip
*) (&ams_delta_mtd
[1]);
182 /* Initialize structures */
183 memset(ams_delta_mtd
, 0, sizeof(struct mtd_info
));
184 memset(this, 0, sizeof(struct nand_chip
));
186 /* Link the private data with the MTD structure */
187 ams_delta_mtd
->priv
= this;
189 if (!request_mem_region(res
->start
, resource_size(res
),
190 dev_name(&pdev
->dev
))) {
191 dev_err(&pdev
->dev
, "request_mem_region failed\n");
196 io_base
= ioremap(res
->start
, resource_size(res
));
197 if (io_base
== NULL
) {
198 dev_err(&pdev
->dev
, "ioremap failed\n");
203 this->priv
= io_base
;
205 /* Set address of NAND IO lines */
206 this->IO_ADDR_R
= io_base
+ OMAP_MPUIO_INPUT_LATCH
;
207 this->IO_ADDR_W
= io_base
+ OMAP_MPUIO_OUTPUT
;
208 this->read_byte
= ams_delta_read_byte
;
209 this->write_buf
= ams_delta_write_buf
;
210 this->read_buf
= ams_delta_read_buf
;
211 this->verify_buf
= ams_delta_verify_buf
;
212 this->cmd_ctrl
= ams_delta_hwcontrol
;
213 if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB
, "nand_rdy") == 0) {
214 this->dev_ready
= ams_delta_nand_ready
;
216 this->dev_ready
= NULL
;
217 printk(KERN_NOTICE
"Couldn't request gpio for Delta NAND ready.\n");
219 /* 25 us command delay time */
220 this->chip_delay
= 30;
221 this->ecc
.mode
= NAND_ECC_SOFT
;
223 platform_set_drvdata(pdev
, io_base
);
225 /* Set chip enabled, but */
226 ams_delta_latch2_write(NAND_MASK
, AMS_DELTA_LATCH2_NAND_NRE
|
227 AMS_DELTA_LATCH2_NAND_NWE
|
228 AMS_DELTA_LATCH2_NAND_NCE
|
229 AMS_DELTA_LATCH2_NAND_NWP
);
231 /* Scan to find existence of the device */
232 if (nand_scan(ams_delta_mtd
, 1)) {
237 /* Register the partitions */
238 mtd_device_register(ams_delta_mtd
, partition_info
,
239 ARRAY_SIZE(partition_info
));
244 platform_set_drvdata(pdev
, NULL
);
247 release_mem_region(res
->start
, resource_size(res
));
249 kfree(ams_delta_mtd
);
257 static int __devexit
ams_delta_cleanup(struct platform_device
*pdev
)
259 void __iomem
*io_base
= platform_get_drvdata(pdev
);
260 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
262 /* Release resources, unregister device */
263 nand_release(ams_delta_mtd
);
266 release_mem_region(res
->start
, resource_size(res
));
268 /* Free the MTD device structure */
269 kfree(ams_delta_mtd
);
274 static struct platform_driver ams_delta_nand_driver
= {
275 .probe
= ams_delta_init
,
276 .remove
= __devexit_p(ams_delta_cleanup
),
278 .name
= "ams-delta-nand",
279 .owner
= THIS_MODULE
,
283 static int __init
ams_delta_nand_init(void)
285 return platform_driver_register(&ams_delta_nand_driver
);
287 module_init(ams_delta_nand_init
);
289 static void __exit
ams_delta_nand_exit(void)
291 platform_driver_unregister(&ams_delta_nand_driver
);
293 module_exit(ams_delta_nand_exit
);
295 MODULE_LICENSE("GPL");
296 MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
297 MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");