1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/types.h>
32 #include <linux/delay.h>
34 #include <linux/netdevice.h>
36 #include "e1000_regs.h"
37 #include "e1000_defines.h"
41 #define E1000_DEV_ID_82576 0x10C9
42 #define E1000_DEV_ID_82576_FIBER 0x10E6
43 #define E1000_DEV_ID_82576_SERDES 0x10E7
44 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
45 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
46 #define E1000_DEV_ID_82576_NS 0x150A
47 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
48 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
49 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
50 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
51 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
52 #define E1000_DEV_ID_82580_COPPER 0x150E
53 #define E1000_DEV_ID_82580_FIBER 0x150F
54 #define E1000_DEV_ID_82580_SERDES 0x1510
55 #define E1000_DEV_ID_82580_SGMII 0x1511
56 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
57 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
58 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
59 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
60 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
61 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
62 #define E1000_DEV_ID_I350_COPPER 0x1521
63 #define E1000_DEV_ID_I350_FIBER 0x1522
64 #define E1000_DEV_ID_I350_SERDES 0x1523
65 #define E1000_DEV_ID_I350_SGMII 0x1524
67 #define E1000_REVISION_2 2
68 #define E1000_REVISION_4 4
70 #define E1000_FUNC_0 0
71 #define E1000_FUNC_1 1
72 #define E1000_FUNC_2 2
73 #define E1000_FUNC_3 3
75 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
76 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
77 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
78 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
86 e1000_num_macs
/* List is 1-based, so subtract 1 for true count. */
89 enum e1000_media_type
{
90 e1000_media_type_unknown
= 0,
91 e1000_media_type_copper
= 1,
92 e1000_media_type_internal_serdes
= 2,
97 e1000_nvm_unknown
= 0,
104 enum e1000_nvm_override
{
105 e1000_nvm_override_none
= 0,
106 e1000_nvm_override_spi_small
,
107 e1000_nvm_override_spi_large
,
110 enum e1000_phy_type
{
111 e1000_phy_unknown
= 0,
122 enum e1000_bus_type
{
123 e1000_bus_type_unknown
= 0,
126 e1000_bus_type_pci_express
,
127 e1000_bus_type_reserved
130 enum e1000_bus_speed
{
131 e1000_bus_speed_unknown
= 0,
137 e1000_bus_speed_2500
,
138 e1000_bus_speed_5000
,
139 e1000_bus_speed_reserved
142 enum e1000_bus_width
{
143 e1000_bus_width_unknown
= 0,
144 e1000_bus_width_pcie_x1
,
145 e1000_bus_width_pcie_x2
,
146 e1000_bus_width_pcie_x4
= 4,
147 e1000_bus_width_pcie_x8
= 8,
150 e1000_bus_width_reserved
153 enum e1000_1000t_rx_status
{
154 e1000_1000t_rx_status_not_ok
= 0,
155 e1000_1000t_rx_status_ok
,
156 e1000_1000t_rx_status_undefined
= 0xFF
159 enum e1000_rev_polarity
{
160 e1000_rev_polarity_normal
= 0,
161 e1000_rev_polarity_reversed
,
162 e1000_rev_polarity_undefined
= 0xFF
170 e1000_fc_default
= 0xFF
173 /* Statistics counters collected by the MAC */
174 struct e1000_hw_stats
{
257 struct e1000_phy_stats
{
262 struct e1000_host_mng_dhcp_cookie
{
273 /* Host Interface "Rev 1" */
274 struct e1000_host_command_header
{
281 #define E1000_HI_MAX_DATA_LENGTH 252
282 struct e1000_host_command_info
{
283 struct e1000_host_command_header command_header
;
284 u8 command_data
[E1000_HI_MAX_DATA_LENGTH
];
287 /* Host Interface "Rev 2" */
288 struct e1000_host_mng_command_header
{
296 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
297 struct e1000_host_mng_command_info
{
298 struct e1000_host_mng_command_header command_header
;
299 u8 command_data
[E1000_HI_MAX_MNG_DATA_LENGTH
];
302 #include "e1000_mac.h"
303 #include "e1000_phy.h"
304 #include "e1000_nvm.h"
305 #include "e1000_mbx.h"
307 struct e1000_mac_operations
{
308 s32 (*check_for_link
)(struct e1000_hw
*);
309 s32 (*reset_hw
)(struct e1000_hw
*);
310 s32 (*init_hw
)(struct e1000_hw
*);
311 bool (*check_mng_mode
)(struct e1000_hw
*);
312 s32 (*setup_physical_interface
)(struct e1000_hw
*);
313 void (*rar_set
)(struct e1000_hw
*, u8
*, u32
);
314 s32 (*read_mac_addr
)(struct e1000_hw
*);
315 s32 (*get_speed_and_duplex
)(struct e1000_hw
*, u16
*, u16
*);
318 struct e1000_phy_operations
{
319 s32 (*acquire
)(struct e1000_hw
*);
320 s32 (*check_polarity
)(struct e1000_hw
*);
321 s32 (*check_reset_block
)(struct e1000_hw
*);
322 s32 (*force_speed_duplex
)(struct e1000_hw
*);
323 s32 (*get_cfg_done
)(struct e1000_hw
*hw
);
324 s32 (*get_cable_length
)(struct e1000_hw
*);
325 s32 (*get_phy_info
)(struct e1000_hw
*);
326 s32 (*read_reg
)(struct e1000_hw
*, u32
, u16
*);
327 void (*release
)(struct e1000_hw
*);
328 s32 (*reset
)(struct e1000_hw
*);
329 s32 (*set_d0_lplu_state
)(struct e1000_hw
*, bool);
330 s32 (*set_d3_lplu_state
)(struct e1000_hw
*, bool);
331 s32 (*write_reg
)(struct e1000_hw
*, u32
, u16
);
334 struct e1000_nvm_operations
{
335 s32 (*acquire
)(struct e1000_hw
*);
336 s32 (*read
)(struct e1000_hw
*, u16
, u16
, u16
*);
337 void (*release
)(struct e1000_hw
*);
338 s32 (*write
)(struct e1000_hw
*, u16
, u16
, u16
*);
339 s32 (*update
)(struct e1000_hw
*);
340 s32 (*validate
)(struct e1000_hw
*);
344 s32 (*get_invariants
)(struct e1000_hw
*);
345 struct e1000_mac_operations
*mac_ops
;
346 struct e1000_phy_operations
*phy_ops
;
347 struct e1000_nvm_operations
*nvm_ops
;
350 extern const struct e1000_info e1000_82575_info
;
352 struct e1000_mac_info
{
353 struct e1000_mac_operations ops
;
358 enum e1000_mac_type type
;
369 /* Maximum size of the MTA register table in all supported adapters */
370 #define MAX_MTA_REG 128
371 u32 mta_shadow
[MAX_MTA_REG
];
374 u8 forced_speed_duplex
;
377 bool arc_subsystem_valid
;
378 bool asf_firmware_present
;
381 bool disable_hw_init_bits
;
382 bool get_link_status
;
383 bool ifs_params_forced
;
385 bool report_tx_early
;
386 bool serdes_has_link
;
387 bool tx_pkt_filtering
;
390 struct e1000_phy_info
{
391 struct e1000_phy_operations ops
;
393 enum e1000_phy_type type
;
395 enum e1000_1000t_rx_status local_rx
;
396 enum e1000_1000t_rx_status remote_rx
;
397 enum e1000_ms_type ms_type
;
398 enum e1000_ms_type original_ms_type
;
399 enum e1000_rev_polarity cable_polarity
;
400 enum e1000_smart_speed smart_speed
;
404 u32 reset_delay_us
; /* in usec */
407 enum e1000_media_type media_type
;
409 u16 autoneg_advertised
;
412 u16 max_cable_length
;
413 u16 min_cable_length
;
417 bool disable_polarity_correction
;
419 bool polarity_correction
;
421 bool speed_downgraded
;
422 bool autoneg_wait_to_complete
;
425 struct e1000_nvm_info
{
426 struct e1000_nvm_operations ops
;
427 enum e1000_nvm_type type
;
428 enum e1000_nvm_override override
;
440 struct e1000_bus_info
{
441 enum e1000_bus_type type
;
442 enum e1000_bus_speed speed
;
443 enum e1000_bus_width width
;
451 struct e1000_fc_info
{
452 u32 high_water
; /* Flow control high-water mark */
453 u32 low_water
; /* Flow control low-water mark */
454 u16 pause_time
; /* Flow control pause timer */
455 bool send_xon
; /* Flow control send XON */
456 bool strict_ieee
; /* Strict IEEE mode */
457 enum e1000_fc_mode current_mode
; /* Type of flow control */
458 enum e1000_fc_mode requested_mode
;
461 struct e1000_mbx_operations
{
462 s32 (*init_params
)(struct e1000_hw
*hw
);
463 s32 (*read
)(struct e1000_hw
*, u32
*, u16
, u16
);
464 s32 (*write
)(struct e1000_hw
*, u32
*, u16
, u16
);
465 s32 (*read_posted
)(struct e1000_hw
*, u32
*, u16
, u16
);
466 s32 (*write_posted
)(struct e1000_hw
*, u32
*, u16
, u16
);
467 s32 (*check_for_msg
)(struct e1000_hw
*, u16
);
468 s32 (*check_for_ack
)(struct e1000_hw
*, u16
);
469 s32 (*check_for_rst
)(struct e1000_hw
*, u16
);
472 struct e1000_mbx_stats
{
481 struct e1000_mbx_info
{
482 struct e1000_mbx_operations ops
;
483 struct e1000_mbx_stats stats
;
489 struct e1000_dev_spec_82575
{
491 bool global_device_reset
;
499 u8 __iomem
*flash_address
;
500 unsigned long io_base
;
502 struct e1000_mac_info mac
;
503 struct e1000_fc_info fc
;
504 struct e1000_phy_info phy
;
505 struct e1000_nvm_info nvm
;
506 struct e1000_bus_info bus
;
507 struct e1000_mbx_info mbx
;
508 struct e1000_host_mng_dhcp_cookie mng_cookie
;
511 struct e1000_dev_spec_82575 _82575
;
515 u16 subsystem_vendor_id
;
516 u16 subsystem_device_id
;
522 extern struct net_device
*igb_get_hw_dev(struct e1000_hw
*hw
);
523 #define hw_dbg(format, arg...) \
524 netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
526 /* These functions must be implemented by drivers */
527 s32
igb_read_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
);
528 s32
igb_write_pcie_cap_reg(struct e1000_hw
*hw
, u32 reg
, u16
*value
);
529 #endif /* _E1000_HW_H_ */