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net: add skb_dst_force() in sock_queue_err_skb()
[linux/fpc-iii.git] / drivers / net / sfc / qt202x_phy.c
blob55f90924247e270f9ec83fdfaef0321834e9bc67
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2006-2010 Solarflare Communications Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
8 */
9 /*
10 * Driver for AMCC QT202x SFP+ and XFP adapters; see www.amcc.com for details
11 */
12
13 #include <linux/slab.h>
14 #include <linux/timer.h>
15 #include <linux/delay.h>
16 #include "efx.h"
17 #include "mdio_10g.h"
18 #include "phy.h"
19 #include "nic.h"
20
21 #define QT202X_REQUIRED_DEVS (MDIO_DEVS_PCS | \
22 MDIO_DEVS_PMAPMD | \
23 MDIO_DEVS_PHYXS)
24
25 #define QT202X_LOOPBACKS ((1 << LOOPBACK_PCS) | \
26 (1 << LOOPBACK_PMAPMD) | \
27 (1 << LOOPBACK_PHYXS_WS))
28
29 /****************************************************************************/
30 /* Quake-specific MDIO registers */
31 #define MDIO_QUAKE_LED0_REG (0xD006)
32
33 /* QT2025C only */
34 #define PCS_FW_HEARTBEAT_REG 0xd7ee
35 #define PCS_FW_HEARTB_LBN 0
36 #define PCS_FW_HEARTB_WIDTH 8
37 #define PCS_FW_PRODUCT_CODE_1 0xd7f0
38 #define PCS_FW_VERSION_1 0xd7f3
39 #define PCS_FW_BUILD_1 0xd7f6
40 #define PCS_UC8051_STATUS_REG 0xd7fd
41 #define PCS_UC_STATUS_LBN 0
42 #define PCS_UC_STATUS_WIDTH 8
43 #define PCS_UC_STATUS_FW_SAVE 0x20
44 #define PMA_PMD_MODE_REG 0xc301
45 #define PMA_PMD_RXIN_SEL_LBN 6
46 #define PMA_PMD_FTX_CTRL2_REG 0xc309
47 #define PMA_PMD_FTX_STATIC_LBN 13
48 #define PMA_PMD_VEND1_REG 0xc001
49 #define PMA_PMD_VEND1_LBTXD_LBN 15
50 #define PCS_VEND1_REG 0xc000
51 #define PCS_VEND1_LBTXD_LBN 5
52
53 void falcon_qt202x_set_led(struct efx_nic *p, int led, int mode)
54 {
55 int addr = MDIO_QUAKE_LED0_REG + led;
56 efx_mdio_write(p, MDIO_MMD_PMAPMD, addr, mode);
57 }
58
59 struct qt202x_phy_data {
60 enum efx_phy_mode phy_mode;
61 bool bug17190_in_bad_state;
62 unsigned long bug17190_timer;
63 u32 firmware_ver;
64 };
65
66 #define QT2022C2_MAX_RESET_TIME 500
67 #define QT2022C2_RESET_WAIT 10
68
69 #define QT2025C_MAX_HEARTB_TIME (5 * HZ)
70 #define QT2025C_HEARTB_WAIT 100
71 #define QT2025C_MAX_FWSTART_TIME (25 * HZ / 10)
72 #define QT2025C_FWSTART_WAIT 100
73
74 #define BUG17190_INTERVAL (2 * HZ)
75
76 static int qt2025c_wait_heartbeat(struct efx_nic *efx)
77 {
78 unsigned long timeout = jiffies + QT2025C_MAX_HEARTB_TIME;
79 int reg, old_counter = 0;
80
81 /* Wait for firmware heartbeat to start */
82 for (;;) {
83 int counter;
84 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_FW_HEARTBEAT_REG);
85 if (reg < 0)
86 return reg;
87 counter = ((reg >> PCS_FW_HEARTB_LBN) &
88 ((1 << PCS_FW_HEARTB_WIDTH) - 1));
89 if (old_counter == 0)
90 old_counter = counter;
91 else if (counter != old_counter)
92 break;
93 if (time_after(jiffies, timeout)) {
94 /* Some cables have EEPROMs that conflict with the
95 * PHY's on-board EEPROM so it cannot load firmware */
96 netif_err(efx, hw, efx->net_dev,
97 "If an SFP+ direct attach cable is"
98 " connected, please check that it complies"
99 " with the SFP+ specification\n");
100 return -ETIMEDOUT;
101 }
102 msleep(QT2025C_HEARTB_WAIT);
103 }
104
105 return 0;
106 }
107
108 static int qt2025c_wait_fw_status_good(struct efx_nic *efx)
109 {
110 unsigned long timeout = jiffies + QT2025C_MAX_FWSTART_TIME;
111 int reg;
112
113 /* Wait for firmware status to look good */
114 for (;;) {
115 reg = efx_mdio_read(efx, MDIO_MMD_PCS, PCS_UC8051_STATUS_REG);
116 if (reg < 0)
117 return reg;
118 if ((reg &
119 ((1 << PCS_UC_STATUS_WIDTH) - 1) << PCS_UC_STATUS_LBN) >=
120 PCS_UC_STATUS_FW_SAVE)
121 break;
122 if (time_after(jiffies, timeout))
123 return -ETIMEDOUT;
124 msleep(QT2025C_FWSTART_WAIT);
125 }
126
127 return 0;
128 }
129
130 static void qt2025c_restart_firmware(struct efx_nic *efx)
131 {
132 /* Restart microcontroller execution of firmware from RAM */
133 efx_mdio_write(efx, 3, 0xe854, 0x00c0);
134 efx_mdio_write(efx, 3, 0xe854, 0x0040);
135 msleep(50);
136 }
137
138 static int qt2025c_wait_reset(struct efx_nic *efx)
139 {
140 int rc;
141
142 rc = qt2025c_wait_heartbeat(efx);
143 if (rc != 0)
144 return rc;
145
146 rc = qt2025c_wait_fw_status_good(efx);
147 if (rc == -ETIMEDOUT) {
148 /* Bug 17689: occasionally heartbeat starts but firmware status
149 * code never progresses beyond 0x00. Try again, once, after
150 * restarting execution of the firmware image. */
151 netif_dbg(efx, hw, efx->net_dev,
152 "bashing QT2025C microcontroller\n");
153 qt2025c_restart_firmware(efx);
154 rc = qt2025c_wait_heartbeat(efx);
155 if (rc != 0)
156 return rc;
157 rc = qt2025c_wait_fw_status_good(efx);
158 }
159
160 return rc;
161 }
162
163 static void qt2025c_firmware_id(struct efx_nic *efx)
164 {
165 struct qt202x_phy_data *phy_data = efx->phy_data;
166 u8 firmware_id[9];
167 size_t i;
168
169 for (i = 0; i < sizeof(firmware_id); i++)
170 firmware_id[i] = efx_mdio_read(efx, MDIO_MMD_PCS,
171 PCS_FW_PRODUCT_CODE_1 + i);
172 netif_info(efx, probe, efx->net_dev,
173 "QT2025C firmware %xr%d v%d.%d.%d.%d [20%02d-%02d-%02d]\n",
174 (firmware_id[0] << 8) | firmware_id[1], firmware_id[2],
175 firmware_id[3] >> 4, firmware_id[3] & 0xf,
176 firmware_id[4], firmware_id[5],
177 firmware_id[6], firmware_id[7], firmware_id[8]);
178 phy_data->firmware_ver = ((firmware_id[3] & 0xf0) << 20) |
179 ((firmware_id[3] & 0x0f) << 16) |
180 (firmware_id[4] << 8) | firmware_id[5];
181 }
182
183 static void qt2025c_bug17190_workaround(struct efx_nic *efx)
184 {
185 struct qt202x_phy_data *phy_data = efx->phy_data;
186
187 /* The PHY can get stuck in a state where it reports PHY_XS and PMA/PMD
188 * layers up, but PCS down (no block_lock). If we notice this state
189 * persisting for a couple of seconds, we switch PMA/PMD loopback
190 * briefly on and then off again, which is normally sufficient to
191 * recover it.
192 */
193 if (efx->link_state.up ||
194 !efx_mdio_links_ok(efx, MDIO_DEVS_PMAPMD | MDIO_DEVS_PHYXS)) {
195 phy_data->bug17190_in_bad_state = false;
196 return;
197 }
198
199 if (!phy_data->bug17190_in_bad_state) {
200 phy_data->bug17190_in_bad_state = true;
201 phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
202 return;
203 }
204
205 if (time_after_eq(jiffies, phy_data->bug17190_timer)) {
206 netif_dbg(efx, hw, efx->net_dev, "bashing QT2025C PMA/PMD\n");
207 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
208 MDIO_PMA_CTRL1_LOOPBACK, true);
209 msleep(100);
210 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_CTRL1,
211 MDIO_PMA_CTRL1_LOOPBACK, false);
212 phy_data->bug17190_timer = jiffies + BUG17190_INTERVAL;
213 }
214 }
215
216 static int qt2025c_select_phy_mode(struct efx_nic *efx)
217 {
218 struct qt202x_phy_data *phy_data = efx->phy_data;
219 struct falcon_board *board = falcon_board(efx);
220 int reg, rc, i;
221 uint16_t phy_op_mode;
222
223 /* Only 2.0.1.0+ PHY firmware supports the more optimal SFP+
224 * Self-Configure mode. Don't attempt any switching if we encounter
225 * older firmware. */
226 if (phy_data->firmware_ver < 0x02000100)
227 return 0;
228
229 /* In general we will get optimal behaviour in "SFP+ Self-Configure"
230 * mode; however, that powers down most of the PHY when no module is
231 * present, so we must use a different mode (any fixed mode will do)
232 * to be sure that loopbacks will work. */
233 phy_op_mode = (efx->loopback_mode == LOOPBACK_NONE) ? 0x0038 : 0x0020;
234
235 /* Only change mode if really necessary */
236 reg = efx_mdio_read(efx, 1, 0xc319);
237 if ((reg & 0x0038) == phy_op_mode)
238 return 0;
239 netif_dbg(efx, hw, efx->net_dev, "Switching PHY to mode 0x%04x\n",
240 phy_op_mode);
241
242 /* This sequence replicates the register writes configured in the boot
243 * EEPROM (including the differences between board revisions), except
244 * that the operating mode is changed, and the PHY is prevented from
245 * unnecessarily reloading the main firmware image again. */
246 efx_mdio_write(efx, 1, 0xc300, 0x0000);
247 /* (Note: this portion of the boot EEPROM sequence, which bit-bashes 9
248 * STOPs onto the firmware/module I2C bus to reset it, varies across
249 * board revisions, as the bus is connected to different GPIO/LED
250 * outputs on the PHY.) */
251 if (board->major == 0 && board->minor < 2) {
252 efx_mdio_write(efx, 1, 0xc303, 0x4498);
253 for (i = 0; i < 9; i++) {
254 efx_mdio_write(efx, 1, 0xc303, 0x4488);
255 efx_mdio_write(efx, 1, 0xc303, 0x4480);
256 efx_mdio_write(efx, 1, 0xc303, 0x4490);
257 efx_mdio_write(efx, 1, 0xc303, 0x4498);
258 }
259 } else {
260 efx_mdio_write(efx, 1, 0xc303, 0x0920);
261 efx_mdio_write(efx, 1, 0xd008, 0x0004);
262 for (i = 0; i < 9; i++) {
263 efx_mdio_write(efx, 1, 0xc303, 0x0900);
264 efx_mdio_write(efx, 1, 0xd008, 0x0005);
265 efx_mdio_write(efx, 1, 0xc303, 0x0920);
266 efx_mdio_write(efx, 1, 0xd008, 0x0004);
267 }
268 efx_mdio_write(efx, 1, 0xc303, 0x4900);
269 }
270 efx_mdio_write(efx, 1, 0xc303, 0x4900);
271 efx_mdio_write(efx, 1, 0xc302, 0x0004);
272 efx_mdio_write(efx, 1, 0xc316, 0x0013);
273 efx_mdio_write(efx, 1, 0xc318, 0x0054);
274 efx_mdio_write(efx, 1, 0xc319, phy_op_mode);
275 efx_mdio_write(efx, 1, 0xc31a, 0x0098);
276 efx_mdio_write(efx, 3, 0x0026, 0x0e00);
277 efx_mdio_write(efx, 3, 0x0027, 0x0013);
278 efx_mdio_write(efx, 3, 0x0028, 0xa528);
279 efx_mdio_write(efx, 1, 0xd006, 0x000a);
280 efx_mdio_write(efx, 1, 0xd007, 0x0009);
281 efx_mdio_write(efx, 1, 0xd008, 0x0004);
282 /* This additional write is not present in the boot EEPROM. It
283 * prevents the PHY's internal boot ROM doing another pointless (and
284 * slow) reload of the firmware image (the microcontroller's code
285 * memory is not affected by the microcontroller reset). */
286 efx_mdio_write(efx, 1, 0xc317, 0x00ff);
287 /* PMA/PMD loopback sets RXIN to inverse polarity and the firmware
288 * restart doesn't reset it. We need to do that ourselves. */
289 efx_mdio_set_flag(efx, 1, PMA_PMD_MODE_REG,
290 1 << PMA_PMD_RXIN_SEL_LBN, false);
291 efx_mdio_write(efx, 1, 0xc300, 0x0002);
292 msleep(20);
293
294 /* Restart microcontroller execution of firmware from RAM */
295 qt2025c_restart_firmware(efx);
296
297 /* Wait for the microcontroller to be ready again */
298 rc = qt2025c_wait_reset(efx);
299 if (rc < 0) {
300 netif_err(efx, hw, efx->net_dev,
301 "PHY microcontroller reset during mode switch "
302 "timed out\n");
303 return rc;
304 }
305
306 return 0;
307 }
308
309 static int qt202x_reset_phy(struct efx_nic *efx)
310 {
311 int rc;
312
313 if (efx->phy_type == PHY_TYPE_QT2025C) {
314 /* Wait for the reset triggered by falcon_reset_hw()
315 * to complete */
316 rc = qt2025c_wait_reset(efx);
317 if (rc < 0)
318 goto fail;
319 } else {
320 /* Reset the PHYXS MMD. This is documented as doing
321 * a complete soft reset. */
322 rc = efx_mdio_reset_mmd(efx, MDIO_MMD_PHYXS,
323 QT2022C2_MAX_RESET_TIME /
324 QT2022C2_RESET_WAIT,
325 QT2022C2_RESET_WAIT);
326 if (rc < 0)
327 goto fail;
328 }
329
330 /* Wait 250ms for the PHY to complete bootup */
331 msleep(250);
332
333 falcon_board(efx)->type->init_phy(efx);
334
335 return 0;
336
337 fail:
338 netif_err(efx, hw, efx->net_dev, "PHY reset timed out\n");
339 return rc;
340 }
341
342 static int qt202x_phy_probe(struct efx_nic *efx)
343 {
344 struct qt202x_phy_data *phy_data;
345
346 phy_data = kzalloc(sizeof(struct qt202x_phy_data), GFP_KERNEL);
347 if (!phy_data)
348 return -ENOMEM;
349 efx->phy_data = phy_data;
350 phy_data->phy_mode = efx->phy_mode;
351 phy_data->bug17190_in_bad_state = false;
352 phy_data->bug17190_timer = 0;
353
354 efx->mdio.mmds = QT202X_REQUIRED_DEVS;
355 efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
356 efx->loopback_modes = QT202X_LOOPBACKS | FALCON_XMAC_LOOPBACKS;
357 return 0;
358 }
359
360 static int qt202x_phy_init(struct efx_nic *efx)
361 {
362 u32 devid;
363 int rc;
364
365 rc = qt202x_reset_phy(efx);
366 if (rc) {
367 netif_err(efx, probe, efx->net_dev, "PHY init failed\n");
368 return rc;
369 }
370
371 devid = efx_mdio_read_id(efx, MDIO_MMD_PHYXS);
372 netif_info(efx, probe, efx->net_dev,
373 "PHY ID reg %x (OUI %06x model %02x revision %x)\n",
374 devid, efx_mdio_id_oui(devid), efx_mdio_id_model(devid),
375 efx_mdio_id_rev(devid));
376
377 if (efx->phy_type == PHY_TYPE_QT2025C)
378 qt2025c_firmware_id(efx);
379
380 return 0;
381 }
382
383 static int qt202x_link_ok(struct efx_nic *efx)
384 {
385 return efx_mdio_links_ok(efx, QT202X_REQUIRED_DEVS);
386 }
387
388 static bool qt202x_phy_poll(struct efx_nic *efx)
389 {
390 bool was_up = efx->link_state.up;
391
392 efx->link_state.up = qt202x_link_ok(efx);
393 efx->link_state.speed = 10000;
394 efx->link_state.fd = true;
395 efx->link_state.fc = efx->wanted_fc;
396
397 if (efx->phy_type == PHY_TYPE_QT2025C)
398 qt2025c_bug17190_workaround(efx);
399
400 return efx->link_state.up != was_up;
401 }
402
403 static int qt202x_phy_reconfigure(struct efx_nic *efx)
404 {
405 struct qt202x_phy_data *phy_data = efx->phy_data;
406
407 if (efx->phy_type == PHY_TYPE_QT2025C) {
408 int rc = qt2025c_select_phy_mode(efx);
409 if (rc)
410 return rc;
411
412 /* There are several different register bits which can
413 * disable TX (and save power) on direct-attach cables
414 * or optical transceivers, varying somewhat between
415 * firmware versions. Only 'static mode' appears to
416 * cover everything. */
417 mdio_set_flag(
418 &efx->mdio, efx->mdio.prtad, MDIO_MMD_PMAPMD,
419 PMA_PMD_FTX_CTRL2_REG, 1 << PMA_PMD_FTX_STATIC_LBN,
420 efx->phy_mode & PHY_MODE_TX_DISABLED ||
421 efx->phy_mode & PHY_MODE_LOW_POWER ||
422 efx->loopback_mode == LOOPBACK_PCS ||
423 efx->loopback_mode == LOOPBACK_PMAPMD);
424 } else {
425 /* Reset the PHY when moving from tx off to tx on */
426 if (!(efx->phy_mode & PHY_MODE_TX_DISABLED) &&
427 (phy_data->phy_mode & PHY_MODE_TX_DISABLED))
428 qt202x_reset_phy(efx);
429
430 efx_mdio_transmit_disable(efx);
431 }
432
433 efx_mdio_phy_reconfigure(efx);
434
435 phy_data->phy_mode = efx->phy_mode;
436
437 return 0;
438 }
439
440 static void qt202x_phy_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
441 {
442 mdio45_ethtool_gset(&efx->mdio, ecmd);
443 }
444
445 static void qt202x_phy_remove(struct efx_nic *efx)
446 {
447 /* Free the context block */
448 kfree(efx->phy_data);
449 efx->phy_data = NULL;
450 }
451
452 struct efx_phy_operations falcon_qt202x_phy_ops = {
453 .probe = qt202x_phy_probe,
454 .init = qt202x_phy_init,
455 .reconfigure = qt202x_phy_reconfigure,
456 .poll = qt202x_phy_poll,
457 .fini = efx_port_dummy_op_void,
458 .remove = qt202x_phy_remove,
459 .get_settings = qt202x_phy_get_settings,
460 .set_settings = efx_mdio_set_settings,
461 .test_alive = efx_mdio_test_alive,
462 };
Linux with added FPC-III support