arch/m68k/include/asm/m520xsim.h

   1 /****************************************************************************/
   2
   3 /*
   4  *  m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
   5  *
   6  *  (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
   7  */
   8
   9 /****************************************************************************/
  10 #ifndef m520xsim_h
  11 #define m520xsim_h
  12 /****************************************************************************/
  13
  14 #define CPU_NAME                "COLDFIRE(m520x)"
  15 #define CPU_INSTR_PER_JIFFY     3
  16 #define MCF_BUSCLK              (MCF_CLK / 2)
  17
  18 #include <asm/m52xxacr.h>
  19
  20 /*
  21  *  Define the 520x SIM register set addresses.
  22  */
  23 #define MCFICM_INTC0        0xFC048000  /* Base for Interrupt Ctrl 0 */
  24 #define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
  25 #define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
  26 #define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
  27 #define MCFINTC_IMRL        0x0c        /* Interrupt mask 1-31 */
  28 #define MCFINTC_INTFRCH     0x10        /* Interrupt force 32-63 */
  29 #define MCFINTC_INTFRCL     0x14        /* Interrupt force 1-31 */
  30 #define MCFINTC_SIMR        0x1c        /* Set interrupt mask 0-63 */
  31 #define MCFINTC_CIMR        0x1d        /* Clear interrupt mask 0-63 */
  32 #define MCFINTC_ICR0        0x40        /* Base ICR register */
  33
  34 /*
  35  *  The common interrupt controller code just wants to know the absolute
  36  *  address to the SIMR and CIMR registers (not offsets into IPSBAR).
  37  *  The 520x family only has a single INTC unit.
  38  */
  39 #define MCFINTC0_SIMR       (MCFICM_INTC0 + MCFINTC_SIMR)
  40 #define MCFINTC0_CIMR       (MCFICM_INTC0 + MCFINTC_CIMR)
  41 #define MCFINTC0_ICR0       (MCFICM_INTC0 + MCFINTC_ICR0)
  42 #define MCFINTC1_SIMR       (0)
  43 #define MCFINTC1_CIMR       (0)
  44 #define MCFINTC1_ICR0       (0)
  45 #define MCFINTC2_SIMR       (0)
  46 #define MCFINTC2_CIMR       (0)
  47 #define MCFINTC2_ICR0       (0)
  48
  49 #define MCFINT_VECBASE      64
  50 #define MCFINT_UART0        26          /* Interrupt number for UART0 */
  51 #define MCFINT_UART1        27          /* Interrupt number for UART1 */
  52 #define MCFINT_UART2        28          /* Interrupt number for UART2 */
  53 #define MCFINT_QSPI         31          /* Interrupt number for QSPI */
  54 #define MCFINT_FECRX0       36          /* Interrupt number for FEC RX */
  55 #define MCFINT_FECTX0       40          /* Interrupt number for FEC RX */
  56 #define MCFINT_FECENTC0     42          /* Interrupt number for FEC RX */
  57 #define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */
  58
  59 #define MCF_IRQ_UART0       (MCFINT_VECBASE + MCFINT_UART0)
  60 #define MCF_IRQ_UART1       (MCFINT_VECBASE + MCFINT_UART1)
  61 #define MCF_IRQ_UART2       (MCFINT_VECBASE + MCFINT_UART2)
  62
  63 #define MCF_IRQ_FECRX0      (MCFINT_VECBASE + MCFINT_FECRX0)
  64 #define MCF_IRQ_FECTX0      (MCFINT_VECBASE + MCFINT_FECTX0)
  65 #define MCF_IRQ_FECENTC0    (MCFINT_VECBASE + MCFINT_FECENTC0)
  66
  67 #define MCF_IRQ_QSPI        (MCFINT_VECBASE + MCFINT_QSPI)
  68 #define MCF_IRQ_PIT1        (MCFINT_VECBASE + MCFINT_PIT1)
  69
  70 /*
  71  *  SDRAM configuration registers.
  72  */
  73 #define MCFSIM_SDMR         0xFC0a8000  /* SDRAM Mode/Extended Mode Register */
  74 #define MCFSIM_SDCR         0xFC0a8004  /* SDRAM Control Register */
  75 #define MCFSIM_SDCFG1       0xFC0a8008  /* SDRAM Configuration Register 1 */
  76 #define MCFSIM_SDCFG2       0xFC0a800c  /* SDRAM Configuration Register 2 */
  77 #define MCFSIM_SDCS0        0xFC0a8110  /* SDRAM Chip Select 0 Configuration */
  78 #define MCFSIM_SDCS1        0xFC0a8114  /* SDRAM Chip Select 1 Configuration */
  79
  80 /*
  81  * EPORT and GPIO registers.
  82  */
  83 #define MCFEPORT_EPPAR                  0xFC088000
  84 #define MCFEPORT_EPDDR                  0xFC088002
  85 #define MCFEPORT_EPIER                  0xFC088003
  86 #define MCFEPORT_EPDR                   0xFC088004
  87 #define MCFEPORT_EPPDR                  0xFC088005
  88 #define MCFEPORT_EPFR                   0xFC088006
  89
  90 #define MCFGPIO_PODR_BUSCTL             0xFC0A4000
  91 #define MCFGPIO_PODR_BE                 0xFC0A4001
  92 #define MCFGPIO_PODR_CS                 0xFC0A4002
  93 #define MCFGPIO_PODR_FECI2C             0xFC0A4003
  94 #define MCFGPIO_PODR_QSPI               0xFC0A4004
  95 #define MCFGPIO_PODR_TIMER              0xFC0A4005
  96 #define MCFGPIO_PODR_UART               0xFC0A4006
  97 #define MCFGPIO_PODR_FECH               0xFC0A4007
  98 #define MCFGPIO_PODR_FECL               0xFC0A4008
  99
 100 #define MCFGPIO_PDDR_BUSCTL             0xFC0A400C
 101 #define MCFGPIO_PDDR_BE                 0xFC0A400D
 102 #define MCFGPIO_PDDR_CS                 0xFC0A400E
 103 #define MCFGPIO_PDDR_FECI2C             0xFC0A400F
 104 #define MCFGPIO_PDDR_QSPI               0xFC0A4010
 105 #define MCFGPIO_PDDR_TIMER              0xFC0A4011
 106 #define MCFGPIO_PDDR_UART               0xFC0A4012
 107 #define MCFGPIO_PDDR_FECH               0xFC0A4013
 108 #define MCFGPIO_PDDR_FECL               0xFC0A4014
 109
 110 #define MCFGPIO_PPDSDR_CS               0xFC0A401A
 111 #define MCFGPIO_PPDSDR_FECI2C           0xFC0A401B
 112 #define MCFGPIO_PPDSDR_QSPI             0xFC0A401C
 113 #define MCFGPIO_PPDSDR_TIMER            0xFC0A401D
 114 #define MCFGPIO_PPDSDR_UART             0xFC0A401E
 115 #define MCFGPIO_PPDSDR_FECH             0xFC0A401F
 116 #define MCFGPIO_PPDSDR_FECL             0xFC0A4020
 117
 118 #define MCFGPIO_PCLRR_BUSCTL            0xFC0A4024
 119 #define MCFGPIO_PCLRR_BE                0xFC0A4025
 120 #define MCFGPIO_PCLRR_CS                0xFC0A4026
 121 #define MCFGPIO_PCLRR_FECI2C            0xFC0A4027
 122 #define MCFGPIO_PCLRR_QSPI              0xFC0A4028
 123 #define MCFGPIO_PCLRR_TIMER             0xFC0A4029
 124 #define MCFGPIO_PCLRR_UART              0xFC0A402A
 125 #define MCFGPIO_PCLRR_FECH              0xFC0A402B
 126 #define MCFGPIO_PCLRR_FECL              0xFC0A402C
 127
 128 /*
 129  * Generic GPIO support
 130  */
 131 #define MCFGPIO_PODR                    MCFGPIO_PODR_CS
 132 #define MCFGPIO_PDDR                    MCFGPIO_PDDR_CS
 133 #define MCFGPIO_PPDR                    MCFGPIO_PPDSDR_CS
 134 #define MCFGPIO_SETR                    MCFGPIO_PPDSDR_CS
 135 #define MCFGPIO_CLRR                    MCFGPIO_PCLRR_CS
 136
 137 #define MCFGPIO_PIN_MAX                 80
 138 #define MCFGPIO_IRQ_MAX                 8
 139 #define MCFGPIO_IRQ_VECBASE             MCFINT_VECBASE
 140
 141 #define MCF_GPIO_PAR_UART               0xFC0A4036
 142 #define MCF_GPIO_PAR_FECI2C             0xFC0A4033
 143 #define MCF_GPIO_PAR_QSPI               0xFC0A4034
 144 #define MCF_GPIO_PAR_FEC                0xFC0A4038
 145
 146 #define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
 147 #define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
 148
 149 #define MCF_GPIO_PAR_UART_PAR_URXD1         (0x0040)
 150 #define MCF_GPIO_PAR_UART_PAR_UTXD1         (0x0080)
 151
 152 #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)
 153 #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
 154
 155 /*
 156  *  PIT timer module.
 157  */
 158 #define MCFPIT_BASE1            0xFC080000      /* Base address of TIMER1 */
 159 #define MCFPIT_BASE2            0xFC084000      /* Base address of TIMER2 */
 160
 161 /*
 162  *  UART module.
 163  */
 164 #define MCFUART_BASE0           0xFC060000      /* Base address of UART0 */
 165 #define MCFUART_BASE1           0xFC064000      /* Base address of UART1 */
 166 #define MCFUART_BASE2           0xFC068000      /* Base address of UART2 */
 167
 168 /*
 169  *  FEC module.
 170  */
 171 #define MCFFEC_BASE0            0xFC030000      /* Base of FEC ethernet */
 172 #define MCFFEC_SIZE0            0x800           /* Register set size */
 173
 174 /*
 175  *  QSPI module.
 176  */
 177 #define MCFQSPI_BASE            0xFC05C000      /* Base of QSPI module */
 178 #define MCFQSPI_SIZE            0x40            /* Register set size */
 179
 180 #define MCFQSPI_CS0             46
 181 #define MCFQSPI_CS1             47
 182 #define MCFQSPI_CS2             27
 183
 184 /*
 185  *  Reset Control Unit.
 186  */
 187 #define MCF_RCR                 0xFC0A0000
 188 #define MCF_RSR                 0xFC0A0001
 189
 190 #define MCF_RCR_SWRESET         0x80            /* Software reset bit */
 191 #define MCF_RCR_FRCSTOUT        0x40            /* Force external reset */
 192
 193 /*
 194  *  Power Management.
 195  */
 196 #define MCFPM_WCR               0xfc040013
 197 #define MCFPM_PPMSR0            0xfc04002c
 198 #define MCFPM_PPMCR0            0xfc04002d
 199 #define MCFPM_PPMHR0            0xfc040030
 200 #define MCFPM_PPMLR0            0xfc040034
 201 #define MCFPM_LPCR              0xfc0a0007
 202
 203 /****************************************************************************/
 204 #endif  /* m520xsim_h */