ARM: multi_v7_defconfig: Switch BCM2835 to sdhci-iproc.c for MMC
[linux/fpc-iii.git] / arch / m68k / include / asm / mcfclk.h
blobea4791e3a55759c77ac3dd4fe17b2c9b016a0983
1 /*
2 * mcfclk.h -- coldfire specific clock structure
3 */
6 #ifndef mcfclk_h
7 #define mcfclk_h
9 struct clk;
11 struct clk_ops {
12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
16 struct clk {
17 const char *name;
18 struct clk_ops *clk_ops;
19 unsigned long rate;
20 unsigned long enabled;
21 u8 slot;
24 extern struct clk *mcf_clks[];
26 #ifdef MCFPM_PPMCR0
27 extern struct clk_ops clk_ops0;
28 #ifdef MCFPM_PPMCR1
29 extern struct clk_ops clk_ops1;
30 #endif /* MCFPM_PPMCR1 */
32 #define DEFINE_CLK(clk_bank, clk_name, clk_slot, clk_rate) \
33 static struct clk __clk_##clk_bank##_##clk_slot = { \
34 .name = clk_name, \
35 .clk_ops = &clk_ops##clk_bank, \
36 .rate = clk_rate, \
37 .slot = clk_slot, \
40 void __clk_init_enabled(struct clk *);
41 void __clk_init_disabled(struct clk *);
42 #else
43 #define DEFINE_CLK(clk_ref, clk_name, clk_rate) \
44 static struct clk clk_##clk_ref = { \
45 .name = clk_name, \
46 .rate = clk_rate, \
48 #endif /* MCFPM_PPMCR0 */
50 #endif /* mcfclk_h */