2 * PCBIT-D device driver definitions
4 * Copyright (C) 1996 Universidade de Lisboa
6 * Written by Pedro Roque Marques (roque@di.fc.ul.pt)
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
15 #include <linux/workqueue.h>
17 #define MAX_PCBIT_CARDS 4
26 unsigned short callref
; /* Call Reference */
27 unsigned char proto
; /* layer2protocol */
28 unsigned char queued
; /* unacked data messages */
29 unsigned char layer2link
; /* used in TData */
30 unsigned char snum
; /* used in TData */
31 unsigned short s_refnum
;
32 unsigned short r_refnum
;
33 unsigned short fsm_state
;
34 struct timer_list fsm_timer
;
36 struct timer_list block_timer
;
42 struct msn_entry
*next
;
48 volatile unsigned char __iomem
*sh_mem
; /* RDP address */
52 unsigned int interrupt
; /* set during interrupt
57 struct msn_entry
*msn_list
; /* ISDN address list */
65 unsigned char l2_state
;
67 struct frame_buf
*read_queue
;
68 struct frame_buf
*read_frame
;
69 struct frame_buf
*write_queue
;
72 wait_queue_head_t set_running_wq
;
73 struct timer_list set_running_timer
;
75 struct timer_list error_recover_timer
;
77 struct work_struct qdelivery
;
82 volatile unsigned char __iomem
*readptr
;
83 volatile unsigned char __iomem
*writeptr
;
87 unsigned short fsize
[8]; /* sent layer2 frames size */
89 unsigned char send_seq
;
90 unsigned char rcv_seq
;
91 unsigned char unack_seq
;
97 struct pcbit_chan
*b1
;
98 struct pcbit_chan
*b2
;
101 #define STATS_TIMER (10 * HZ)
102 #define ERRTIME (HZ / 10)
105 #define MAXBUFSIZE 1534
106 #define MRU MAXBUFSIZE
108 #define STATBUF_LEN 2048
113 #endif /* __KERNEL__ */
115 /* isdn_ctrl only allows a long sized argument */
123 unsigned long l2_status
;
129 #define PCBIT_IOCTL_GETSTAT 0x01 /* layer2 status */
130 #define PCBIT_IOCTL_LWMODE 0x02 /* linear write mode */
131 #define PCBIT_IOCTL_STRLOAD 0x03 /* start load mode */
132 #define PCBIT_IOCTL_ENDLOAD 0x04 /* end load mode */
133 #define PCBIT_IOCTL_SETBYTE 0x05 /* set byte */
134 #define PCBIT_IOCTL_GETBYTE 0x06 /* get byte */
135 #define PCBIT_IOCTL_RUNNING 0x07 /* set protocol running */
136 #define PCBIT_IOCTL_WATCH188 0x08 /* set watch 188 */
137 #define PCBIT_IOCTL_PING188 0x09 /* ping 188 */
138 #define PCBIT_IOCTL_FWMODE 0x0A /* firmware write mode */
139 #define PCBIT_IOCTL_STOP 0x0B /* stop protocol */
140 #define PCBIT_IOCTL_APION 0x0C /* issue API_ON */
144 #define PCBIT_GETSTAT (PCBIT_IOCTL_GETSTAT + IIOCDRVCTL)
145 #define PCBIT_LWMODE (PCBIT_IOCTL_LWMODE + IIOCDRVCTL)
146 #define PCBIT_STRLOAD (PCBIT_IOCTL_STRLOAD + IIOCDRVCTL)
147 #define PCBIT_ENDLOAD (PCBIT_IOCTL_ENDLOAD + IIOCDRVCTL)
148 #define PCBIT_SETBYTE (PCBIT_IOCTL_SETBYTE + IIOCDRVCTL)
149 #define PCBIT_GETBYTE (PCBIT_IOCTL_GETBYTE + IIOCDRVCTL)
150 #define PCBIT_RUNNING (PCBIT_IOCTL_RUNNING + IIOCDRVCTL)
151 #define PCBIT_WATCH188 (PCBIT_IOCTL_WATCH188 + IIOCDRVCTL)
152 #define PCBIT_PING188 (PCBIT_IOCTL_PING188 + IIOCDRVCTL)
153 #define PCBIT_FWMODE (PCBIT_IOCTL_FWMODE + IIOCDRVCTL)
154 #define PCBIT_STOP (PCBIT_IOCTL_STOP + IIOCDRVCTL)
155 #define PCBIT_APION (PCBIT_IOCTL_APION + IIOCDRVCTL)
157 #define MAXSUPERLINE 3000
165 #define L2_STARTING 4
169 void pcbit_deliver(struct work_struct
*work
);
170 int pcbit_init_dev(int board
, int mem_base
, int irq
);
171 void pcbit_terminate(int board
);
172 void pcbit_l3_receive(struct pcbit_dev
*dev
, ulong msg
, struct sk_buff
*skb
,
173 ushort hdr_len
, ushort refnum
);
174 void pcbit_state_change(struct pcbit_dev
*dev
, struct pcbit_chan
*chan
,
175 unsigned short i
, unsigned short ev
, unsigned short f
);