drivers/clk/tegra/clk.h

   1         /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __TEGRA_CLK_H
  18 #define __TEGRA_CLK_H
  19
  20 #include <linux/clk-provider.h>
  21 #include <linux/clkdev.h>
  22
  23 /**
  24  * struct tegra_clk_sync_source - external clock source from codec
  25  *
  26  * @hw: handle between common and hardware-specific interfaces
  27  * @rate: input frequency from source
  28  * @max_rate: max rate allowed
  29  */
  30 struct tegra_clk_sync_source {
  31         struct          clk_hw hw;
  32         unsigned long   rate;
  33         unsigned long   max_rate;
  34 };
  35
  36 #define to_clk_sync_source(_hw)                                 \
  37         container_of(_hw, struct tegra_clk_sync_source, hw)
  38
  39 extern const struct clk_ops tegra_clk_sync_source_ops;
  40 extern int *periph_clk_enb_refcnt;
  41
  42 struct clk *tegra_clk_register_sync_source(const char *name,
  43                 unsigned long fixed_rate, unsigned long max_rate);
  44
  45 /**
  46  * struct tegra_clk_frac_div - fractional divider clock
  47  *
  48  * @hw:         handle between common and hardware-specific interfaces
  49  * @reg:        register containing divider
  50  * @flags:      hardware-specific flags
  51  * @shift:      shift to the divider bit field
  52  * @width:      width of the divider bit field
  53  * @frac_width: width of the fractional bit field
  54  * @lock:       register lock
  55  *
  56  * Flags:
  57  * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
  58  * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
  59  *      flag indicates that this divider is for fixed rate PLL.
  60  * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
  61  *      fraction bit is set. This flags indicates to calculate divider for which
  62  *      fracton bit will be zero.
  63  * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
  64  *      set when divider value is not 0. This flags indicates that the divider
  65  *      is for UART module.
  66  */
  67 struct tegra_clk_frac_div {
  68         struct clk_hw   hw;
  69         void __iomem    *reg;
  70         u8              flags;
  71         u8              shift;
  72         u8              width;
  73         u8              frac_width;
  74         spinlock_t      *lock;
  75 };
  76
  77 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
  78
  79 #define TEGRA_DIVIDER_ROUND_UP BIT(0)
  80 #define TEGRA_DIVIDER_FIXED BIT(1)
  81 #define TEGRA_DIVIDER_INT BIT(2)
  82 #define TEGRA_DIVIDER_UART BIT(3)
  83
  84 extern const struct clk_ops tegra_clk_frac_div_ops;
  85 struct clk *tegra_clk_register_divider(const char *name,
  86                 const char *parent_name, void __iomem *reg,
  87                 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
  88                 u8 frac_width, spinlock_t *lock);
  89 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
  90                                   void __iomem *reg, spinlock_t *lock);
  91
  92 /*
  93  * Tegra PLL:
  94  *
  95  * In general, there are 3 requirements for each PLL
  96  * that SW needs to be comply with.
  97  * (1) Input frequency range (REF).
  98  * (2) Comparison frequency range (CF). CF = REF/DIVM.
  99  * (3) VCO frequency range (VCO).  VCO = CF * DIVN.
 100  *
 101  * The final PLL output frequency (FO) = VCO >> DIVP.
 102  */
 103
 104 /**
 105  * struct tegra_clk_pll_freq_table - PLL frequecy table
 106  *
 107  * @input_rate:         input rate from source
 108  * @output_rate:        output rate from PLL for the input rate
 109  * @n:                  feedback divider
 110  * @m:                  input divider
 111  * @p:                  post divider
 112  * @cpcon:              charge pump current
 113  * @sdm_data:           fraction divider setting (0 = disabled)
 114  */
 115 struct tegra_clk_pll_freq_table {
 116         unsigned long   input_rate;
 117         unsigned long   output_rate;
 118         u32             n;
 119         u32             m;
 120         u8              p;
 121         u8              cpcon;
 122         u16             sdm_data;
 123 };
 124
 125 /**
 126  * struct pdiv_map - map post divider to hw value
 127  *
 128  * @pdiv:               post divider
 129  * @hw_val:             value to be written to the PLL hw
 130  */
 131 struct pdiv_map {
 132         u8 pdiv;
 133         u8 hw_val;
 134 };
 135
 136 /**
 137  * struct div_nmp - offset and width of m,n and p fields
 138  *
 139  * @divn_shift: shift to the feedback divider bit field
 140  * @divn_width: width of the feedback divider bit field
 141  * @divm_shift: shift to the input divider bit field
 142  * @divm_width: width of the input divider bit field
 143  * @divp_shift: shift to the post divider bit field
 144  * @divp_width: width of the post divider bit field
 145  * @override_divn_shift: shift to the feedback divider bitfield in override reg
 146  * @override_divm_shift: shift to the input divider bitfield in override reg
 147  * @override_divp_shift: shift to the post divider bitfield in override reg
 148  */
 149 struct div_nmp {
 150         u8              divn_shift;
 151         u8              divn_width;
 152         u8              divm_shift;
 153         u8              divm_width;
 154         u8              divp_shift;
 155         u8              divp_width;
 156         u8              override_divn_shift;
 157         u8              override_divm_shift;
 158         u8              override_divp_shift;
 159 };
 160
 161 #define MAX_PLL_MISC_REG_COUNT  6
 162
 163 struct tegra_clk_pll;
 164
 165 /**
 166  * struct tegra_clk_pll_params - PLL parameters
 167  *
 168  * @input_min:                  Minimum input frequency
 169  * @input_max:                  Maximum input frequency
 170  * @cf_min:                     Minimum comparison frequency
 171  * @cf_max:                     Maximum comparison frequency
 172  * @vco_min:                    Minimum VCO frequency
 173  * @vco_max:                    Maximum VCO frequency
 174  * @base_reg:                   PLL base reg offset
 175  * @misc_reg:                   PLL misc reg offset
 176  * @lock_reg:                   PLL lock reg offset
 177  * @lock_mask:                  Bitmask for PLL lock status
 178  * @lock_enable_bit_idx:        Bit index to enable PLL lock
 179  * @iddq_reg:                   PLL IDDQ register offset
 180  * @iddq_bit_idx:               Bit index to enable PLL IDDQ
 181  * @reset_reg:                  Register offset of where RESET bit is
 182  * @reset_bit_idx:              Shift of reset bit in reset_reg
 183  * @sdm_din_reg:                Register offset where SDM settings are
 184  * @sdm_din_mask:               Mask of SDM divider bits
 185  * @sdm_ctrl_reg:               Register offset where SDM enable is
 186  * @sdm_ctrl_en_mask:           Mask of SDM enable bit
 187  * @ssc_ctrl_reg:               Register offset where SSC settings are
 188  * @ssc_ctrl_en_mask:           Mask of SSC enable bit
 189  * @aux_reg:                    AUX register offset
 190  * @dyn_ramp_reg:               Dynamic ramp control register offset
 191  * @ext_misc_reg:               Miscellaneous control register offsets
 192  * @pmc_divnm_reg:              n, m divider PMC override register offset (PLLM)
 193  * @pmc_divp_reg:               p divider PMC override register offset (PLLM)
 194  * @flags:                      PLL flags
 195  * @stepa_shift:                Dynamic ramp step A field shift
 196  * @stepb_shift:                Dynamic ramp step B field shift
 197  * @lock_delay:                 Delay in us if PLL lock is not used
 198  * @max_p:                      maximum value for the p divider
 199  * @defaults_set:               Boolean signaling all reg defaults for PLL set.
 200  * @pdiv_tohw:                  mapping of p divider to register values
 201  * @div_nmp:                    offsets and widths on n, m and p fields
 202  * @freq_table:                 array of frequencies supported by PLL
 203  * @fixed_rate:                 PLL rate if it is fixed
 204  * @mdiv_default:               Default value for fixed mdiv for this PLL
 205  * @round_p_to_pdiv:            Callback used to round p to the closed pdiv
 206  * @set_gain:                   Callback to adjust N div for SDM enabled
 207  *                              PLL's based on fractional divider value.
 208  * @calc_rate:                  Callback used to change how out of table
 209  *                              rates (dividers and multipler) are calculated.
 210  * @adjust_vco:                 Callback to adjust the programming range of the
 211  *                              divider range (if SDM is present)
 212  * @set_defaults:               Callback which will try to initialize PLL
 213  *                              registers to sane default values. This is first
 214  *                              tried during PLL registration, but if the PLL
 215  *                              is already enabled, it will be done the first
 216  *                              time the rate is changed while the PLL is
 217  *                              disabled.
 218  * @dyn_ramp:                   Callback which can be used to define a custom
 219  *                              dynamic ramp function for a given PLL.
 220  *
 221  * Flags:
 222  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
 223  *     PLL locking. If not set it will use lock_delay value to wait.
 224  * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
 225  *     to be programmed to change output frequency of the PLL.
 226  * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
 227  *     to be programmed to change output frequency of the PLL.
 228  * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
 229  *     to be programmed to change output frequency of the PLL.
 230  * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
 231  *     that it is PLLU and invert post divider value.
 232  * TEGRA_PLLM - PLLM has additional override settings in PMC. This
 233  *     flag indicates that it is PLLM and use override settings.
 234  * TEGRA_PLL_FIXED - We are not supposed to change output frequency
 235  *     of some plls.
 236  * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
 237  * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
 238  *     base register.
 239  * TEGRA_PLL_BYPASS - PLL has bypass bit
 240  * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
 241  * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
 242  *     it may be more accurate (especially if SDM present)
 243  * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
 244  *     flag indicated that it is PLLMB.
 245  * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
 246  */
 247 struct tegra_clk_pll_params {
 248         unsigned long   input_min;
 249         unsigned long   input_max;
 250         unsigned long   cf_min;
 251         unsigned long   cf_max;
 252         unsigned long   vco_min;
 253         unsigned long   vco_max;
 254
 255         u32             base_reg;
 256         u32             misc_reg;
 257         u32             lock_reg;
 258         u32             lock_mask;
 259         u32             lock_enable_bit_idx;
 260         u32             iddq_reg;
 261         u32             iddq_bit_idx;
 262         u32             reset_reg;
 263         u32             reset_bit_idx;
 264         u32             sdm_din_reg;
 265         u32             sdm_din_mask;
 266         u32             sdm_ctrl_reg;
 267         u32             sdm_ctrl_en_mask;
 268         u32             ssc_ctrl_reg;
 269         u32             ssc_ctrl_en_mask;
 270         u32             aux_reg;
 271         u32             dyn_ramp_reg;
 272         u32             ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
 273         u32             pmc_divnm_reg;
 274         u32             pmc_divp_reg;
 275         u32             flags;
 276         int             stepa_shift;
 277         int             stepb_shift;
 278         int             lock_delay;
 279         int             max_p;
 280         bool            defaults_set;
 281         const struct pdiv_map *pdiv_tohw;
 282         struct div_nmp  *div_nmp;
 283         struct tegra_clk_pll_freq_table *freq_table;
 284         unsigned long   fixed_rate;
 285         u16             mdiv_default;
 286         u32     (*round_p_to_pdiv)(u32 p, u32 *pdiv);
 287         void    (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
 288         int     (*calc_rate)(struct clk_hw *hw,
 289                         struct tegra_clk_pll_freq_table *cfg,
 290                         unsigned long rate, unsigned long parent_rate);
 291         unsigned long   (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
 292                                 unsigned long parent_rate);
 293         void    (*set_defaults)(struct tegra_clk_pll *pll);
 294         int     (*dyn_ramp)(struct tegra_clk_pll *pll,
 295                         struct tegra_clk_pll_freq_table *cfg);
 296 };
 297
 298 #define TEGRA_PLL_USE_LOCK BIT(0)
 299 #define TEGRA_PLL_HAS_CPCON BIT(1)
 300 #define TEGRA_PLL_SET_LFCON BIT(2)
 301 #define TEGRA_PLL_SET_DCCON BIT(3)
 302 #define TEGRA_PLLU BIT(4)
 303 #define TEGRA_PLLM BIT(5)
 304 #define TEGRA_PLL_FIXED BIT(6)
 305 #define TEGRA_PLLE_CONFIGURE BIT(7)
 306 #define TEGRA_PLL_LOCK_MISC BIT(8)
 307 #define TEGRA_PLL_BYPASS BIT(9)
 308 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
 309 #define TEGRA_MDIV_NEW BIT(11)
 310 #define TEGRA_PLLMB BIT(12)
 311 #define TEGRA_PLL_VCO_OUT BIT(13)
 312
 313 /**
 314  * struct tegra_clk_pll - Tegra PLL clock
 315  *
 316  * @hw:         handle between common and hardware-specifix interfaces
 317  * @clk_base:   address of CAR controller
 318  * @pmc:        address of PMC, required to read override bits
 319  * @lock:       register lock
 320  * @params:     PLL parameters
 321  */
 322 struct tegra_clk_pll {
 323         struct clk_hw   hw;
 324         void __iomem    *clk_base;
 325         void __iomem    *pmc;
 326         spinlock_t      *lock;
 327         struct tegra_clk_pll_params     *params;
 328 };
 329
 330 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
 331
 332 /**
 333  * struct tegra_audio_clk_info - Tegra Audio Clk Information
 334  *
 335  * @name:       name for the audio pll
 336  * @pll_params: pll_params for audio pll
 337  * @clk_id:     clk_ids for the audio pll
 338  * @parent:     name of the parent of the audio pll
 339  */
 340 struct tegra_audio_clk_info {
 341         char *name;
 342         struct tegra_clk_pll_params *pll_params;
 343         int clk_id;
 344         char *parent;
 345 };
 346
 347 extern const struct clk_ops tegra_clk_pll_ops;
 348 extern const struct clk_ops tegra_clk_plle_ops;
 349 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
 350                 void __iomem *clk_base, void __iomem *pmc,
 351                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
 352                 spinlock_t *lock);
 353
 354 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
 355                 void __iomem *clk_base, void __iomem *pmc,
 356                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
 357                 spinlock_t *lock);
 358
 359 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
 360                             void __iomem *clk_base, void __iomem *pmc,
 361                             unsigned long flags,
 362                             struct tegra_clk_pll_params *pll_params,
 363                             spinlock_t *lock);
 364
 365 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
 366                            void __iomem *clk_base, void __iomem *pmc,
 367                            unsigned long flags,
 368                            struct tegra_clk_pll_params *pll_params,
 369                            spinlock_t *lock);
 370
 371 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
 372                            void __iomem *clk_base, void __iomem *pmc,
 373                            unsigned long flags,
 374                            struct tegra_clk_pll_params *pll_params,
 375                            spinlock_t *lock);
 376
 377 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
 378                            void __iomem *clk_base, void __iomem *pmc,
 379                            unsigned long flags,
 380                            struct tegra_clk_pll_params *pll_params,
 381                            spinlock_t *lock, unsigned long parent_rate);
 382
 383 struct clk *tegra_clk_register_pllre_tegra210(const char *name,
 384                            const char *parent_name, void __iomem *clk_base,
 385                            void __iomem *pmc, unsigned long flags,
 386                            struct tegra_clk_pll_params *pll_params,
 387                            spinlock_t *lock, unsigned long parent_rate);
 388
 389 struct clk *tegra_clk_register_plle_tegra114(const char *name,
 390                                 const char *parent_name,
 391                                 void __iomem *clk_base, unsigned long flags,
 392                                 struct tegra_clk_pll_params *pll_params,
 393                                 spinlock_t *lock);
 394
 395 struct clk *tegra_clk_register_plle_tegra210(const char *name,
 396                                 const char *parent_name,
 397                                 void __iomem *clk_base, unsigned long flags,
 398                                 struct tegra_clk_pll_params *pll_params,
 399                                 spinlock_t *lock);
 400
 401 struct clk *tegra_clk_register_pllc_tegra210(const char *name,
 402                                 const char *parent_name, void __iomem *clk_base,
 403                                 void __iomem *pmc, unsigned long flags,
 404                                 struct tegra_clk_pll_params *pll_params,
 405                                 spinlock_t *lock);
 406
 407 struct clk *tegra_clk_register_pllss_tegra210(const char *name,
 408                                 const char *parent_name, void __iomem *clk_base,
 409                                 unsigned long flags,
 410                                 struct tegra_clk_pll_params *pll_params,
 411                                 spinlock_t *lock);
 412
 413 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
 414                            void __iomem *clk_base, unsigned long flags,
 415                            struct tegra_clk_pll_params *pll_params,
 416                            spinlock_t *lock);
 417
 418 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
 419                            void __iomem *clk_base, void __iomem *pmc,
 420                            unsigned long flags,
 421                            struct tegra_clk_pll_params *pll_params,
 422                            spinlock_t *lock);
 423
 424 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name,
 425                                 void __iomem *clk_base, unsigned long flags,
 426                                 struct tegra_clk_pll_params *pll_params,
 427                                 spinlock_t *lock);
 428
 429 struct clk *tegra_clk_register_pllu_tegra114(const char *name,
 430                                 const char *parent_name,
 431                                 void __iomem *clk_base, unsigned long flags,
 432                                 struct tegra_clk_pll_params *pll_params,
 433                                 spinlock_t *lock);
 434
 435 struct clk *tegra_clk_register_pllu_tegra210(const char *name,
 436                                 const char *parent_name,
 437                                 void __iomem *clk_base, unsigned long flags,
 438                                 struct tegra_clk_pll_params *pll_params,
 439                                 spinlock_t *lock);
 440
 441 /**
 442  * struct tegra_clk_pll_out - PLL divider down clock
 443  *
 444  * @hw:                 handle between common and hardware-specific interfaces
 445  * @reg:                register containing the PLL divider
 446  * @enb_bit_idx:        bit to enable/disable PLL divider
 447  * @rst_bit_idx:        bit to reset PLL divider
 448  * @lock:               register lock
 449  * @flags:              hardware-specific flags
 450  */
 451 struct tegra_clk_pll_out {
 452         struct clk_hw   hw;
 453         void __iomem    *reg;
 454         u8              enb_bit_idx;
 455         u8              rst_bit_idx;
 456         spinlock_t      *lock;
 457         u8              flags;
 458 };
 459
 460 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
 461
 462 extern const struct clk_ops tegra_clk_pll_out_ops;
 463 struct clk *tegra_clk_register_pll_out(const char *name,
 464                 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
 465                 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
 466                 spinlock_t *lock);
 467
 468 /**
 469  * struct tegra_clk_periph_regs -  Registers controlling peripheral clock
 470  *
 471  * @enb_reg:            read the enable status
 472  * @enb_set_reg:        write 1 to enable clock
 473  * @enb_clr_reg:        write 1 to disable clock
 474  * @rst_reg:            read the reset status
 475  * @rst_set_reg:        write 1 to assert the reset of peripheral
 476  * @rst_clr_reg:        write 1 to deassert the reset of peripheral
 477  */
 478 struct tegra_clk_periph_regs {
 479         u32 enb_reg;
 480         u32 enb_set_reg;
 481         u32 enb_clr_reg;
 482         u32 rst_reg;
 483         u32 rst_set_reg;
 484         u32 rst_clr_reg;
 485 };
 486
 487 /**
 488  * struct tegra_clk_periph_gate - peripheral gate clock
 489  *
 490  * @magic:              magic number to validate type
 491  * @hw:                 handle between common and hardware-specific interfaces
 492  * @clk_base:           address of CAR controller
 493  * @regs:               Registers to control the peripheral
 494  * @flags:              hardware-specific flags
 495  * @clk_num:            Clock number
 496  * @enable_refcnt:      array to maintain reference count of the clock
 497  *
 498  * Flags:
 499  * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
 500  *     for this module.
 501  * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
 502  *     after clock enable and driver for the module is responsible for
 503  *     doing reset.
 504  * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
 505  *     bus to flush the write operation in apb bus. This flag indicates
 506  *     that this peripheral is in apb bus.
 507  * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
 508  */
 509 struct tegra_clk_periph_gate {
 510         u32                     magic;
 511         struct clk_hw           hw;
 512         void __iomem            *clk_base;
 513         u8                      flags;
 514         int                     clk_num;
 515         int                     *enable_refcnt;
 516         const struct tegra_clk_periph_regs *regs;
 517 };
 518
 519 #define to_clk_periph_gate(_hw)                                 \
 520         container_of(_hw, struct tegra_clk_periph_gate, hw)
 521
 522 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
 523
 524 #define TEGRA_PERIPH_NO_RESET BIT(0)
 525 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
 526 #define TEGRA_PERIPH_ON_APB BIT(2)
 527 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
 528 #define TEGRA_PERIPH_NO_DIV BIT(4)
 529 #define TEGRA_PERIPH_NO_GATE BIT(5)
 530
 531 extern const struct clk_ops tegra_clk_periph_gate_ops;
 532 struct clk *tegra_clk_register_periph_gate(const char *name,
 533                 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
 534                 unsigned long flags, int clk_num, int *enable_refcnt);
 535
 536 struct tegra_clk_periph_fixed {
 537         struct clk_hw hw;
 538         void __iomem *base;
 539         const struct tegra_clk_periph_regs *regs;
 540         unsigned int mul;
 541         unsigned int div;
 542         unsigned int num;
 543 };
 544
 545 struct clk *tegra_clk_register_periph_fixed(const char *name,
 546                                             const char *parent,
 547                                             unsigned long flags,
 548                                             void __iomem *base,
 549                                             unsigned int mul,
 550                                             unsigned int div,
 551                                             unsigned int num);
 552
 553 /**
 554  * struct clk-periph - peripheral clock
 555  *
 556  * @magic:      magic number to validate type
 557  * @hw:         handle between common and hardware-specific interfaces
 558  * @mux:        mux clock
 559  * @divider:    divider clock
 560  * @gate:       gate clock
 561  * @mux_ops:    mux clock ops
 562  * @div_ops:    divider clock ops
 563  * @gate_ops:   gate clock ops
 564  */
 565 struct tegra_clk_periph {
 566         u32                     magic;
 567         struct clk_hw           hw;
 568         struct clk_mux          mux;
 569         struct tegra_clk_frac_div       divider;
 570         struct tegra_clk_periph_gate    gate;
 571
 572         const struct clk_ops    *mux_ops;
 573         const struct clk_ops    *div_ops;
 574         const struct clk_ops    *gate_ops;
 575 };
 576
 577 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
 578
 579 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223
 580
 581 extern const struct clk_ops tegra_clk_periph_ops;
 582 struct clk *tegra_clk_register_periph(const char *name,
 583                 const char * const *parent_names, int num_parents,
 584                 struct tegra_clk_periph *periph, void __iomem *clk_base,
 585                 u32 offset, unsigned long flags);
 586 struct clk *tegra_clk_register_periph_nodiv(const char *name,
 587                 const char * const *parent_names, int num_parents,
 588                 struct tegra_clk_periph *periph, void __iomem *clk_base,
 589                 u32 offset);
 590
 591 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags,             \
 592                          _div_shift, _div_width, _div_frac_width,       \
 593                          _div_flags, _clk_num,\
 594                          _gate_flags, _table, _lock)                    \
 595         {                                                               \
 596                 .mux = {                                                \
 597                         .flags = _mux_flags,                            \
 598                         .shift = _mux_shift,                            \
 599                         .mask = _mux_mask,                              \
 600                         .table = _table,                                \
 601                         .lock = _lock,                                  \
 602                 },                                                      \
 603                 .divider = {                                            \
 604                         .flags = _div_flags,                            \
 605                         .shift = _div_shift,                            \
 606                         .width = _div_width,                            \
 607                         .frac_width = _div_frac_width,                  \
 608                         .lock = _lock,                                  \
 609                 },                                                      \
 610                 .gate = {                                               \
 611                         .flags = _gate_flags,                           \
 612                         .clk_num = _clk_num,                            \
 613                 },                                                      \
 614                 .mux_ops = &clk_mux_ops,                                \
 615                 .div_ops = &tegra_clk_frac_div_ops,                     \
 616                 .gate_ops = &tegra_clk_periph_gate_ops,                 \
 617         }
 618
 619 struct tegra_periph_init_data {
 620         const char *name;
 621         int clk_id;
 622         union {
 623                 const char *const *parent_names;
 624                 const char *parent_name;
 625         } p;
 626         int num_parents;
 627         struct tegra_clk_periph periph;
 628         u32 offset;
 629         const char *con_id;
 630         const char *dev_id;
 631         unsigned long flags;
 632 };
 633
 634 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
 635                         _mux_shift, _mux_mask, _mux_flags, _div_shift,  \
 636                         _div_width, _div_frac_width, _div_flags,        \
 637                         _clk_num, _gate_flags, _clk_id, _table,         \
 638                         _flags, _lock) \
 639         {                                                               \
 640                 .name = _name,                                          \
 641                 .clk_id = _clk_id,                                      \
 642                 .p.parent_names = _parent_names,                        \
 643                 .num_parents = ARRAY_SIZE(_parent_names),               \
 644                 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask,       \
 645                                            _mux_flags, _div_shift,      \
 646                                            _div_width, _div_frac_width, \
 647                                            _div_flags, _clk_num,        \
 648                                            _gate_flags, _table, _lock), \
 649                 .offset = _offset,                                      \
 650                 .con_id = _con_id,                                      \
 651                 .dev_id = _dev_id,                                      \
 652                 .flags = _flags                                         \
 653         }
 654
 655 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
 656                         _mux_shift, _mux_width, _mux_flags, _div_shift, \
 657                         _div_width, _div_frac_width, _div_flags, \
 658                         _clk_num, _gate_flags, _clk_id) \
 659         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
 660                         _mux_shift, BIT(_mux_width) - 1, _mux_flags,    \
 661                         _div_shift, _div_width, _div_frac_width, _div_flags, \
 662                         _clk_num, _gate_flags, _clk_id,\
 663                         NULL, 0, NULL)
 664
 665 /**
 666  * struct clk_super_mux - super clock
 667  *
 668  * @hw:         handle between common and hardware-specific interfaces
 669  * @reg:        register controlling multiplexer
 670  * @width:      width of the multiplexer bit field
 671  * @flags:      hardware-specific flags
 672  * @div2_index: bit controlling divide-by-2
 673  * @pllx_index: PLLX index in the parent list
 674  * @lock:       register lock
 675  *
 676  * Flags:
 677  * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
 678  *     that this is LP cluster clock.
 679  */
 680 struct tegra_clk_super_mux {
 681         struct clk_hw   hw;
 682         void __iomem    *reg;
 683         struct tegra_clk_frac_div frac_div;
 684         const struct clk_ops    *div_ops;
 685         u8              width;
 686         u8              flags;
 687         u8              div2_index;
 688         u8              pllx_index;
 689         spinlock_t      *lock;
 690 };
 691
 692 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
 693
 694 #define TEGRA_DIVIDER_2 BIT(0)
 695
 696 extern const struct clk_ops tegra_clk_super_ops;
 697 struct clk *tegra_clk_register_super_mux(const char *name,
 698                 const char **parent_names, u8 num_parents,
 699                 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 700                 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
 701 struct clk *tegra_clk_register_super_clk(const char *name,
 702                 const char * const *parent_names, u8 num_parents,
 703                 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 704                 spinlock_t *lock);
 705 /**
 706  * struct clk_init_table - clock initialization table
 707  * @clk_id:     clock id as mentioned in device tree bindings
 708  * @parent_id:  parent clock id as mentioned in device tree bindings
 709  * @rate:       rate to set
 710  * @state:      enable/disable
 711  */
 712 struct tegra_clk_init_table {
 713         unsigned int    clk_id;
 714         unsigned int    parent_id;
 715         unsigned long   rate;
 716         int             state;
 717 };
 718
 719 /**
 720  * struct clk_duplicate - duplicate clocks
 721  * @clk_id:     clock id as mentioned in device tree bindings
 722  * @lookup:     duplicate lookup entry for the clock
 723  */
 724 struct tegra_clk_duplicate {
 725         int                     clk_id;
 726         struct clk_lookup       lookup;
 727 };
 728
 729 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
 730         {                                       \
 731                 .clk_id = _clk_id,              \
 732                 .lookup = {                     \
 733                         .dev_id = _dev,         \
 734                         .con_id = _con,         \
 735                 },                              \
 736         }
 737
 738 struct tegra_clk {
 739         int                     dt_id;
 740         bool                    present;
 741 };
 742
 743 struct tegra_devclk {
 744         int             dt_id;
 745         char            *dev_id;
 746         char            *con_id;
 747 };
 748
 749 void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long),
 750                                int (*deassert)(unsigned long));
 751
 752 void tegra_init_from_table(struct tegra_clk_init_table *tbl,
 753                 struct clk *clks[], int clk_max);
 754
 755 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
 756                 struct clk *clks[], int clk_max);
 757
 758 const struct tegra_clk_periph_regs *get_reg_bank(int clkid);
 759 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
 760
 761 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
 762
 763 void tegra_add_of_provider(struct device_node *np);
 764 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
 765
 766 void tegra_audio_clk_init(void __iomem *clk_base,
 767                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 768                         struct tegra_audio_clk_info *audio_info,
 769                         unsigned int num_plls);
 770
 771 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
 772                         struct tegra_clk *tegra_clks,
 773                         struct tegra_clk_pll_params *pll_params);
 774
 775 void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
 776 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
 777 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
 778                        unsigned long *input_freqs, unsigned int num,
 779                        unsigned int clk_m_div, unsigned long *osc_freq,
 780                        unsigned long *pll_ref_freq);
 781 void tegra_super_clk_gen4_init(void __iomem *clk_base,
 782                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 783                         struct tegra_clk_pll_params *pll_params);
 784 void tegra_super_clk_gen5_init(void __iomem *clk_base,
 785                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 786                         struct tegra_clk_pll_params *pll_params);
 787
 788 #ifdef CONFIG_TEGRA_CLK_EMC
 789 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
 790                                    spinlock_t *lock);
 791 #else
 792 static inline struct clk *tegra_clk_register_emc(void __iomem *base,
 793                                                  struct device_node *np,
 794                                                  spinlock_t *lock)
 795 {
 796         return NULL;
 797 }
 798 #endif
 799
 800 void tegra114_clock_tune_cpu_trimmers_high(void);
 801 void tegra114_clock_tune_cpu_trimmers_low(void);
 802 void tegra114_clock_tune_cpu_trimmers_init(void);
 803 void tegra114_clock_assert_dfll_dvco_reset(void);
 804 void tegra114_clock_deassert_dfll_dvco_reset(void);
 805
 806 typedef void (*tegra_clk_apply_init_table_func)(void);
 807 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 808 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
 809 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
 810 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
 811
 812 #endif /* TEGRA_CLK_H */