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x86/unwinder: Handle stack overflows more gracefully
[linux/fpc-iii.git] / arch / mips / cavium-octeon / octeon-platform.c
blob8505db478904b10855eabf266f75ff9dd93e3699
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2017 Cavium, Inc.
7 * Copyright (C) 2008 Wind River Systems
8 */
9
10 #include <linux/etherdevice.h>
11 #include <linux/of_platform.h>
12 #include <linux/of_fdt.h>
13 #include <linux/libfdt.h>
14
15 #include <asm/octeon/octeon.h>
16 #include <asm/octeon/cvmx-helper-board.h>
17
18 #ifdef CONFIG_USB
19 #include <linux/usb/ehci_def.h>
20 #include <linux/usb/ehci_pdriver.h>
21 #include <linux/usb/ohci_pdriver.h>
22 #include <asm/octeon/cvmx-uctlx-defs.h>
23
24 #define CVMX_UAHCX_EHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000010ull))
25 #define CVMX_UAHCX_OHCI_USBCMD (CVMX_ADD_IO_SEG(0x00016F0000000408ull))
26
27 static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
28
29 static int octeon2_usb_clock_start_cnt;
30
31 static int __init octeon2_usb_reset(void)
32 {
33 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
34 u32 ucmd;
35
36 if (!OCTEON_IS_OCTEON2())
37 return 0;
38
39 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
40 if (clk_rst_ctl.s.hrst) {
41 ucmd = cvmx_read64_uint32(CVMX_UAHCX_EHCI_USBCMD);
42 ucmd &= ~CMD_RUN;
43 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
44 mdelay(2);
45 ucmd |= CMD_RESET;
46 cvmx_write64_uint32(CVMX_UAHCX_EHCI_USBCMD, ucmd);
47 ucmd = cvmx_read64_uint32(CVMX_UAHCX_OHCI_USBCMD);
48 ucmd |= CMD_RUN;
49 cvmx_write64_uint32(CVMX_UAHCX_OHCI_USBCMD, ucmd);
50 }
51
52 return 0;
53 }
54 arch_initcall(octeon2_usb_reset);
55
56 static void octeon2_usb_clocks_start(struct device *dev)
57 {
58 u64 div;
59 union cvmx_uctlx_if_ena if_ena;
60 union cvmx_uctlx_clk_rst_ctl clk_rst_ctl;
61 union cvmx_uctlx_uphy_portx_ctl_status port_ctl_status;
62 int i;
63 unsigned long io_clk_64_to_ns;
64 u32 clock_rate = 12000000;
65 bool is_crystal_clock = false;
66
67
68 mutex_lock(&octeon2_usb_clocks_mutex);
69
70 octeon2_usb_clock_start_cnt++;
71 if (octeon2_usb_clock_start_cnt != 1)
72 goto exit;
73
74 io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
75
76 if (dev->of_node) {
77 struct device_node *uctl_node;
78 const char *clock_type;
79
80 uctl_node = of_get_parent(dev->of_node);
81 if (!uctl_node) {
82 dev_err(dev, "No UCTL device node\n");
83 goto exit;
84 }
85 i = of_property_read_u32(uctl_node,
86 "refclk-frequency", &clock_rate);
87 if (i) {
88 dev_err(dev, "No UCTL \"refclk-frequency\"\n");
89 goto exit;
90 }
91 i = of_property_read_string(uctl_node,
92 "refclk-type", &clock_type);
93
94 if (!i && strcmp("crystal", clock_type) == 0)
95 is_crystal_clock = true;
96 }
97
98 /*
99 * Step 1: Wait for voltages stable. That surely happened
100 * before starting the kernel.
101 *
102 * Step 2: Enable SCLK of UCTL by writing UCTL0_IF_ENA[EN] = 1
103 */
104 if_ena.u64 = 0;
105 if_ena.s.en = 1;
106 cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
107
108 for (i = 0; i <= 1; i++) {
109 port_ctl_status.u64 =
110 cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
111 /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
112 port_ctl_status.s.txvreftune = 15;
113 port_ctl_status.s.txrisetune = 1;
114 port_ctl_status.s.txpreemphasistune = 1;
115 cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
116 port_ctl_status.u64);
117 }
118
119 /* Step 3: Configure the reference clock, PHY, and HCLK */
120 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
121
122 /*
123 * If the UCTL looks like it has already been started, skip
124 * the initialization, otherwise bus errors are obtained.
125 */
126 if (clk_rst_ctl.s.hrst)
127 goto end_clock;
128 /* 3a */
129 clk_rst_ctl.s.p_por = 1;
130 clk_rst_ctl.s.hrst = 0;
131 clk_rst_ctl.s.p_prst = 0;
132 clk_rst_ctl.s.h_clkdiv_rst = 0;
133 clk_rst_ctl.s.o_clkdiv_rst = 0;
134 clk_rst_ctl.s.h_clkdiv_en = 0;
135 clk_rst_ctl.s.o_clkdiv_en = 0;
136 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
137
138 /* 3b */
139 clk_rst_ctl.s.p_refclk_sel = is_crystal_clock ? 0 : 1;
140 switch (clock_rate) {
141 default:
142 pr_err("Invalid UCTL clock rate of %u, using 12000000 instead\n",
143 clock_rate);
144 /* Fall through */
145 case 12000000:
146 clk_rst_ctl.s.p_refclk_div = 0;
147 break;
148 case 24000000:
149 clk_rst_ctl.s.p_refclk_div = 1;
150 break;
151 case 48000000:
152 clk_rst_ctl.s.p_refclk_div = 2;
153 break;
154 }
155 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
156
157 /* 3c */
158 div = octeon_get_io_clock_rate() / 130000000ull;
159
160 switch (div) {
161 case 0:
162 div = 1;
163 break;
164 case 1:
165 case 2:
166 case 3:
167 case 4:
168 break;
169 case 5:
170 div = 4;
171 break;
172 case 6:
173 case 7:
174 div = 6;
175 break;
176 case 8:
177 case 9:
178 case 10:
179 case 11:
180 div = 8;
181 break;
182 default:
183 div = 12;
184 break;
185 }
186 clk_rst_ctl.s.h_div = div;
187 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
188 /* Read it back, */
189 clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
190 clk_rst_ctl.s.h_clkdiv_en = 1;
191 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
192 /* 3d */
193 clk_rst_ctl.s.h_clkdiv_rst = 1;
194 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
195
196 /* 3e: delay 64 io clocks */
197 ndelay(io_clk_64_to_ns);
198
199 /*
200 * Step 4: Program the power-on reset field in the UCTL
201 * clock-reset-control register.
202 */
203 clk_rst_ctl.s.p_por = 0;
204 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
205
206 /* Step 5: Wait 3 ms for the PHY clock to start. */
207 mdelay(3);
208
209 /* Steps 6..9 for ATE only, are skipped. */
210
211 /* Step 10: Configure the OHCI_CLK48 and OHCI_CLK12 clocks. */
212 /* 10a */
213 clk_rst_ctl.s.o_clkdiv_rst = 1;
214 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
215
216 /* 10b */
217 clk_rst_ctl.s.o_clkdiv_en = 1;
218 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
219
220 /* 10c */
221 ndelay(io_clk_64_to_ns);
222
223 /*
224 * Step 11: Program the PHY reset field:
225 * UCTL0_CLK_RST_CTL[P_PRST] = 1
226 */
227 clk_rst_ctl.s.p_prst = 1;
228 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
229
230 /* Step 11b */
231 udelay(1);
232
233 /* Step 11c */
234 clk_rst_ctl.s.p_prst = 0;
235 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
236
237 /* Step 11d */
238 mdelay(1);
239
240 /* Step 11e */
241 clk_rst_ctl.s.p_prst = 1;
242 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
243
244 /* Step 12: Wait 1 uS. */
245 udelay(1);
246
247 /* Step 13: Program the HRESET_N field: UCTL0_CLK_RST_CTL[HRST] = 1 */
248 clk_rst_ctl.s.hrst = 1;
249 cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
250
251 end_clock:
252 /* Set uSOF cycle period to 60,000 bits. */
253 cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
254
255 exit:
256 mutex_unlock(&octeon2_usb_clocks_mutex);
257 }
258
259 static void octeon2_usb_clocks_stop(void)
260 {
261 mutex_lock(&octeon2_usb_clocks_mutex);
262 octeon2_usb_clock_start_cnt--;
263 mutex_unlock(&octeon2_usb_clocks_mutex);
264 }
265
266 static int octeon_ehci_power_on(struct platform_device *pdev)
267 {
268 octeon2_usb_clocks_start(&pdev->dev);
269 return 0;
270 }
271
272 static void octeon_ehci_power_off(struct platform_device *pdev)
273 {
274 octeon2_usb_clocks_stop();
275 }
276
277 static struct usb_ehci_pdata octeon_ehci_pdata = {
278 /* Octeon EHCI matches CPU endianness. */
279 #ifdef __BIG_ENDIAN
280 .big_endian_mmio = 1,
281 #endif
282 /*
283 * We can DMA from anywhere. But the descriptors must be in
284 * the lower 4GB.
285 */
286 .dma_mask_64 = 0,
287 .power_on = octeon_ehci_power_on,
288 .power_off = octeon_ehci_power_off,
289 };
290
291 static void __init octeon_ehci_hw_start(struct device *dev)
292 {
293 union cvmx_uctlx_ehci_ctl ehci_ctl;
294
295 octeon2_usb_clocks_start(dev);
296
297 ehci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_EHCI_CTL(0));
298 /* Use 64-bit addressing. */
299 ehci_ctl.s.ehci_64b_addr_en = 1;
300 ehci_ctl.s.l2c_addr_msb = 0;
301 #ifdef __BIG_ENDIAN
302 ehci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
303 ehci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
304 #else
305 ehci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
306 ehci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
307 ehci_ctl.s.inv_reg_a2 = 1;
308 #endif
309 cvmx_write_csr(CVMX_UCTLX_EHCI_CTL(0), ehci_ctl.u64);
310
311 octeon2_usb_clocks_stop();
312 }
313
314 static int __init octeon_ehci_device_init(void)
315 {
316 struct platform_device *pd;
317 struct device_node *ehci_node;
318 int ret = 0;
319
320 ehci_node = of_find_node_by_name(NULL, "ehci");
321 if (!ehci_node)
322 return 0;
323
324 pd = of_find_device_by_node(ehci_node);
325 if (!pd)
326 return 0;
327
328 pd->dev.platform_data = &octeon_ehci_pdata;
329 octeon_ehci_hw_start(&pd->dev);
330
331 return ret;
332 }
333 device_initcall(octeon_ehci_device_init);
334
335 static int octeon_ohci_power_on(struct platform_device *pdev)
336 {
337 octeon2_usb_clocks_start(&pdev->dev);
338 return 0;
339 }
340
341 static void octeon_ohci_power_off(struct platform_device *pdev)
342 {
343 octeon2_usb_clocks_stop();
344 }
345
346 static struct usb_ohci_pdata octeon_ohci_pdata = {
347 /* Octeon OHCI matches CPU endianness. */
348 #ifdef __BIG_ENDIAN
349 .big_endian_mmio = 1,
350 #endif
351 .power_on = octeon_ohci_power_on,
352 .power_off = octeon_ohci_power_off,
353 };
354
355 static void __init octeon_ohci_hw_start(struct device *dev)
356 {
357 union cvmx_uctlx_ohci_ctl ohci_ctl;
358
359 octeon2_usb_clocks_start(dev);
360
361 ohci_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_OHCI_CTL(0));
362 ohci_ctl.s.l2c_addr_msb = 0;
363 #ifdef __BIG_ENDIAN
364 ohci_ctl.s.l2c_buff_emod = 1; /* Byte swapped. */
365 ohci_ctl.s.l2c_desc_emod = 1; /* Byte swapped. */
366 #else
367 ohci_ctl.s.l2c_buff_emod = 0; /* not swapped. */
368 ohci_ctl.s.l2c_desc_emod = 0; /* not swapped. */
369 ohci_ctl.s.inv_reg_a2 = 1;
370 #endif
371 cvmx_write_csr(CVMX_UCTLX_OHCI_CTL(0), ohci_ctl.u64);
372
373 octeon2_usb_clocks_stop();
374 }
375
376 static int __init octeon_ohci_device_init(void)
377 {
378 struct platform_device *pd;
379 struct device_node *ohci_node;
380 int ret = 0;
381
382 ohci_node = of_find_node_by_name(NULL, "ohci");
383 if (!ohci_node)
384 return 0;
385
386 pd = of_find_device_by_node(ohci_node);
387 if (!pd)
388 return 0;
389
390 pd->dev.platform_data = &octeon_ohci_pdata;
391 octeon_ohci_hw_start(&pd->dev);
392
393 return ret;
394 }
395 device_initcall(octeon_ohci_device_init);
396
397 #endif /* CONFIG_USB */
398
399 /* Octeon Random Number Generator. */
400 static int __init octeon_rng_device_init(void)
401 {
402 struct platform_device *pd;
403 int ret = 0;
404
405 struct resource rng_resources[] = {
406 {
407 .flags = IORESOURCE_MEM,
408 .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS),
409 .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf
410 }, {
411 .flags = IORESOURCE_MEM,
412 .start = cvmx_build_io_address(8, 0),
413 .end = cvmx_build_io_address(8, 0) + 0x7
414 }
415 };
416
417 pd = platform_device_alloc("octeon_rng", -1);
418 if (!pd) {
419 ret = -ENOMEM;
420 goto out;
421 }
422
423 ret = platform_device_add_resources(pd, rng_resources,
424 ARRAY_SIZE(rng_resources));
425 if (ret)
426 goto fail;
427
428 ret = platform_device_add(pd);
429 if (ret)
430 goto fail;
431
432 return ret;
433 fail:
434 platform_device_put(pd);
435
436 out:
437 return ret;
438 }
439 device_initcall(octeon_rng_device_init);
440
441 const struct of_device_id octeon_ids[] __initconst = {
442 { .compatible = "simple-bus", },
443 { .compatible = "cavium,octeon-6335-uctl", },
444 { .compatible = "cavium,octeon-5750-usbn", },
445 { .compatible = "cavium,octeon-3860-bootbus", },
446 { .compatible = "cavium,mdio-mux", },
447 { .compatible = "gpio-leds", },
448 { .compatible = "cavium,octeon-7130-usb-uctl", },
449 {},
450 };
451
452 static bool __init octeon_has_88e1145(void)
453 {
454 return !OCTEON_IS_MODEL(OCTEON_CN52XX) &&
455 !OCTEON_IS_MODEL(OCTEON_CN6XXX) &&
456 !OCTEON_IS_MODEL(OCTEON_CN56XX);
457 }
458
459 static void __init octeon_fdt_set_phy(int eth, int phy_addr)
460 {
461 const __be32 *phy_handle;
462 const __be32 *alt_phy_handle;
463 const __be32 *reg;
464 u32 phandle;
465 int phy;
466 int alt_phy;
467 const char *p;
468 int current_len;
469 char new_name[20];
470
471 phy_handle = fdt_getprop(initial_boot_params, eth, "phy-handle", NULL);
472 if (!phy_handle)
473 return;
474
475 phandle = be32_to_cpup(phy_handle);
476 phy = fdt_node_offset_by_phandle(initial_boot_params, phandle);
477
478 alt_phy_handle = fdt_getprop(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
479 if (alt_phy_handle) {
480 u32 alt_phandle = be32_to_cpup(alt_phy_handle);
481
482 alt_phy = fdt_node_offset_by_phandle(initial_boot_params, alt_phandle);
483 } else {
484 alt_phy = -1;
485 }
486
487 if (phy_addr < 0 || phy < 0) {
488 /* Delete the PHY things */
489 fdt_nop_property(initial_boot_params, eth, "phy-handle");
490 /* This one may fail */
491 fdt_nop_property(initial_boot_params, eth, "cavium,alt-phy-handle");
492 if (phy >= 0)
493 fdt_nop_node(initial_boot_params, phy);
494 if (alt_phy >= 0)
495 fdt_nop_node(initial_boot_params, alt_phy);
496 return;
497 }
498
499 if (phy_addr >= 256 && alt_phy > 0) {
500 const struct fdt_property *phy_prop;
501 struct fdt_property *alt_prop;
502 u32 phy_handle_name;
503
504 /* Use the alt phy node instead.*/
505 phy_prop = fdt_get_property(initial_boot_params, eth, "phy-handle", NULL);
506 phy_handle_name = phy_prop->nameoff;
507 fdt_nop_node(initial_boot_params, phy);
508 fdt_nop_property(initial_boot_params, eth, "phy-handle");
509 alt_prop = fdt_get_property_w(initial_boot_params, eth, "cavium,alt-phy-handle", NULL);
510 alt_prop->nameoff = phy_handle_name;
511 phy = alt_phy;
512 }
513
514 phy_addr &= 0xff;
515
516 if (octeon_has_88e1145()) {
517 fdt_nop_property(initial_boot_params, phy, "marvell,reg-init");
518 memset(new_name, 0, sizeof(new_name));
519 strcpy(new_name, "marvell,88e1145");
520 p = fdt_getprop(initial_boot_params, phy, "compatible",
521 &current_len);
522 if (p && current_len >= strlen(new_name))
523 fdt_setprop_inplace(initial_boot_params, phy,
524 "compatible", new_name, current_len);
525 }
526
527 reg = fdt_getprop(initial_boot_params, phy, "reg", NULL);
528 if (phy_addr == be32_to_cpup(reg))
529 return;
530
531 fdt_setprop_inplace_cell(initial_boot_params, phy, "reg", phy_addr);
532
533 snprintf(new_name, sizeof(new_name), "ethernet-phy@%x", phy_addr);
534
535 p = fdt_get_name(initial_boot_params, phy, &current_len);
536 if (p && current_len == strlen(new_name))
537 fdt_set_name(initial_boot_params, phy, new_name);
538 else
539 pr_err("Error: could not rename ethernet phy: <%s>", p);
540 }
541
542 static void __init octeon_fdt_set_mac_addr(int n, u64 *pmac)
543 {
544 const u8 *old_mac;
545 int old_len;
546 u8 new_mac[6];
547 u64 mac = *pmac;
548 int r;
549
550 old_mac = fdt_getprop(initial_boot_params, n, "local-mac-address",
551 &old_len);
552 if (!old_mac || old_len != 6 || is_valid_ether_addr(old_mac))
553 return;
554
555 new_mac[0] = (mac >> 40) & 0xff;
556 new_mac[1] = (mac >> 32) & 0xff;
557 new_mac[2] = (mac >> 24) & 0xff;
558 new_mac[3] = (mac >> 16) & 0xff;
559 new_mac[4] = (mac >> 8) & 0xff;
560 new_mac[5] = mac & 0xff;
561
562 r = fdt_setprop_inplace(initial_boot_params, n, "local-mac-address",
563 new_mac, sizeof(new_mac));
564
565 if (r) {
566 pr_err("Setting \"local-mac-address\" failed %d", r);
567 return;
568 }
569 *pmac = mac + 1;
570 }
571
572 static void __init octeon_fdt_rm_ethernet(int node)
573 {
574 const __be32 *phy_handle;
575
576 phy_handle = fdt_getprop(initial_boot_params, node, "phy-handle", NULL);
577 if (phy_handle) {
578 u32 ph = be32_to_cpup(phy_handle);
579 int p = fdt_node_offset_by_phandle(initial_boot_params, ph);
580
581 if (p >= 0)
582 fdt_nop_node(initial_boot_params, p);
583 }
584 fdt_nop_node(initial_boot_params, node);
585 }
586
587 static void __init octeon_fdt_pip_port(int iface, int i, int p, int max)
588 {
589 char name_buffer[20];
590 int eth;
591 int phy_addr;
592 int ipd_port;
593
594 snprintf(name_buffer, sizeof(name_buffer), "ethernet@%x", p);
595 eth = fdt_subnode_offset(initial_boot_params, iface, name_buffer);
596 if (eth < 0)
597 return;
598 if (p > max) {
599 pr_debug("Deleting port %x:%x\n", i, p);
600 octeon_fdt_rm_ethernet(eth);
601 return;
602 }
603 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
604 ipd_port = (0x100 * i) + (0x10 * p) + 0x800;
605 else
606 ipd_port = 16 * i + p;
607
608 phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
609 octeon_fdt_set_phy(eth, phy_addr);
610 }
611
612 static void __init octeon_fdt_pip_iface(int pip, int idx)
613 {
614 char name_buffer[20];
615 int iface;
616 int p;
617 int count = 0;
618
619 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", idx);
620 iface = fdt_subnode_offset(initial_boot_params, pip, name_buffer);
621 if (iface < 0)
622 return;
623
624 if (cvmx_helper_interface_enumerate(idx) == 0)
625 count = cvmx_helper_ports_on_interface(idx);
626
627 for (p = 0; p < 16; p++)
628 octeon_fdt_pip_port(iface, idx, p, count - 1);
629 }
630
631 void __init octeon_fill_mac_addresses(void)
632 {
633 const char *alias_prop;
634 char name_buffer[20];
635 u64 mac_addr_base;
636 int aliases;
637 int pip;
638 int i;
639
640 aliases = fdt_path_offset(initial_boot_params, "/aliases");
641 if (aliases < 0)
642 return;
643
644 mac_addr_base =
645 ((octeon_bootinfo->mac_addr_base[0] & 0xffull)) << 40 |
646 ((octeon_bootinfo->mac_addr_base[1] & 0xffull)) << 32 |
647 ((octeon_bootinfo->mac_addr_base[2] & 0xffull)) << 24 |
648 ((octeon_bootinfo->mac_addr_base[3] & 0xffull)) << 16 |
649 ((octeon_bootinfo->mac_addr_base[4] & 0xffull)) << 8 |
650 (octeon_bootinfo->mac_addr_base[5] & 0xffull);
651
652 for (i = 0; i < 2; i++) {
653 int mgmt;
654
655 snprintf(name_buffer, sizeof(name_buffer), "mix%d", i);
656 alias_prop = fdt_getprop(initial_boot_params, aliases,
657 name_buffer, NULL);
658 if (!alias_prop)
659 continue;
660 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
661 if (mgmt < 0)
662 continue;
663 octeon_fdt_set_mac_addr(mgmt, &mac_addr_base);
664 }
665
666 alias_prop = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
667 if (!alias_prop)
668 return;
669
670 pip = fdt_path_offset(initial_boot_params, alias_prop);
671 if (pip < 0)
672 return;
673
674 for (i = 0; i <= 4; i++) {
675 int iface;
676 int p;
677
678 snprintf(name_buffer, sizeof(name_buffer), "interface@%d", i);
679 iface = fdt_subnode_offset(initial_boot_params, pip,
680 name_buffer);
681 if (iface < 0)
682 continue;
683 for (p = 0; p < 16; p++) {
684 int eth;
685
686 snprintf(name_buffer, sizeof(name_buffer),
687 "ethernet@%x", p);
688 eth = fdt_subnode_offset(initial_boot_params, iface,
689 name_buffer);
690 if (eth < 0)
691 continue;
692 octeon_fdt_set_mac_addr(eth, &mac_addr_base);
693 }
694 }
695 }
696
697 int __init octeon_prune_device_tree(void)
698 {
699 int i, max_port, uart_mask;
700 const char *pip_path;
701 const char *alias_prop;
702 char name_buffer[20];
703 int aliases;
704
705 if (fdt_check_header(initial_boot_params))
706 panic("Corrupt Device Tree.");
707
708 WARN(octeon_bootinfo->board_type == CVMX_BOARD_TYPE_CUST_DSR1000N,
709 "Built-in DTB booting is deprecated on %s. Please switch to use appended DTB.",
710 cvmx_board_type_to_string(octeon_bootinfo->board_type));
711
712 aliases = fdt_path_offset(initial_boot_params, "/aliases");
713 if (aliases < 0) {
714 pr_err("Error: No /aliases node in device tree.");
715 return -EINVAL;
716 }
717
718 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX))
719 max_port = 2;
720 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN68XX))
721 max_port = 1;
722 else
723 max_port = 0;
724
725 if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E)
726 max_port = 0;
727
728 for (i = 0; i < 2; i++) {
729 int mgmt;
730
731 snprintf(name_buffer, sizeof(name_buffer),
732 "mix%d", i);
733 alias_prop = fdt_getprop(initial_boot_params, aliases,
734 name_buffer, NULL);
735 if (alias_prop) {
736 mgmt = fdt_path_offset(initial_boot_params, alias_prop);
737 if (mgmt < 0)
738 continue;
739 if (i >= max_port) {
740 pr_debug("Deleting mix%d\n", i);
741 octeon_fdt_rm_ethernet(mgmt);
742 fdt_nop_property(initial_boot_params, aliases,
743 name_buffer);
744 } else {
745 int phy_addr = cvmx_helper_board_get_mii_address(CVMX_HELPER_BOARD_MGMT_IPD_PORT + i);
746
747 octeon_fdt_set_phy(mgmt, phy_addr);
748 }
749 }
750 }
751
752 pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
753 if (pip_path) {
754 int pip = fdt_path_offset(initial_boot_params, pip_path);
755
756 if (pip >= 0)
757 for (i = 0; i <= 4; i++)
758 octeon_fdt_pip_iface(pip, i);
759 }
760
761 /* I2C */
762 if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
763 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
764 OCTEON_IS_MODEL(OCTEON_CN68XX) ||
765 OCTEON_IS_MODEL(OCTEON_CN56XX))
766 max_port = 2;
767 else
768 max_port = 1;
769
770 for (i = 0; i < 2; i++) {
771 int i2c;
772
773 snprintf(name_buffer, sizeof(name_buffer),
774 "twsi%d", i);
775 alias_prop = fdt_getprop(initial_boot_params, aliases,
776 name_buffer, NULL);
777
778 if (alias_prop) {
779 i2c = fdt_path_offset(initial_boot_params, alias_prop);
780 if (i2c < 0)
781 continue;
782 if (i >= max_port) {
783 pr_debug("Deleting twsi%d\n", i);
784 fdt_nop_node(initial_boot_params, i2c);
785 fdt_nop_property(initial_boot_params, aliases,
786 name_buffer);
787 }
788 }
789 }
790
791 /* SMI/MDIO */
792 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
793 max_port = 4;
794 else if (OCTEON_IS_MODEL(OCTEON_CN52XX) ||
795 OCTEON_IS_MODEL(OCTEON_CN63XX) ||
796 OCTEON_IS_MODEL(OCTEON_CN56XX))
797 max_port = 2;
798 else
799 max_port = 1;
800
801 for (i = 0; i < 2; i++) {
802 int i2c;
803
804 snprintf(name_buffer, sizeof(name_buffer),
805 "smi%d", i);
806 alias_prop = fdt_getprop(initial_boot_params, aliases,
807 name_buffer, NULL);
808 if (alias_prop) {
809 i2c = fdt_path_offset(initial_boot_params, alias_prop);
810 if (i2c < 0)
811 continue;
812 if (i >= max_port) {
813 pr_debug("Deleting smi%d\n", i);
814 fdt_nop_node(initial_boot_params, i2c);
815 fdt_nop_property(initial_boot_params, aliases,
816 name_buffer);
817 }
818 }
819 }
820
821 /* Serial */
822 uart_mask = 3;
823
824 /* Right now CN52XX is the only chip with a third uart */
825 if (OCTEON_IS_MODEL(OCTEON_CN52XX))
826 uart_mask |= 4; /* uart2 */
827
828 for (i = 0; i < 3; i++) {
829 int uart;
830
831 snprintf(name_buffer, sizeof(name_buffer),
832 "uart%d", i);
833 alias_prop = fdt_getprop(initial_boot_params, aliases,
834 name_buffer, NULL);
835
836 if (alias_prop) {
837 uart = fdt_path_offset(initial_boot_params, alias_prop);
838 if (uart_mask & (1 << i)) {
839 __be32 f;
840
841 f = cpu_to_be32(octeon_get_io_clock_rate());
842 fdt_setprop_inplace(initial_boot_params,
843 uart, "clock-frequency",
844 &f, sizeof(f));
845 continue;
846 }
847 pr_debug("Deleting uart%d\n", i);
848 fdt_nop_node(initial_boot_params, uart);
849 fdt_nop_property(initial_boot_params, aliases,
850 name_buffer);
851 }
852 }
853
854 /* Compact Flash */
855 alias_prop = fdt_getprop(initial_boot_params, aliases,
856 "cf0", NULL);
857 if (alias_prop) {
858 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
859 unsigned long base_ptr, region_base, region_size;
860 unsigned long region1_base = 0;
861 unsigned long region1_size = 0;
862 int cs, bootbus;
863 bool is_16bit = false;
864 bool is_true_ide = false;
865 __be32 new_reg[6];
866 __be32 *ranges;
867 int len;
868
869 int cf = fdt_path_offset(initial_boot_params, alias_prop);
870
871 base_ptr = 0;
872 if (octeon_bootinfo->major_version == 1
873 && octeon_bootinfo->minor_version >= 1) {
874 if (octeon_bootinfo->compact_flash_common_base_addr)
875 base_ptr = octeon_bootinfo->compact_flash_common_base_addr;
876 } else {
877 base_ptr = 0x1d000800;
878 }
879
880 if (!base_ptr)
881 goto no_cf;
882
883 /* Find CS0 region. */
884 for (cs = 0; cs < 8; cs++) {
885 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
886 region_base = mio_boot_reg_cfg.s.base << 16;
887 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
888 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
889 && base_ptr < region_base + region_size) {
890 is_16bit = mio_boot_reg_cfg.s.width;
891 break;
892 }
893 }
894 if (cs >= 7) {
895 /* cs and cs + 1 are CS0 and CS1, both must be less than 8. */
896 goto no_cf;
897 }
898
899 if (!(base_ptr & 0xfffful)) {
900 /*
901 * Boot loader signals availability of DMA (true_ide
902 * mode) by setting low order bits of base_ptr to
903 * zero.
904 */
905
906 /* Asume that CS1 immediately follows. */
907 mio_boot_reg_cfg.u64 =
908 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs + 1));
909 region1_base = mio_boot_reg_cfg.s.base << 16;
910 region1_size = (mio_boot_reg_cfg.s.size + 1) << 16;
911 if (!mio_boot_reg_cfg.s.en)
912 goto no_cf;
913 is_true_ide = true;
914
915 } else {
916 fdt_nop_property(initial_boot_params, cf, "cavium,true-ide");
917 fdt_nop_property(initial_boot_params, cf, "cavium,dma-engine-handle");
918 if (!is_16bit) {
919 __be32 width = cpu_to_be32(8);
920
921 fdt_setprop_inplace(initial_boot_params, cf,
922 "cavium,bus-width", &width, sizeof(width));
923 }
924 }
925 new_reg[0] = cpu_to_be32(cs);
926 new_reg[1] = cpu_to_be32(0);
927 new_reg[2] = cpu_to_be32(0x10000);
928 new_reg[3] = cpu_to_be32(cs + 1);
929 new_reg[4] = cpu_to_be32(0);
930 new_reg[5] = cpu_to_be32(0x10000);
931 fdt_setprop_inplace(initial_boot_params, cf,
932 "reg", new_reg, sizeof(new_reg));
933
934 bootbus = fdt_parent_offset(initial_boot_params, cf);
935 if (bootbus < 0)
936 goto no_cf;
937 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
938 if (!ranges || len < (5 * 8 * sizeof(__be32)))
939 goto no_cf;
940
941 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
942 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
943 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
944 if (is_true_ide) {
945 cs++;
946 ranges[(cs * 5) + 2] = cpu_to_be32(region1_base >> 32);
947 ranges[(cs * 5) + 3] = cpu_to_be32(region1_base & 0xffffffff);
948 ranges[(cs * 5) + 4] = cpu_to_be32(region1_size);
949 }
950 goto end_cf;
951 no_cf:
952 fdt_nop_node(initial_boot_params, cf);
953
954 end_cf:
955 ;
956 }
957
958 /* 8 char LED */
959 alias_prop = fdt_getprop(initial_boot_params, aliases,
960 "led0", NULL);
961 if (alias_prop) {
962 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
963 unsigned long base_ptr, region_base, region_size;
964 int cs, bootbus;
965 __be32 new_reg[6];
966 __be32 *ranges;
967 int len;
968 int led = fdt_path_offset(initial_boot_params, alias_prop);
969
970 base_ptr = octeon_bootinfo->led_display_base_addr;
971 if (base_ptr == 0)
972 goto no_led;
973 /* Find CS0 region. */
974 for (cs = 0; cs < 8; cs++) {
975 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
976 region_base = mio_boot_reg_cfg.s.base << 16;
977 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
978 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
979 && base_ptr < region_base + region_size)
980 break;
981 }
982
983 if (cs > 7)
984 goto no_led;
985
986 new_reg[0] = cpu_to_be32(cs);
987 new_reg[1] = cpu_to_be32(0x20);
988 new_reg[2] = cpu_to_be32(0x20);
989 new_reg[3] = cpu_to_be32(cs);
990 new_reg[4] = cpu_to_be32(0);
991 new_reg[5] = cpu_to_be32(0x20);
992 fdt_setprop_inplace(initial_boot_params, led,
993 "reg", new_reg, sizeof(new_reg));
994
995 bootbus = fdt_parent_offset(initial_boot_params, led);
996 if (bootbus < 0)
997 goto no_led;
998 ranges = fdt_getprop_w(initial_boot_params, bootbus, "ranges", &len);
999 if (!ranges || len < (5 * 8 * sizeof(__be32)))
1000 goto no_led;
1001
1002 ranges[(cs * 5) + 2] = cpu_to_be32(region_base >> 32);
1003 ranges[(cs * 5) + 3] = cpu_to_be32(region_base & 0xffffffff);
1004 ranges[(cs * 5) + 4] = cpu_to_be32(region_size);
1005 goto end_led;
1006
1007 no_led:
1008 fdt_nop_node(initial_boot_params, led);
1009 end_led:
1010 ;
1011 }
1012
1013 #ifdef CONFIG_USB
1014 /* OHCI/UHCI USB */
1015 alias_prop = fdt_getprop(initial_boot_params, aliases,
1016 "uctl", NULL);
1017 if (alias_prop) {
1018 int uctl = fdt_path_offset(initial_boot_params, alias_prop);
1019
1020 if (uctl >= 0 && (!OCTEON_IS_MODEL(OCTEON_CN6XXX) ||
1021 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC2E)) {
1022 pr_debug("Deleting uctl\n");
1023 fdt_nop_node(initial_boot_params, uctl);
1024 fdt_nop_property(initial_boot_params, aliases, "uctl");
1025 } else if (octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC10E ||
1026 octeon_bootinfo->board_type == CVMX_BOARD_TYPE_NIC4E) {
1027 /* Missing "refclk-type" defaults to crystal. */
1028 fdt_nop_property(initial_boot_params, uctl, "refclk-type");
1029 }
1030 }
1031
1032 /* DWC2 USB */
1033 alias_prop = fdt_getprop(initial_boot_params, aliases,
1034 "usbn", NULL);
1035 if (alias_prop) {
1036 int usbn = fdt_path_offset(initial_boot_params, alias_prop);
1037
1038 if (usbn >= 0 && (current_cpu_type() == CPU_CAVIUM_OCTEON2 ||
1039 !octeon_has_feature(OCTEON_FEATURE_USB))) {
1040 pr_debug("Deleting usbn\n");
1041 fdt_nop_node(initial_boot_params, usbn);
1042 fdt_nop_property(initial_boot_params, aliases, "usbn");
1043 } else {
1044 __be32 new_f[1];
1045 enum cvmx_helper_board_usb_clock_types c;
1046
1047 c = __cvmx_helper_board_usb_get_clock_type();
1048 switch (c) {
1049 case USB_CLOCK_TYPE_REF_48:
1050 new_f[0] = cpu_to_be32(48000000);
1051 fdt_setprop_inplace(initial_boot_params, usbn,
1052 "refclk-frequency", new_f, sizeof(new_f));
1053 /* Fall through ...*/
1054 case USB_CLOCK_TYPE_REF_12:
1055 /* Missing "refclk-type" defaults to external. */
1056 fdt_nop_property(initial_boot_params, usbn, "refclk-type");
1057 break;
1058 default:
1059 break;
1060 }
1061 }
1062 }
1063 #endif
1064
1065 return 0;
1066 }
1067
1068 static int __init octeon_publish_devices(void)
1069 {
1070 return of_platform_bus_probe(NULL, octeon_ids, NULL);
1071 }
1072 arch_initcall(octeon_publish_devices);
Linux with added FPC-III support