| blob | 09ac5c43807ee6f31da0b1f007802e49be56c68b |
1 /*
2 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
16 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
17 #include <dt-bindings/clock/qcom,rpmcc.h>
19 / {
20 model = "Qualcomm Technologies, Inc. MSM8916";
21 compatible = "qcom,msm8916";
23 interrupt-parent = <&intc>;
25 #address-cells = <2>;
26 #size-cells = <2>;
28 aliases {
29 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
30 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
31 };
33 chosen { };
35 memory {
36 device_type = "memory";
37 /* We expect the bootloader to fill in the reg */
38 reg = <0 0 0 0>;
39 };
41 reserved-memory {
42 #address-cells = <2>;
43 #size-cells = <2>;
44 ranges;
46 tz-apps@86000000 {
47 reg = <0x0 0x86000000 0x0 0x300000>;
48 no-map;
49 };
51 smem_mem: smem_region@86300000 {
52 reg = <0x0 0x86300000 0x0 0x100000>;
53 no-map;
54 };
56 hypervisor@86400000 {
57 reg = <0x0 0x86400000 0x0 0x100000>;
58 no-map;
59 };
61 tz@86500000 {
62 reg = <0x0 0x86500000 0x0 0x180000>;
63 no-map;
64 };
66 reserved@8668000 {
67 reg = <0x0 0x86680000 0x0 0x80000>;
68 no-map;
69 };
71 rmtfs@86700000 {
72 compatible = "qcom,rmtfs-mem";
73 reg = <0x0 0x86700000 0x0 0xe0000>;
74 no-map;
76 qcom,client-id = <1>;
77 };
79 rfsa@867e00000 {
80 reg = <0x0 0x867e0000 0x0 0x20000>;
81 no-map;
82 };
84 mpss_mem: mpss@86800000 {
85 reg = <0x0 0x86800000 0x0 0x2b00000>;
86 no-map;
87 };
89 wcnss_mem: wcnss@89300000 {
90 reg = <0x0 0x89300000 0x0 0x600000>;
91 no-map;
92 };
94 venus_mem: venus@89900000 {
95 reg = <0x0 0x89900000 0x0 0x600000>;
96 no-map;
97 };
99 mba_mem: mba@8ea00000 {
100 no-map;
101 reg = <0 0x8ea00000 0 0x100000>;
102 };
103 };
105 cpus {
106 #address-cells = <1>;
107 #size-cells = <0>;
109 CPU0: cpu@0 {
110 device_type = "cpu";
111 compatible = "arm,cortex-a53", "arm,armv8";
112 reg = <0x0>;
113 next-level-cache = <&L2_0>;
114 enable-method = "psci";
115 cpu-idle-states = <&CPU_SPC>;
116 };
118 CPU1: cpu@1 {
119 device_type = "cpu";
120 compatible = "arm,cortex-a53", "arm,armv8";
121 reg = <0x1>;
122 next-level-cache = <&L2_0>;
123 enable-method = "psci";
124 cpu-idle-states = <&CPU_SPC>;
125 };
127 CPU2: cpu@2 {
128 device_type = "cpu";
129 compatible = "arm,cortex-a53", "arm,armv8";
130 reg = <0x2>;
131 next-level-cache = <&L2_0>;
132 enable-method = "psci";
133 cpu-idle-states = <&CPU_SPC>;
134 };
136 CPU3: cpu@3 {
137 device_type = "cpu";
138 compatible = "arm,cortex-a53", "arm,armv8";
139 reg = <0x3>;
140 next-level-cache = <&L2_0>;
141 enable-method = "psci";
142 cpu-idle-states = <&CPU_SPC>;
143 };
145 L2_0: l2-cache {
146 compatible = "cache";
147 cache-level = <2>;
148 };
150 idle-states {
151 CPU_SPC: spc {
152 compatible = "arm,idle-state";
153 arm,psci-suspend-param = <0x40000002>;
154 entry-latency-us = <130>;
155 exit-latency-us = <150>;
156 min-residency-us = <2000>;
157 local-timer-stop;
158 };
159 };
160 };
162 psci {
163 compatible = "arm,psci-1.0";
164 method = "smc";
165 };
167 pmu {
168 compatible = "arm,cortex-a53-pmu";
169 interrupts = <GIC_PPI 7 GIC_CPU_MASK_SIMPLE(4)>;
170 };
172 thermal-zones {
173 cpu-thermal0 {
174 polling-delay-passive = <250>;
175 polling-delay = <1000>;
177 thermal-sensors = <&tsens 4>;
179 trips {
180 cpu_alert0: trip0 {
181 temperature = <75000>;
182 hysteresis = <2000>;
183 type = "passive";
184 };
185 cpu_crit0: trip1 {
186 temperature = <110000>;
187 hysteresis = <2000>;
188 type = "critical";
189 };
190 };
191 };
193 cpu-thermal1 {
194 polling-delay-passive = <250>;
195 polling-delay = <1000>;
197 thermal-sensors = <&tsens 3>;
199 trips {
200 cpu_alert1: trip0 {
201 temperature = <75000>;
202 hysteresis = <2000>;
203 type = "passive";
204 };
205 cpu_crit1: trip1 {
206 temperature = <110000>;
207 hysteresis = <2000>;
208 type = "critical";
209 };
210 };
211 };
213 };
215 gpu_opp_table: opp_table {
216 compatible = "operating-points-v2";
218 opp-400000000 {
219 opp-hz = /bits/ 64 <400000000>;
220 };
221 opp-19200000 {
222 opp-hz = /bits/ 64 <19200000>;
223 };
224 };
226 timer {
227 compatible = "arm,armv8-timer";
228 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
229 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
230 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
231 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
232 };
234 clocks {
235 xo_board: xo_board {
236 compatible = "fixed-clock";
237 #clock-cells = <0>;
238 clock-frequency = <19200000>;
239 };
241 sleep_clk: sleep_clk {
242 compatible = "fixed-clock";
243 #clock-cells = <0>;
244 clock-frequency = <32768>;
245 };
246 };
248 smem {
249 compatible = "qcom,smem";
251 memory-region = <&smem_mem>;
252 qcom,rpm-msg-ram = <&rpm_msg_ram>;
254 hwlocks = <&tcsr_mutex 3>;
255 };
257 firmware {
258 scm: scm {
259 compatible = "qcom,scm";
260 clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
261 clock-names = "core", "bus", "iface";
262 #reset-cells = <1>;
264 qcom,dload-mode = <&tcsr 0x6100>;
265 };
266 };
268 soc: soc {
269 #address-cells = <1>;
270 #size-cells = <1>;
271 ranges = <0 0 0 0xffffffff>;
272 compatible = "simple-bus";
274 restart@4ab000 {
275 compatible = "qcom,pshold";
276 reg = <0x4ab000 0x4>;
277 };
279 msmgpio: pinctrl@1000000 {
280 compatible = "qcom,msm8916-pinctrl";
281 reg = <0x1000000 0x300000>;
282 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
283 gpio-controller;
284 #gpio-cells = <2>;
285 interrupt-controller;
286 #interrupt-cells = <2>;
287 };
289 gcc: clock-controller@1800000 {
290 compatible = "qcom,gcc-msm8916";
291 #clock-cells = <1>;
292 #reset-cells = <1>;
293 #power-domain-cells = <1>;
294 reg = <0x1800000 0x80000>;
295 };
297 tcsr_mutex_regs: syscon@1905000 {
298 compatible = "syscon";
299 reg = <0x1905000 0x20000>;
300 };
302 tcsr: syscon@1937000 {
303 compatible = "qcom,tcsr-msm8916", "syscon";
304 reg = <0x1937000 0x30000>;
305 };
307 tcsr_mutex: hwlock {
308 compatible = "qcom,tcsr-mutex";
309 syscon = <&tcsr_mutex_regs 0 0x1000>;
310 #hwlock-cells = <1>;
311 };
313 rpm_msg_ram: memory@60000 {
314 compatible = "qcom,rpm-msg-ram";
315 reg = <0x60000 0x8000>;
316 };
318 blsp1_uart1: serial@78af000 {
319 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
320 reg = <0x78af000 0x200>;
321 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
322 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
323 clock-names = "core", "iface";
324 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
325 dma-names = "rx", "tx";
326 status = "disabled";
327 };
329 apcs: syscon@b011000 {
330 compatible = "syscon";
331 reg = <0x0b011000 0x1000>;
332 };
334 blsp1_uart2: serial@78b0000 {
335 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
336 reg = <0x78b0000 0x200>;
337 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
339 clock-names = "core", "iface";
340 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
341 dma-names = "rx", "tx";
342 status = "disabled";
343 };
345 blsp_dma: dma@7884000 {
346 compatible = "qcom,bam-v1.7.0";
347 reg = <0x07884000 0x23000>;
348 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
350 clock-names = "bam_clk";
351 #dma-cells = <1>;
352 qcom,ee = <0>;
353 status = "disabled";
354 };
356 blsp_spi1: spi@78b5000 {
357 compatible = "qcom,spi-qup-v2.2.1";
358 reg = <0x078b5000 0x600>;
359 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
361 <&gcc GCC_BLSP1_AHB_CLK>;
362 clock-names = "core", "iface";
363 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
364 dma-names = "rx", "tx";
365 pinctrl-names = "default", "sleep";
366 pinctrl-0 = <&spi1_default>;
367 pinctrl-1 = <&spi1_sleep>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370 status = "disabled";
371 };
373 blsp_spi2: spi@78b6000 {
374 compatible = "qcom,spi-qup-v2.2.1";
375 reg = <0x078b6000 0x600>;
376 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
378 <&gcc GCC_BLSP1_AHB_CLK>;
379 clock-names = "core", "iface";
380 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
381 dma-names = "rx", "tx";
382 pinctrl-names = "default", "sleep";
383 pinctrl-0 = <&spi2_default>;
384 pinctrl-1 = <&spi2_sleep>;
385 #address-cells = <1>;
386 #size-cells = <0>;
387 status = "disabled";
388 };
390 blsp_spi3: spi@78b7000 {
391 compatible = "qcom,spi-qup-v2.2.1";
392 reg = <0x078b7000 0x600>;
393 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
395 <&gcc GCC_BLSP1_AHB_CLK>;
396 clock-names = "core", "iface";
397 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
398 dma-names = "rx", "tx";
399 pinctrl-names = "default", "sleep";
400 pinctrl-0 = <&spi3_default>;
401 pinctrl-1 = <&spi3_sleep>;
402 #address-cells = <1>;
403 #size-cells = <0>;
404 status = "disabled";
405 };
407 blsp_spi4: spi@78b8000 {
408 compatible = "qcom,spi-qup-v2.2.1";
409 reg = <0x078b8000 0x600>;
410 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
412 <&gcc GCC_BLSP1_AHB_CLK>;
413 clock-names = "core", "iface";
414 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
415 dma-names = "rx", "tx";
416 pinctrl-names = "default", "sleep";
417 pinctrl-0 = <&spi4_default>;
418 pinctrl-1 = <&spi4_sleep>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 status = "disabled";
422 };
424 blsp_spi5: spi@78b9000 {
425 compatible = "qcom,spi-qup-v2.2.1";
426 reg = <0x078b9000 0x600>;
427 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
428 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
429 <&gcc GCC_BLSP1_AHB_CLK>;
430 clock-names = "core", "iface";
431 dmas = <&blsp_dma 13>, <&blsp_dma 12>;
432 dma-names = "rx", "tx";
433 pinctrl-names = "default", "sleep";
434 pinctrl-0 = <&spi5_default>;
435 pinctrl-1 = <&spi5_sleep>;
436 #address-cells = <1>;
437 #size-cells = <0>;
438 status = "disabled";
439 };
441 blsp_spi6: spi@78ba000 {
442 compatible = "qcom,spi-qup-v2.2.1";
443 reg = <0x078ba000 0x600>;
444 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
446 <&gcc GCC_BLSP1_AHB_CLK>;
447 clock-names = "core", "iface";
448 dmas = <&blsp_dma 15>, <&blsp_dma 14>;
449 dma-names = "rx", "tx";
450 pinctrl-names = "default", "sleep";
451 pinctrl-0 = <&spi6_default>;
452 pinctrl-1 = <&spi6_sleep>;
453 #address-cells = <1>;
454 #size-cells = <0>;
455 status = "disabled";
456 };
458 blsp_i2c2: i2c@78b6000 {
459 compatible = "qcom,i2c-qup-v2.2.1";
460 reg = <0x78b6000 0x1000>;
461 interrupts = <GIC_SPI 96 0>;
462 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
463 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
464 clock-names = "iface", "core";
465 pinctrl-names = "default", "sleep";
466 pinctrl-0 = <&i2c2_default>;
467 pinctrl-1 = <&i2c2_sleep>;
468 #address-cells = <1>;
469 #size-cells = <0>;
470 status = "disabled";
471 };
473 blsp_i2c4: i2c@78b8000 {
474 compatible = "qcom,i2c-qup-v2.2.1";
475 reg = <0x78b8000 0x1000>;
476 interrupts = <GIC_SPI 98 0>;
477 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
478 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
479 clock-names = "iface", "core";
480 pinctrl-names = "default", "sleep";
481 pinctrl-0 = <&i2c4_default>;
482 pinctrl-1 = <&i2c4_sleep>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 status = "disabled";
486 };
488 blsp_i2c6: i2c@78ba000 {
489 compatible = "qcom,i2c-qup-v2.2.1";
490 reg = <0x78ba000 0x1000>;
491 interrupts = <GIC_SPI 100 0>;
492 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
493 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
494 clock-names = "iface", "core";
495 pinctrl-names = "default", "sleep";
496 pinctrl-0 = <&i2c6_default>;
497 pinctrl-1 = <&i2c6_sleep>;
498 #address-cells = <1>;
499 #size-cells = <0>;
500 status = "disabled";
501 };
503 lpass: lpass@7708000 {
504 status = "disabled";
505 compatible = "qcom,lpass-cpu-apq8016";
506 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
507 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
508 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
509 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
510 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
511 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
512 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
514 clock-names = "ahbix-clk",
515 "pcnoc-mport-clk",
516 "pcnoc-sway-clk",
517 "mi2s-bit-clk0",
518 "mi2s-bit-clk1",
519 "mi2s-bit-clk2",
520 "mi2s-bit-clk3";
521 #sound-dai-cells = <1>;
523 interrupts = <0 160 0>;
524 interrupt-names = "lpass-irq-lpaif";
525 reg = <0x07708000 0x10000>;
526 reg-names = "lpass-lpaif";
527 };
529 lpass_codec: codec{
530 compatible = "qcom,msm8916-wcd-digital-codec";
531 reg = <0x0771c000 0x400>;
532 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
533 <&gcc GCC_CODEC_DIGCODEC_CLK>;
534 clock-names = "ahbix-clk", "mclk";
535 #sound-dai-cells = <1>;
536 };
538 sdhc_1: sdhci@7824000 {
539 compatible = "qcom,sdhci-msm-v4";
540 reg = <0x07824900 0x11c>, <0x07824000 0x800>;
541 reg-names = "hc_mem", "core_mem";
543 interrupts = <0 123 0>, <0 138 0>;
544 interrupt-names = "hc_irq", "pwr_irq";
545 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
546 <&gcc GCC_SDCC1_AHB_CLK>,
547 <&xo_board>;
548 clock-names = "core", "iface", "xo";
549 mmc-ddr-1_8v;
550 bus-width = <8>;
551 non-removable;
552 status = "disabled";
553 };
555 sdhc_2: sdhci@7864000 {
556 compatible = "qcom,sdhci-msm-v4";
557 reg = <0x07864900 0x11c>, <0x07864000 0x800>;
558 reg-names = "hc_mem", "core_mem";
560 interrupts = <0 125 0>, <0 221 0>;
561 interrupt-names = "hc_irq", "pwr_irq";
562 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
563 <&gcc GCC_SDCC2_AHB_CLK>,
564 <&xo_board>;
565 clock-names = "core", "iface", "xo";
566 bus-width = <4>;
567 status = "disabled";
568 };
570 otg: usb@78d9000 {
571 compatible = "qcom,ci-hdrc";
572 reg = <0x78d9000 0x200>,
573 <0x78d9200 0x200>;
574 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
576 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
577 <&gcc GCC_USB_HS_SYSTEM_CLK>;
578 clock-names = "iface", "core";
579 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
580 assigned-clock-rates = <80000000>;
581 resets = <&gcc GCC_USB_HS_BCR>;
582 reset-names = "core";
583 phy_type = "ulpi";
584 dr_mode = "otg";
585 ahb-burst-config = <0>;
586 phy-names = "usb-phy";
587 phys = <&usb_hs_phy>;
588 status = "disabled";
589 #reset-cells = <1>;
591 ulpi {
592 usb_hs_phy: phy {
593 compatible = "qcom,usb-hs-phy-msm8916",
594 "qcom,usb-hs-phy";
595 #phy-cells = <0>;
596 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
597 clock-names = "ref", "sleep";
598 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
599 reset-names = "phy", "por";
600 qcom,init-seq = /bits/ 8 <0x0 0x44
601 0x1 0x6b 0x2 0x24 0x3 0x13>;
602 };
603 };
604 };
606 intc: interrupt-controller@b000000 {
607 compatible = "qcom,msm-qgic2";
608 interrupt-controller;
609 #interrupt-cells = <3>;
610 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
611 };
613 timer@b020000 {
614 #address-cells = <1>;
615 #size-cells = <1>;
616 ranges;
617 compatible = "arm,armv7-timer-mem";
618 reg = <0xb020000 0x1000>;
619 clock-frequency = <19200000>;
621 frame@b021000 {
622 frame-number = <0>;
623 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
624 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
625 reg = <0xb021000 0x1000>,
626 <0xb022000 0x1000>;
627 };
629 frame@b023000 {
630 frame-number = <1>;
631 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
632 reg = <0xb023000 0x1000>;
633 status = "disabled";
634 };
636 frame@b024000 {
637 frame-number = <2>;
638 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
639 reg = <0xb024000 0x1000>;
640 status = "disabled";
641 };
643 frame@b025000 {
644 frame-number = <3>;
645 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
646 reg = <0xb025000 0x1000>;
647 status = "disabled";
648 };
650 frame@b026000 {
651 frame-number = <4>;
652 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
653 reg = <0xb026000 0x1000>;
654 status = "disabled";
655 };
657 frame@b027000 {
658 frame-number = <5>;
659 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
660 reg = <0xb027000 0x1000>;
661 status = "disabled";
662 };
664 frame@b028000 {
665 frame-number = <6>;
666 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
667 reg = <0xb028000 0x1000>;
668 status = "disabled";
669 };
670 };
672 spmi_bus: spmi@200f000 {
673 compatible = "qcom,spmi-pmic-arb";
674 reg = <0x200f000 0x001000>,
675 <0x2400000 0x400000>,
676 <0x2c00000 0x400000>,
677 <0x3800000 0x200000>,
678 <0x200a000 0x002100>;
679 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
680 interrupt-names = "periph_irq";
681 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
682 qcom,ee = <0>;
683 qcom,channel = <0>;
684 #address-cells = <2>;
685 #size-cells = <0>;
686 interrupt-controller;
687 #interrupt-cells = <4>;
688 };
690 rng@22000 {
691 compatible = "qcom,prng";
692 reg = <0x00022000 0x200>;
693 clocks = <&gcc GCC_PRNG_AHB_CLK>;
694 clock-names = "core";
695 };
697 qfprom: qfprom@5c000 {
698 compatible = "qcom,qfprom";
699 reg = <0x5c000 0x1000>;
700 #address-cells = <1>;
701 #size-cells = <1>;
702 tsens_caldata: caldata@d0 {
703 reg = <0xd0 0x8>;
704 };
705 tsens_calsel: calsel@ec {
706 reg = <0xec 0x4>;
707 };
708 };
710 tsens: thermal-sensor@4a8000 {
711 compatible = "qcom,msm8916-tsens";
712 reg = <0x4a8000 0x2000>;
713 nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
714 nvmem-cell-names = "calib", "calib_sel";
715 #thermal-sensor-cells = <1>;
716 };
718 apps_iommu: iommu@1ef0000 {
719 #address-cells = <1>;
720 #size-cells = <1>;
721 #iommu-cells = <1>;
722 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
723 ranges = <0 0x1e20000 0x40000>;
724 reg = <0x1ef0000 0x3000>;
725 clocks = <&gcc GCC_SMMU_CFG_CLK>,
726 <&gcc GCC_APSS_TCU_CLK>;
727 clock-names = "iface", "bus";
728 qcom,iommu-secure-id = <17>;
730 // mdp_0:
731 iommu-ctx@4000 {
732 compatible = "qcom,msm-iommu-v1-ns";
733 reg = <0x4000 0x1000>;
734 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
735 };
737 // venus_ns:
738 iommu-ctx@5000 {
739 compatible = "qcom,msm-iommu-v1-sec";
740 reg = <0x5000 0x1000>;
741 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
742 };
743 };
745 gpu_iommu: iommu@1f08000 {
746 #address-cells = <1>;
747 #size-cells = <1>;
748 #iommu-cells = <1>;
749 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
750 ranges = <0 0x1f08000 0x10000>;
751 clocks = <&gcc GCC_SMMU_CFG_CLK>,
752 <&gcc GCC_GFX_TCU_CLK>;
753 clock-names = "iface", "bus";
754 qcom,iommu-secure-id = <18>;
756 // gfx3d_user:
757 iommu-ctx@1000 {
758 compatible = "qcom,msm-iommu-v1-ns";
759 reg = <0x1000 0x1000>;
760 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
761 };
763 // gfx3d_priv:
764 iommu-ctx@2000 {
765 compatible = "qcom,msm-iommu-v1-ns";
766 reg = <0x2000 0x1000>;
767 interrupts = <GIC_SPI 242 0>;
768 };
769 };
771 gpu@1c00000 {
772 compatible = "qcom,adreno-306.0", "qcom,adreno";
773 reg = <0x01c00000 0x20000>;
774 reg-names = "kgsl_3d0_reg_memory";
775 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-names = "kgsl_3d0_irq";
777 clock-names =
778 "core",
779 "iface",
780 "mem",
781 "mem_iface",
782 "alt_mem_iface",
783 "gfx3d";
784 clocks =
785 <&gcc GCC_OXILI_GFX3D_CLK>,
786 <&gcc GCC_OXILI_AHB_CLK>,
787 <&gcc GCC_OXILI_GMEM_CLK>,
788 <&gcc GCC_BIMC_GFX_CLK>,
789 <&gcc GCC_BIMC_GPU_CLK>,
790 <&gcc GFX3D_CLK_SRC>;
791 power-domains = <&gcc OXILI_GDSC>;
792 operating-points-v2 = <&gpu_opp_table>;
793 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
794 };
796 mdss: mdss@1a00000 {
797 compatible = "qcom,mdss";
798 reg = <0x1a00000 0x1000>,
799 <0x1ac8000 0x3000>;
800 reg-names = "mdss_phys", "vbif_phys";
802 power-domains = <&gcc MDSS_GDSC>;
804 clocks = <&gcc GCC_MDSS_AHB_CLK>,
805 <&gcc GCC_MDSS_AXI_CLK>,
806 <&gcc GCC_MDSS_VSYNC_CLK>;
807 clock-names = "iface_clk",
808 "bus_clk",
809 "vsync_clk";
811 interrupts = <0 72 0>;
813 interrupt-controller;
814 #interrupt-cells = <1>;
816 #address-cells = <1>;
817 #size-cells = <1>;
818 ranges;
820 mdp: mdp@1a01000 {
821 compatible = "qcom,mdp5";
822 reg = <0x1a01000 0x89000>;
823 reg-names = "mdp_phys";
825 interrupt-parent = <&mdss>;
826 interrupts = <0 0>;
828 clocks = <&gcc GCC_MDSS_AHB_CLK>,
829 <&gcc GCC_MDSS_AXI_CLK>,
830 <&gcc GCC_MDSS_MDP_CLK>,
831 <&gcc GCC_MDSS_VSYNC_CLK>;
832 clock-names = "iface_clk",
833 "bus_clk",
834 "core_clk",
835 "vsync_clk";
837 iommus = <&apps_iommu 4>;
839 ports {
840 #address-cells = <1>;
841 #size-cells = <0>;
843 port@0 {
844 reg = <0>;
845 mdp5_intf1_out: endpoint {
846 remote-endpoint = <&dsi0_in>;
847 };
848 };
849 };
850 };
852 dsi0: dsi@1a98000 {
853 compatible = "qcom,mdss-dsi-ctrl";
854 reg = <0x1a98000 0x25c>;
855 reg-names = "dsi_ctrl";
857 interrupt-parent = <&mdss>;
858 interrupts = <4 0>;
860 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
861 <&gcc PCLK0_CLK_SRC>;
862 assigned-clock-parents = <&dsi_phy0 0>,
863 <&dsi_phy0 1>;
865 clocks = <&gcc GCC_MDSS_MDP_CLK>,
866 <&gcc GCC_MDSS_AHB_CLK>,
867 <&gcc GCC_MDSS_AXI_CLK>,
868 <&gcc GCC_MDSS_BYTE0_CLK>,
869 <&gcc GCC_MDSS_PCLK0_CLK>,
870 <&gcc GCC_MDSS_ESC0_CLK>;
871 clock-names = "mdp_core_clk",
872 "iface_clk",
873 "bus_clk",
874 "byte_clk",
875 "pixel_clk",
876 "core_clk";
877 phys = <&dsi_phy0>;
878 phy-names = "dsi-phy";
880 ports {
881 #address-cells = <1>;
882 #size-cells = <0>;
884 port@0 {
885 reg = <0>;
886 dsi0_in: endpoint {
887 remote-endpoint = <&mdp5_intf1_out>;
888 };
889 };
891 port@1 {
892 reg = <1>;
893 dsi0_out: endpoint {
894 };
895 };
896 };
897 };
899 dsi_phy0: dsi-phy@1a98300 {
900 compatible = "qcom,dsi-phy-28nm-lp";
901 reg = <0x1a98300 0xd4>,
902 <0x1a98500 0x280>,
903 <0x1a98780 0x30>;
904 reg-names = "dsi_pll",
905 "dsi_phy",
906 "dsi_phy_regulator";
908 #clock-cells = <1>;
909 #phy-cells = <0>;
911 clocks = <&gcc GCC_MDSS_AHB_CLK>;
912 clock-names = "iface_clk";
913 };
914 };
917 hexagon@4080000 {
918 compatible = "qcom,q6v5-pil";
919 reg = <0x04080000 0x100>,
920 <0x04020000 0x040>;
922 reg-names = "qdsp6", "rmb";
924 interrupts-extended = <&intc 0 24 1>,
925 <&hexagon_smp2p_in 0 0>,
926 <&hexagon_smp2p_in 1 0>,
927 <&hexagon_smp2p_in 2 0>,
928 <&hexagon_smp2p_in 3 0>;
929 interrupt-names = "wdog", "fatal", "ready",
930 "handover", "stop-ack";
932 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
933 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
934 <&gcc GCC_BOOT_ROM_AHB_CLK>,
935 <&xo_board>;
936 clock-names = "iface", "bus", "mem", "xo";
938 qcom,smem-states = <&hexagon_smp2p_out 0>;
939 qcom,smem-state-names = "stop";
941 resets = <&scm 0>;
942 reset-names = "mss_restart";
944 cx-supply = <&pm8916_s1>;
945 mx-supply = <&pm8916_l3>;
946 pll-supply = <&pm8916_l7>;
948 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
950 status = "disabled";
952 mba {
953 memory-region = <&mba_mem>;
954 };
956 mpss {
957 memory-region = <&mpss_mem>;
958 };
960 smd-edge {
961 interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
963 qcom,smd-edge = <0>;
964 qcom,ipc = <&apcs 8 12>;
965 qcom,remote-pid = <1>;
967 label = "hexagon";
968 };
969 };
971 pronto: wcnss@a21b000 {
972 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
973 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
974 reg-names = "ccu", "dxe", "pmu";
976 memory-region = <&wcnss_mem>;
978 interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
979 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
980 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
981 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
982 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
983 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
985 vddmx-supply = <&pm8916_l3>;
986 vddpx-supply = <&pm8916_l7>;
988 qcom,state = <&wcnss_smp2p_out 0>;
989 qcom,state-names = "stop";
991 pinctrl-names = "default";
992 pinctrl-0 = <&wcnss_pin_a>;
994 status = "disabled";
996 iris {
997 compatible = "qcom,wcn3620";
999 clocks = <&rpmcc RPM_SMD_RF_CLK2>;
1000 clock-names = "xo";
1002 vddxo-supply = <&pm8916_l7>;
1003 vddrfa-supply = <&pm8916_s3>;
1004 vddpa-supply = <&pm8916_l9>;
1005 vdddig-supply = <&pm8916_l5>;
1006 };
1008 smd-edge {
1009 interrupts = <0 142 1>;
1011 qcom,ipc = <&apcs 8 17>;
1012 qcom,smd-edge = <6>;
1013 qcom,remote-pid = <4>;
1015 label = "pronto";
1017 wcnss {
1018 compatible = "qcom,wcnss";
1019 qcom,smd-channels = "WCNSS_CTRL";
1021 qcom,mmio = <&pronto>;
1023 bt {
1024 compatible = "qcom,wcnss-bt";
1025 };
1027 wifi {
1028 compatible = "qcom,wcnss-wlan";
1030 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
1031 <0 146 IRQ_TYPE_LEVEL_HIGH>;
1032 interrupt-names = "tx", "rx";
1034 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1035 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1036 };
1037 };
1038 };
1039 };
1041 tpiu@820000 {
1042 compatible = "arm,coresight-tpiu", "arm,primecell";
1043 reg = <0x820000 0x1000>;
1045 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1046 clock-names = "apb_pclk", "atclk";
1048 port {
1049 tpiu_in: endpoint {
1050 slave-mode;
1051 remote-endpoint = <&replicator_out1>;
1052 };
1053 };
1054 };
1056 funnel@821000 {
1057 compatible = "arm,coresight-funnel", "arm,primecell";
1058 reg = <0x821000 0x1000>;
1060 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1061 clock-names = "apb_pclk", "atclk";
1063 ports {
1064 #address-cells = <1>;
1065 #size-cells = <0>;
1067 /*
1068 * Not described input ports:
1069 * 0 - connected to Resource and Power Manger CPU ETM
1070 * 1 - not-connected
1071 * 2 - connected to Modem CPU ETM
1072 * 3 - not-connected
1073 * 5 - not-connected
1074 * 6 - connected trought funnel to Wireless CPU ETM
1075 * 7 - connected to STM component
1076 */
1078 port@4 {
1079 reg = <4>;
1080 funnel0_in4: endpoint {
1081 slave-mode;
1082 remote-endpoint = <&funnel1_out>;
1083 };
1084 };
1085 port@8 {
1086 reg = <0>;
1087 funnel0_out: endpoint {
1088 remote-endpoint = <&etf_in>;
1089 };
1090 };
1091 };
1092 };
1094 replicator@824000 {
1095 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1096 reg = <0x824000 0x1000>;
1098 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1099 clock-names = "apb_pclk", "atclk";
1101 ports {
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1105 port@0 {
1106 reg = <0>;
1107 replicator_out0: endpoint {
1108 remote-endpoint = <&etr_in>;
1109 };
1110 };
1111 port@1 {
1112 reg = <1>;
1113 replicator_out1: endpoint {
1114 remote-endpoint = <&tpiu_in>;
1115 };
1116 };
1117 port@2 {
1118 reg = <0>;
1119 replicator_in: endpoint {
1120 slave-mode;
1121 remote-endpoint = <&etf_out>;
1122 };
1123 };
1124 };
1125 };
1127 etf@825000 {
1128 compatible = "arm,coresight-tmc", "arm,primecell";
1129 reg = <0x825000 0x1000>;
1131 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1132 clock-names = "apb_pclk", "atclk";
1134 ports {
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1138 port@0 {
1139 reg = <0>;
1140 etf_out: endpoint {
1141 slave-mode;
1142 remote-endpoint = <&funnel0_out>;
1143 };
1144 };
1145 port@1 {
1146 reg = <0>;
1147 etf_in: endpoint {
1148 remote-endpoint = <&replicator_in>;
1149 };
1150 };
1151 };
1152 };
1154 etr@826000 {
1155 compatible = "arm,coresight-tmc", "arm,primecell";
1156 reg = <0x826000 0x1000>;
1158 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1159 clock-names = "apb_pclk", "atclk";
1161 port {
1162 etr_in: endpoint {
1163 slave-mode;
1164 remote-endpoint = <&replicator_out0>;
1165 };
1166 };
1167 };
1169 funnel@841000 { /* APSS funnel only 4 inputs are used */
1170 compatible = "arm,coresight-funnel", "arm,primecell";
1171 reg = <0x841000 0x1000>;
1173 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1174 clock-names = "apb_pclk", "atclk";
1176 ports {
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1180 port@0 {
1181 reg = <0>;
1182 funnel1_in0: endpoint {
1183 slave-mode;
1184 remote-endpoint = <&etm0_out>;
1185 };
1186 };
1187 port@1 {
1188 reg = <1>;
1189 funnel1_in1: endpoint {
1190 slave-mode;
1191 remote-endpoint = <&etm1_out>;
1192 };
1193 };
1194 port@2 {
1195 reg = <2>;
1196 funnel1_in2: endpoint {
1197 slave-mode;
1198 remote-endpoint = <&etm2_out>;
1199 };
1200 };
1201 port@3 {
1202 reg = <3>;
1203 funnel1_in3: endpoint {
1204 slave-mode;
1205 remote-endpoint = <&etm3_out>;
1206 };
1207 };
1208 port@4 {
1209 reg = <0>;
1210 funnel1_out: endpoint {
1211 remote-endpoint = <&funnel0_in4>;
1212 };
1213 };
1214 };
1215 };
1217 debug@850000 {
1218 compatible = "arm,coresight-cpu-debug","arm,primecell";
1219 reg = <0x850000 0x1000>;
1220 clocks = <&rpmcc RPM_QDSS_CLK>;
1221 clock-names = "apb_pclk";
1222 cpu = <&CPU0>;
1223 };
1225 debug@852000 {
1226 compatible = "arm,coresight-cpu-debug","arm,primecell";
1227 reg = <0x852000 0x1000>;
1228 clocks = <&rpmcc RPM_QDSS_CLK>;
1229 clock-names = "apb_pclk";
1230 cpu = <&CPU1>;
1231 };
1233 debug@854000 {
1234 compatible = "arm,coresight-cpu-debug","arm,primecell";
1235 reg = <0x854000 0x1000>;
1236 clocks = <&rpmcc RPM_QDSS_CLK>;
1237 clock-names = "apb_pclk";
1238 cpu = <&CPU2>;
1239 };
1241 debug@856000 {
1242 compatible = "arm,coresight-cpu-debug","arm,primecell";
1243 reg = <0x856000 0x1000>;
1244 clocks = <&rpmcc RPM_QDSS_CLK>;
1245 clock-names = "apb_pclk";
1246 cpu = <&CPU3>;
1247 };
1249 etm@85c000 {
1250 compatible = "arm,coresight-etm4x", "arm,primecell";
1251 reg = <0x85c000 0x1000>;
1253 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1254 clock-names = "apb_pclk", "atclk";
1256 cpu = <&CPU0>;
1258 port {
1259 etm0_out: endpoint {
1260 remote-endpoint = <&funnel1_in0>;
1261 };
1262 };
1263 };
1265 etm@85d000 {
1266 compatible = "arm,coresight-etm4x", "arm,primecell";
1267 reg = <0x85d000 0x1000>;
1269 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1270 clock-names = "apb_pclk", "atclk";
1272 cpu = <&CPU1>;
1274 port {
1275 etm1_out: endpoint {
1276 remote-endpoint = <&funnel1_in1>;
1277 };
1278 };
1279 };
1281 etm@85e000 {
1282 compatible = "arm,coresight-etm4x", "arm,primecell";
1283 reg = <0x85e000 0x1000>;
1285 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1286 clock-names = "apb_pclk", "atclk";
1288 cpu = <&CPU2>;
1290 port {
1291 etm2_out: endpoint {
1292 remote-endpoint = <&funnel1_in2>;
1293 };
1294 };
1295 };
1297 etm@85f000 {
1298 compatible = "arm,coresight-etm4x", "arm,primecell";
1299 reg = <0x85f000 0x1000>;
1301 clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
1302 clock-names = "apb_pclk", "atclk";
1304 cpu = <&CPU3>;
1306 port {
1307 etm3_out: endpoint {
1308 remote-endpoint = <&funnel1_in3>;
1309 };
1310 };
1311 };
1313 venus: video-codec@1d00000 {
1314 compatible = "qcom,msm8916-venus";
1315 reg = <0x01d00000 0xff000>;
1316 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1317 power-domains = <&gcc VENUS_GDSC>;
1318 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1319 <&gcc GCC_VENUS0_AHB_CLK>,
1320 <&gcc GCC_VENUS0_AXI_CLK>;
1321 clock-names = "core", "iface", "bus";
1322 iommus = <&apps_iommu 5>;
1323 memory-region = <&venus_mem>;
1324 status = "okay";
1326 video-decoder {
1327 compatible = "venus-decoder";
1328 };
1330 video-encoder {
1331 compatible = "venus-encoder";
1332 };
1333 };
1334 };
1336 smd {
1337 compatible = "qcom,smd";
1339 rpm {
1340 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1341 qcom,ipc = <&apcs 8 0>;
1342 qcom,smd-edge = <15>;
1344 rpm_requests {
1345 compatible = "qcom,rpm-msm8916";
1346 qcom,smd-channels = "rpm_requests";
1348 rpmcc: qcom,rpmcc {
1349 compatible = "qcom,rpmcc-msm8916";
1350 #clock-cells = <1>;
1351 };
1353 smd_rpm_regulators: pm8916-regulators {
1354 compatible = "qcom,rpm-pm8916-regulators";
1356 pm8916_s1: s1 {};
1357 pm8916_s3: s3 {};
1358 pm8916_s4: s4 {};
1360 pm8916_l1: l1 {};
1361 pm8916_l2: l2 {};
1362 pm8916_l3: l3 {};
1363 pm8916_l4: l4 {};
1364 pm8916_l5: l5 {};
1365 pm8916_l6: l6 {};
1366 pm8916_l7: l7 {};
1367 pm8916_l8: l8 {};
1368 pm8916_l9: l9 {};
1369 pm8916_l10: l10 {};
1370 pm8916_l11: l11 {};
1371 pm8916_l12: l12 {};
1372 pm8916_l13: l13 {};
1373 pm8916_l14: l14 {};
1374 pm8916_l15: l15 {};
1375 pm8916_l16: l16 {};
1376 pm8916_l17: l17 {};
1377 pm8916_l18: l18 {};
1378 };
1379 };
1380 };
1381 };
1383 hexagon-smp2p {
1384 compatible = "qcom,smp2p";
1385 qcom,smem = <435>, <428>;
1387 interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
1389 qcom,ipc = <&apcs 8 14>;
1391 qcom,local-pid = <0>;
1392 qcom,remote-pid = <1>;
1394 hexagon_smp2p_out: master-kernel {
1395 qcom,entry-name = "master-kernel";
1397 #qcom,smem-state-cells = <1>;
1398 };
1400 hexagon_smp2p_in: slave-kernel {
1401 qcom,entry-name = "slave-kernel";
1403 interrupt-controller;
1404 #interrupt-cells = <2>;
1405 };
1406 };
1408 wcnss-smp2p {
1409 compatible = "qcom,smp2p";
1410 qcom,smem = <451>, <431>;
1412 interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
1414 qcom,ipc = <&apcs 8 18>;
1416 qcom,local-pid = <0>;
1417 qcom,remote-pid = <4>;
1419 wcnss_smp2p_out: master-kernel {
1420 qcom,entry-name = "master-kernel";
1422 #qcom,smem-state-cells = <1>;
1423 };
1425 wcnss_smp2p_in: slave-kernel {
1426 qcom,entry-name = "slave-kernel";
1428 interrupt-controller;
1429 #interrupt-cells = <2>;
1430 };
1431 };
1433 smsm {
1434 compatible = "qcom,smsm";
1436 #address-cells = <1>;
1437 #size-cells = <0>;
1439 qcom,ipc-1 = <&apcs 0 13>;
1440 qcom,ipc-6 = <&apcs 0 19>;
1442 apps_smsm: apps@0 {
1443 reg = <0>;
1445 #qcom,smem-state-cells = <1>;
1446 };
1448 hexagon_smsm: hexagon@1 {
1449 reg = <1>;
1450 interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
1452 interrupt-controller;
1453 #interrupt-cells = <2>;
1454 };
1456 wcnss_smsm: wcnss@6 {
1457 reg = <6>;
1458 interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
1460 interrupt-controller;
1461 #interrupt-cells = <2>;
1462 };
1463 };
1464 };
1466 #include "msm8916-pins.dtsi"