drivers/rtc/rtc-tegra.c

   1 /*
   2  * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
   3  *
   4  * Copyright (c) 2010, NVIDIA Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along
  17  * with this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/clk.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/slab.h>
  25 #include <linux/irq.h>
  26 #include <linux/io.h>
  27 #include <linux/delay.h>
  28 #include <linux/rtc.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm.h>
  31
  32 /* set to 1 = busy every eight 32kHz clocks during copy of sec+msec to AHB */
  33 #define TEGRA_RTC_REG_BUSY                      0x004
  34 #define TEGRA_RTC_REG_SECONDS                   0x008
  35 /* when msec is read, the seconds are buffered into shadow seconds. */
  36 #define TEGRA_RTC_REG_SHADOW_SECONDS            0x00c
  37 #define TEGRA_RTC_REG_MILLI_SECONDS             0x010
  38 #define TEGRA_RTC_REG_SECONDS_ALARM0            0x014
  39 #define TEGRA_RTC_REG_SECONDS_ALARM1            0x018
  40 #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0      0x01c
  41 #define TEGRA_RTC_REG_INTR_MASK                 0x028
  42 /* write 1 bits to clear status bits */
  43 #define TEGRA_RTC_REG_INTR_STATUS               0x02c
  44
  45 /* bits in INTR_MASK */
  46 #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM      (1<<4)
  47 #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM       (1<<3)
  48 #define TEGRA_RTC_INTR_MASK_MSEC_ALARM          (1<<2)
  49 #define TEGRA_RTC_INTR_MASK_SEC_ALARM1          (1<<1)
  50 #define TEGRA_RTC_INTR_MASK_SEC_ALARM0          (1<<0)
  51
  52 /* bits in INTR_STATUS */
  53 #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM    (1<<4)
  54 #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM     (1<<3)
  55 #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM        (1<<2)
  56 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1        (1<<1)
  57 #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0        (1<<0)
  58
  59 struct tegra_rtc_info {
  60         struct platform_device  *pdev;
  61         struct rtc_device       *rtc_dev;
  62         void __iomem            *rtc_base; /* NULL if not initialized. */
  63         struct clk              *clk;
  64         int                     tegra_rtc_irq; /* alarm and periodic irq */
  65         spinlock_t              tegra_rtc_lock;
  66 };
  67
  68 /* RTC hardware is busy when it is updating its values over AHB once
  69  * every eight 32kHz clocks (~250uS).
  70  * outside of these updates the CPU is free to write.
  71  * CPU is always free to read.
  72  */
  73 static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info)
  74 {
  75         return readl(info->rtc_base + TEGRA_RTC_REG_BUSY) & 1;
  76 }
  77
  78 /* Wait for hardware to be ready for writing.
  79  * This function tries to maximize the amount of time before the next update.
  80  * It does this by waiting for the RTC to become busy with its periodic update,
  81  * then returning once the RTC first becomes not busy.
  82  * This periodic update (where the seconds and milliseconds are copied to the
  83  * AHB side) occurs every eight 32kHz clocks (~250uS).
  84  * The behavior of this function allows us to make some assumptions without
  85  * introducing a race, because 250uS is plenty of time to read/write a value.
  86  */
  87 static int tegra_rtc_wait_while_busy(struct device *dev)
  88 {
  89         struct tegra_rtc_info *info = dev_get_drvdata(dev);
  90
  91         int retries = 500; /* ~490 us is the worst case, ~250 us is best. */
  92
  93         /* first wait for the RTC to become busy. this is when it
  94          * posts its updated seconds+msec registers to AHB side. */
  95         while (tegra_rtc_check_busy(info)) {
  96                 if (!retries--)
  97                         goto retry_failed;
  98                 udelay(1);
  99         }
 100
 101         /* now we have about 250 us to manipulate registers */
 102         return 0;
 103
 104 retry_failed:
 105         dev_err(dev, "write failed:retry count exceeded.\n");
 106         return -ETIMEDOUT;
 107 }
 108
 109 static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
 110 {
 111         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 112         unsigned long sec, msec;
 113         unsigned long sl_irq_flags;
 114
 115         /* RTC hardware copies seconds to shadow seconds when a read
 116          * of milliseconds occurs. use a lock to keep other threads out. */
 117         spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 118
 119         msec = readl(info->rtc_base + TEGRA_RTC_REG_MILLI_SECONDS);
 120         sec = readl(info->rtc_base + TEGRA_RTC_REG_SHADOW_SECONDS);
 121
 122         spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 123
 124         rtc_time_to_tm(sec, tm);
 125
 126         dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
 127                 sec,
 128                 tm->tm_mon + 1,
 129                 tm->tm_mday,
 130                 tm->tm_year + 1900,
 131                 tm->tm_hour,
 132                 tm->tm_min,
 133                 tm->tm_sec
 134         );
 135
 136         return 0;
 137 }
 138
 139 static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
 140 {
 141         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 142         unsigned long sec;
 143         int ret;
 144
 145         /* convert tm to seconds. */
 146         ret = rtc_valid_tm(tm);
 147         if (ret)
 148                 return ret;
 149
 150         rtc_tm_to_time(tm, &sec);
 151
 152         dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
 153                 sec,
 154                 tm->tm_mon+1,
 155                 tm->tm_mday,
 156                 tm->tm_year+1900,
 157                 tm->tm_hour,
 158                 tm->tm_min,
 159                 tm->tm_sec
 160         );
 161
 162         /* seconds only written if wait succeeded. */
 163         ret = tegra_rtc_wait_while_busy(dev);
 164         if (!ret)
 165                 writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS);
 166
 167         dev_vdbg(dev, "time read back as %d\n",
 168                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS));
 169
 170         return ret;
 171 }
 172
 173 static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 174 {
 175         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 176         unsigned long sec;
 177         unsigned tmp;
 178
 179         sec = readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 180
 181         if (sec == 0) {
 182                 /* alarm is disabled. */
 183                 alarm->enabled = 0;
 184                 alarm->time.tm_mon = -1;
 185                 alarm->time.tm_mday = -1;
 186                 alarm->time.tm_year = -1;
 187                 alarm->time.tm_hour = -1;
 188                 alarm->time.tm_min = -1;
 189                 alarm->time.tm_sec = -1;
 190         } else {
 191                 /* alarm is enabled. */
 192                 alarm->enabled = 1;
 193                 rtc_time_to_tm(sec, &alarm->time);
 194         }
 195
 196         tmp = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 197         alarm->pending = (tmp & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0;
 198
 199         return 0;
 200 }
 201
 202 static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 203 {
 204         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 205         unsigned status;
 206         unsigned long sl_irq_flags;
 207
 208         tegra_rtc_wait_while_busy(dev);
 209         spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 210
 211         /* read the original value, and OR in the flag. */
 212         status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 213         if (enabled)
 214                 status |= TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* set it */
 215         else
 216                 status &= ~TEGRA_RTC_INTR_MASK_SEC_ALARM0; /* clear it */
 217
 218         writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 219
 220         spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 221
 222         return 0;
 223 }
 224
 225 static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
 226 {
 227         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 228         unsigned long sec;
 229
 230         if (alarm->enabled)
 231                 rtc_tm_to_time(&alarm->time, &sec);
 232         else
 233                 sec = 0;
 234
 235         tegra_rtc_wait_while_busy(dev);
 236         writel(sec, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 237         dev_vdbg(dev, "alarm read back as %d\n",
 238                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
 239
 240         /* if successfully written and alarm is enabled ... */
 241         if (sec) {
 242                 tegra_rtc_alarm_irq_enable(dev, 1);
 243
 244                 dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
 245                         sec,
 246                         alarm->time.tm_mon+1,
 247                         alarm->time.tm_mday,
 248                         alarm->time.tm_year+1900,
 249                         alarm->time.tm_hour,
 250                         alarm->time.tm_min,
 251                         alarm->time.tm_sec);
 252         } else {
 253                 /* disable alarm if 0 or write error. */
 254                 dev_vdbg(dev, "alarm disabled\n");
 255                 tegra_rtc_alarm_irq_enable(dev, 0);
 256         }
 257
 258         return 0;
 259 }
 260
 261 static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
 262 {
 263         if (!dev || !dev->driver)
 264                 return 0;
 265
 266         seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
 267
 268         return 0;
 269 }
 270
 271 static irqreturn_t tegra_rtc_irq_handler(int irq, void *data)
 272 {
 273         struct device *dev = data;
 274         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 275         unsigned long events = 0;
 276         unsigned status;
 277         unsigned long sl_irq_flags;
 278
 279         status = readl(info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 280         if (status) {
 281                 /* clear the interrupt masks and status on any irq. */
 282                 tegra_rtc_wait_while_busy(dev);
 283                 spin_lock_irqsave(&info->tegra_rtc_lock, sl_irq_flags);
 284                 writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 285                 writel(status, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 286                 spin_unlock_irqrestore(&info->tegra_rtc_lock, sl_irq_flags);
 287         }
 288
 289         /* check if Alarm */
 290         if ((status & TEGRA_RTC_INTR_STATUS_SEC_ALARM0))
 291                 events |= RTC_IRQF | RTC_AF;
 292
 293         /* check if Periodic */
 294         if ((status & TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM))
 295                 events |= RTC_IRQF | RTC_PF;
 296
 297         rtc_update_irq(info->rtc_dev, 1, events);
 298
 299         return IRQ_HANDLED;
 300 }
 301
 302 static struct rtc_class_ops tegra_rtc_ops = {
 303         .read_time      = tegra_rtc_read_time,
 304         .set_time       = tegra_rtc_set_time,
 305         .read_alarm     = tegra_rtc_read_alarm,
 306         .set_alarm      = tegra_rtc_set_alarm,
 307         .proc           = tegra_rtc_proc,
 308         .alarm_irq_enable = tegra_rtc_alarm_irq_enable,
 309 };
 310
 311 static const struct of_device_id tegra_rtc_dt_match[] = {
 312         { .compatible = "nvidia,tegra20-rtc", },
 313         {}
 314 };
 315 MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match);
 316
 317 static int __init tegra_rtc_probe(struct platform_device *pdev)
 318 {
 319         struct tegra_rtc_info *info;
 320         struct resource *res;
 321         int ret;
 322
 323         info = devm_kzalloc(&pdev->dev, sizeof(struct tegra_rtc_info),
 324                 GFP_KERNEL);
 325         if (!info)
 326                 return -ENOMEM;
 327
 328         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 329         info->rtc_base = devm_ioremap_resource(&pdev->dev, res);
 330         if (IS_ERR(info->rtc_base))
 331                 return PTR_ERR(info->rtc_base);
 332
 333         info->tegra_rtc_irq = platform_get_irq(pdev, 0);
 334         if (info->tegra_rtc_irq <= 0)
 335                 return -EBUSY;
 336
 337         info->clk = devm_clk_get(&pdev->dev, NULL);
 338         if (IS_ERR(info->clk))
 339                 return PTR_ERR(info->clk);
 340
 341         ret = clk_prepare_enable(info->clk);
 342         if (ret < 0)
 343                 return ret;
 344
 345         /* set context info. */
 346         info->pdev = pdev;
 347         spin_lock_init(&info->tegra_rtc_lock);
 348
 349         platform_set_drvdata(pdev, info);
 350
 351         /* clear out the hardware. */
 352         writel(0, info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0);
 353         writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 354         writel(0, info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 355
 356         device_init_wakeup(&pdev->dev, 1);
 357
 358         info->rtc_dev = devm_rtc_device_register(&pdev->dev,
 359                                 dev_name(&pdev->dev), &tegra_rtc_ops,
 360                                 THIS_MODULE);
 361         if (IS_ERR(info->rtc_dev)) {
 362                 ret = PTR_ERR(info->rtc_dev);
 363                 dev_err(&pdev->dev, "Unable to register device (err=%d).\n",
 364                         ret);
 365                 goto disable_clk;
 366         }
 367
 368         ret = devm_request_irq(&pdev->dev, info->tegra_rtc_irq,
 369                         tegra_rtc_irq_handler, IRQF_TRIGGER_HIGH,
 370                         dev_name(&pdev->dev), &pdev->dev);
 371         if (ret) {
 372                 dev_err(&pdev->dev,
 373                         "Unable to request interrupt for device (err=%d).\n",
 374                         ret);
 375                 goto disable_clk;
 376         }
 377
 378         dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
 379
 380         return 0;
 381
 382 disable_clk:
 383         clk_disable_unprepare(info->clk);
 384         return ret;
 385 }
 386
 387 static int tegra_rtc_remove(struct platform_device *pdev)
 388 {
 389         struct tegra_rtc_info *info = platform_get_drvdata(pdev);
 390
 391         clk_disable_unprepare(info->clk);
 392
 393         return 0;
 394 }
 395
 396 #ifdef CONFIG_PM_SLEEP
 397 static int tegra_rtc_suspend(struct device *dev)
 398 {
 399         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 400
 401         tegra_rtc_wait_while_busy(dev);
 402
 403         /* only use ALARM0 as a wake source. */
 404         writel(0xffffffff, info->rtc_base + TEGRA_RTC_REG_INTR_STATUS);
 405         writel(TEGRA_RTC_INTR_STATUS_SEC_ALARM0,
 406                 info->rtc_base + TEGRA_RTC_REG_INTR_MASK);
 407
 408         dev_vdbg(dev, "alarm sec = %d\n",
 409                 readl(info->rtc_base + TEGRA_RTC_REG_SECONDS_ALARM0));
 410
 411         dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
 412                 device_may_wakeup(dev), info->tegra_rtc_irq);
 413
 414         /* leave the alarms on as a wake source. */
 415         if (device_may_wakeup(dev))
 416                 enable_irq_wake(info->tegra_rtc_irq);
 417
 418         return 0;
 419 }
 420
 421 static int tegra_rtc_resume(struct device *dev)
 422 {
 423         struct tegra_rtc_info *info = dev_get_drvdata(dev);
 424
 425         dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n",
 426                 device_may_wakeup(dev));
 427         /* alarms were left on as a wake source, turn them off. */
 428         if (device_may_wakeup(dev))
 429                 disable_irq_wake(info->tegra_rtc_irq);
 430
 431         return 0;
 432 }
 433 #endif
 434
 435 static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume);
 436
 437 static void tegra_rtc_shutdown(struct platform_device *pdev)
 438 {
 439         dev_vdbg(&pdev->dev, "disabling interrupts.\n");
 440         tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
 441 }
 442
 443 MODULE_ALIAS("platform:tegra_rtc");
 444 static struct platform_driver tegra_rtc_driver = {
 445         .remove         = tegra_rtc_remove,
 446         .shutdown       = tegra_rtc_shutdown,
 447         .driver         = {
 448                 .name   = "tegra_rtc",
 449                 .of_match_table = tegra_rtc_dt_match,
 450                 .pm     = &tegra_rtc_pm_ops,
 451         },
 452 };
 453
 454 module_platform_driver_probe(tegra_rtc_driver, tegra_rtc_probe);
 455
 456 MODULE_AUTHOR("Jon Mayo <jmayo@nvidia.com>");
 457 MODULE_DESCRIPTION("driver for Tegra internal RTC");
 458 MODULE_LICENSE("GPL");