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USB: add PID for FTDI based OpenDCC hardware
[linux/fpc-iii.git] / drivers / serial / bfin_5xx.c
blob511cbf68787782ce9b782f85ae51a0b5a80df5a6
1 /*
2 * Blackfin On-Chip Serial Driver
3 *
4 * Copyright 2006-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12 #define SUPPORT_SYSRQ
13 #endif
14
15 #include <linux/module.h>
16 #include <linux/ioport.h>
17 #include <linux/gfp.h>
18 #include <linux/io.h>
19 #include <linux/init.h>
20 #include <linux/console.h>
21 #include <linux/sysrq.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/serial_core.h>
26
27 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
28 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
29 #include <linux/kgdb.h>
30 #include <asm/irq_regs.h>
31 #endif
32
33 #include <asm/gpio.h>
34 #include <mach/bfin_serial_5xx.h>
35
36 #ifdef CONFIG_SERIAL_BFIN_DMA
37 #include <linux/dma-mapping.h>
38 #include <asm/io.h>
39 #include <asm/irq.h>
40 #include <asm/cacheflush.h>
41 #endif
42
43 #ifdef CONFIG_SERIAL_BFIN_MODULE
44 # undef CONFIG_EARLY_PRINTK
45 #endif
46
47 #ifdef CONFIG_SERIAL_BFIN_MODULE
48 # undef CONFIG_EARLY_PRINTK
49 #endif
50
51 /* UART name and device definitions */
52 #define BFIN_SERIAL_NAME "ttyBF"
53 #define BFIN_SERIAL_MAJOR 204
54 #define BFIN_SERIAL_MINOR 64
55
56 static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
57 static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
58
59 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
60 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
61
62 # ifndef CONFIG_SERIAL_BFIN_PIO
63 # error KGDB only support UART in PIO mode.
64 # endif
65
66 static int kgdboc_port_line;
67 static int kgdboc_break_enabled;
68 #endif
69 /*
70 * Setup for console. Argument comes from the menuconfig
71 */
72 #define DMA_RX_XCOUNT 512
73 #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
74
75 #define DMA_RX_FLUSH_JIFFIES (HZ / 50)
76
77 #ifdef CONFIG_SERIAL_BFIN_DMA
78 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
79 #else
80 static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
81 #endif
82
83 static void bfin_serial_reset_irda(struct uart_port *port);
84
85 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
86 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
87 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
88 {
89 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
90 if (uart->cts_pin < 0)
91 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
92
93 /* CTS PIN is negative assertive. */
94 if (UART_GET_CTS(uart))
95 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
96 else
97 return TIOCM_DSR | TIOCM_CAR;
98 }
99
100 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
101 {
102 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
103 if (uart->rts_pin < 0)
104 return;
105
106 /* RTS PIN is negative assertive. */
107 if (mctrl & TIOCM_RTS)
108 UART_ENABLE_RTS(uart);
109 else
110 UART_DISABLE_RTS(uart);
111 }
112
113 /*
114 * Handle any change of modem status signal.
115 */
116 static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
117 {
118 struct bfin_serial_port *uart = dev_id;
119 unsigned int status;
120
121 status = bfin_serial_get_mctrl(&uart->port);
122 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
123 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
124 uart->scts = 1;
125 UART_CLEAR_SCTS(uart);
126 UART_CLEAR_IER(uart, EDSSI);
127 #endif
128
129 return IRQ_HANDLED;
130 }
131 #else
132 static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
133 {
134 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
135 }
136
137 static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
138 {
139 }
140 #endif
141
142 /*
143 * interrupts are disabled on entry
144 */
145 static void bfin_serial_stop_tx(struct uart_port *port)
146 {
147 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
148 #ifdef CONFIG_SERIAL_BFIN_DMA
149 struct circ_buf *xmit = &uart->port.state->xmit;
150 #endif
151
152 while (!(UART_GET_LSR(uart) & TEMT))
153 cpu_relax();
154
155 #ifdef CONFIG_SERIAL_BFIN_DMA
156 disable_dma(uart->tx_dma_channel);
157 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
158 uart->port.icount.tx += uart->tx_count;
159 uart->tx_count = 0;
160 uart->tx_done = 1;
161 #else
162 #ifdef CONFIG_BF54x
163 /* Clear TFI bit */
164 UART_PUT_LSR(uart, TFI);
165 #endif
166 UART_CLEAR_IER(uart, ETBEI);
167 #endif
168 }
169
170 /*
171 * port is locked and interrupts are disabled
172 */
173 static void bfin_serial_start_tx(struct uart_port *port)
174 {
175 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
176 struct tty_struct *tty = uart->port.state->port.tty;
177
178 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
179 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
180 uart->scts = 0;
181 uart_handle_cts_change(&uart->port, uart->scts);
182 }
183 #endif
184
185 /*
186 * To avoid losting RX interrupt, we reset IR function
187 * before sending data.
188 */
189 if (tty->termios->c_line == N_IRDA)
190 bfin_serial_reset_irda(port);
191
192 #ifdef CONFIG_SERIAL_BFIN_DMA
193 if (uart->tx_done)
194 bfin_serial_dma_tx_chars(uart);
195 #else
196 UART_SET_IER(uart, ETBEI);
197 bfin_serial_tx_chars(uart);
198 #endif
199 }
200
201 /*
202 * Interrupts are enabled
203 */
204 static void bfin_serial_stop_rx(struct uart_port *port)
205 {
206 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
207
208 UART_CLEAR_IER(uart, ERBFI);
209 }
210
211 /*
212 * Set the modem control timer to fire immediately.
213 */
214 static void bfin_serial_enable_ms(struct uart_port *port)
215 {
216 }
217
218
219 #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
220 # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
221 # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
222 #else
223 # define UART_GET_ANOMALY_THRESHOLD(uart) 0
224 # define UART_SET_ANOMALY_THRESHOLD(uart, v)
225 #endif
226
227 #ifdef CONFIG_SERIAL_BFIN_PIO
228 static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
229 {
230 struct tty_struct *tty = NULL;
231 unsigned int status, ch, flg;
232 static struct timeval anomaly_start = { .tv_sec = 0 };
233
234 status = UART_GET_LSR(uart);
235 UART_CLEAR_LSR(uart);
236
237 ch = UART_GET_CHAR(uart);
238 uart->port.icount.rx++;
239
240 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
241 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
242 if (kgdb_connected && kgdboc_port_line == uart->port.line
243 && kgdboc_break_enabled)
244 if (ch == 0x3) {/* Ctrl + C */
245 kgdb_breakpoint();
246 return;
247 }
248
249 if (!uart->port.state || !uart->port.state->port.tty)
250 return;
251 #endif
252 tty = uart->port.state->port.tty;
253
254 if (ANOMALY_05000363) {
255 /* The BF533 (and BF561) family of processors have a nice anomaly
256 * where they continuously generate characters for a "single" break.
257 * We have to basically ignore this flood until the "next" valid
258 * character comes across. Due to the nature of the flood, it is
259 * not possible to reliably catch bytes that are sent too quickly
260 * after this break. So application code talking to the Blackfin
261 * which sends a break signal must allow at least 1.5 character
262 * times after the end of the break for things to stabilize. This
263 * timeout was picked as it must absolutely be larger than 1
264 * character time +/- some percent. So 1.5 sounds good. All other
265 * Blackfin families operate properly. Woo.
266 */
267 if (anomaly_start.tv_sec) {
268 struct timeval curr;
269 suseconds_t usecs;
270
271 if ((~ch & (~ch + 1)) & 0xff)
272 goto known_good_char;
273
274 do_gettimeofday(&curr);
275 if (curr.tv_sec - anomaly_start.tv_sec > 1)
276 goto known_good_char;
277
278 usecs = 0;
279 if (curr.tv_sec != anomaly_start.tv_sec)
280 usecs += USEC_PER_SEC;
281 usecs += curr.tv_usec - anomaly_start.tv_usec;
282
283 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
284 goto known_good_char;
285
286 if (ch)
287 anomaly_start.tv_sec = 0;
288 else
289 anomaly_start = curr;
290
291 return;
292
293 known_good_char:
294 status &= ~BI;
295 anomaly_start.tv_sec = 0;
296 }
297 }
298
299 if (status & BI) {
300 if (ANOMALY_05000363)
301 if (bfin_revid() < 5)
302 do_gettimeofday(&anomaly_start);
303 uart->port.icount.brk++;
304 if (uart_handle_break(&uart->port))
305 goto ignore_char;
306 status &= ~(PE | FE);
307 }
308 if (status & PE)
309 uart->port.icount.parity++;
310 if (status & OE)
311 uart->port.icount.overrun++;
312 if (status & FE)
313 uart->port.icount.frame++;
314
315 status &= uart->port.read_status_mask;
316
317 if (status & BI)
318 flg = TTY_BREAK;
319 else if (status & PE)
320 flg = TTY_PARITY;
321 else if (status & FE)
322 flg = TTY_FRAME;
323 else
324 flg = TTY_NORMAL;
325
326 if (uart_handle_sysrq_char(&uart->port, ch))
327 goto ignore_char;
328
329 uart_insert_char(&uart->port, status, OE, ch, flg);
330
331 ignore_char:
332 tty_flip_buffer_push(tty);
333 }
334
335 static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
336 {
337 struct circ_buf *xmit = &uart->port.state->xmit;
338
339 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
340 #ifdef CONFIG_BF54x
341 /* Clear TFI bit */
342 UART_PUT_LSR(uart, TFI);
343 #endif
344 /* Anomaly notes:
345 * 05000215 - we always clear ETBEI within last UART TX
346 * interrupt to end a string. It is always set
347 * when start a new tx.
348 */
349 UART_CLEAR_IER(uart, ETBEI);
350 return;
351 }
352
353 if (uart->port.x_char) {
354 UART_PUT_CHAR(uart, uart->port.x_char);
355 uart->port.icount.tx++;
356 uart->port.x_char = 0;
357 }
358
359 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
360 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
361 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
362 uart->port.icount.tx++;
363 SSYNC();
364 }
365
366 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
367 uart_write_wakeup(&uart->port);
368 }
369
370 static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
371 {
372 struct bfin_serial_port *uart = dev_id;
373
374 spin_lock(&uart->port.lock);
375 while (UART_GET_LSR(uart) & DR)
376 bfin_serial_rx_chars(uart);
377 spin_unlock(&uart->port.lock);
378
379 return IRQ_HANDLED;
380 }
381
382 static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
383 {
384 struct bfin_serial_port *uart = dev_id;
385
386 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
387 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
388 uart->scts = 0;
389 uart_handle_cts_change(&uart->port, uart->scts);
390 }
391 #endif
392 spin_lock(&uart->port.lock);
393 if (UART_GET_LSR(uart) & THRE)
394 bfin_serial_tx_chars(uart);
395 spin_unlock(&uart->port.lock);
396
397 return IRQ_HANDLED;
398 }
399 #endif
400
401 #ifdef CONFIG_SERIAL_BFIN_DMA
402 static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
403 {
404 struct circ_buf *xmit = &uart->port.state->xmit;
405
406 uart->tx_done = 0;
407
408 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
409 uart->tx_count = 0;
410 uart->tx_done = 1;
411 return;
412 }
413
414 if (uart->port.x_char) {
415 UART_PUT_CHAR(uart, uart->port.x_char);
416 uart->port.icount.tx++;
417 uart->port.x_char = 0;
418 }
419
420 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
421 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
422 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
423 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
424 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
425 set_dma_config(uart->tx_dma_channel,
426 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
427 INTR_ON_BUF,
428 DIMENSION_LINEAR,
429 DATA_SIZE_8,
430 DMA_SYNC_RESTART));
431 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
432 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
433 set_dma_x_modify(uart->tx_dma_channel, 1);
434 SSYNC();
435 enable_dma(uart->tx_dma_channel);
436
437 UART_SET_IER(uart, ETBEI);
438 }
439
440 static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
441 {
442 struct tty_struct *tty = uart->port.state->port.tty;
443 int i, flg, status;
444
445 status = UART_GET_LSR(uart);
446 UART_CLEAR_LSR(uart);
447
448 uart->port.icount.rx +=
449 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
450 UART_XMIT_SIZE);
451
452 if (status & BI) {
453 uart->port.icount.brk++;
454 if (uart_handle_break(&uart->port))
455 goto dma_ignore_char;
456 status &= ~(PE | FE);
457 }
458 if (status & PE)
459 uart->port.icount.parity++;
460 if (status & OE)
461 uart->port.icount.overrun++;
462 if (status & FE)
463 uart->port.icount.frame++;
464
465 status &= uart->port.read_status_mask;
466
467 if (status & BI)
468 flg = TTY_BREAK;
469 else if (status & PE)
470 flg = TTY_PARITY;
471 else if (status & FE)
472 flg = TTY_FRAME;
473 else
474 flg = TTY_NORMAL;
475
476 for (i = uart->rx_dma_buf.tail; ; i++) {
477 if (i >= UART_XMIT_SIZE)
478 i = 0;
479 if (i == uart->rx_dma_buf.head)
480 break;
481 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
482 uart_insert_char(&uart->port, status, OE,
483 uart->rx_dma_buf.buf[i], flg);
484 }
485
486 dma_ignore_char:
487 tty_flip_buffer_push(tty);
488 }
489
490 void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
491 {
492 int x_pos, pos;
493
494 dma_disable_irq(uart->tx_dma_channel);
495 dma_disable_irq(uart->rx_dma_channel);
496 spin_lock_bh(&uart->port.lock);
497
498 /* 2D DMA RX buffer ring is used. Because curr_y_count and
499 * curr_x_count can't be read as an atomic operation,
500 * curr_y_count should be read before curr_x_count. When
501 * curr_x_count is read, curr_y_count may already indicate
502 * next buffer line. But, the position calculated here is
503 * still indicate the old line. The wrong position data may
504 * be smaller than current buffer tail, which cause garbages
505 * are received if it is not prohibit.
506 */
507 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
508 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
509 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
510 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
511 uart->rx_dma_nrows = 0;
512 x_pos = DMA_RX_XCOUNT - x_pos;
513 if (x_pos == DMA_RX_XCOUNT)
514 x_pos = 0;
515
516 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
517 /* Ignore receiving data if new position is in the same line of
518 * current buffer tail and small.
519 */
520 if (pos > uart->rx_dma_buf.tail ||
521 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
522 uart->rx_dma_buf.head = pos;
523 bfin_serial_dma_rx_chars(uart);
524 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
525 }
526
527 spin_unlock_bh(&uart->port.lock);
528 dma_enable_irq(uart->tx_dma_channel);
529 dma_enable_irq(uart->rx_dma_channel);
530
531 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
532 }
533
534 static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
535 {
536 struct bfin_serial_port *uart = dev_id;
537 struct circ_buf *xmit = &uart->port.state->xmit;
538
539 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
540 if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
541 uart->scts = 0;
542 uart_handle_cts_change(&uart->port, uart->scts);
543 }
544 #endif
545
546 spin_lock(&uart->port.lock);
547 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
548 disable_dma(uart->tx_dma_channel);
549 clear_dma_irqstat(uart->tx_dma_channel);
550 /* Anomaly notes:
551 * 05000215 - we always clear ETBEI within last UART TX
552 * interrupt to end a string. It is always set
553 * when start a new tx.
554 */
555 UART_CLEAR_IER(uart, ETBEI);
556 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
557 uart->port.icount.tx += uart->tx_count;
558
559 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
560 uart_write_wakeup(&uart->port);
561
562 bfin_serial_dma_tx_chars(uart);
563 }
564
565 spin_unlock(&uart->port.lock);
566 return IRQ_HANDLED;
567 }
568
569 static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
570 {
571 struct bfin_serial_port *uart = dev_id;
572 unsigned short irqstat;
573 int x_pos, pos;
574
575 spin_lock(&uart->port.lock);
576 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
577 clear_dma_irqstat(uart->rx_dma_channel);
578
579 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
580 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
581 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
582 if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
583 uart->rx_dma_nrows = 0;
584
585 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
586 if (pos > uart->rx_dma_buf.tail ||
587 uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
588 uart->rx_dma_buf.head = pos;
589 bfin_serial_dma_rx_chars(uart);
590 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
591 }
592
593 spin_unlock(&uart->port.lock);
594
595 return IRQ_HANDLED;
596 }
597 #endif
598
599 /*
600 * Return TIOCSER_TEMT when transmitter is not busy.
601 */
602 static unsigned int bfin_serial_tx_empty(struct uart_port *port)
603 {
604 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
605 unsigned short lsr;
606
607 lsr = UART_GET_LSR(uart);
608 if (lsr & TEMT)
609 return TIOCSER_TEMT;
610 else
611 return 0;
612 }
613
614 static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
615 {
616 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
617 u16 lcr = UART_GET_LCR(uart);
618 if (break_state)
619 lcr |= SB;
620 else
621 lcr &= ~SB;
622 UART_PUT_LCR(uart, lcr);
623 SSYNC();
624 }
625
626 static int bfin_serial_startup(struct uart_port *port)
627 {
628 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
629
630 #ifdef CONFIG_SERIAL_BFIN_DMA
631 dma_addr_t dma_handle;
632
633 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
634 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
635 return -EBUSY;
636 }
637
638 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
639 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
640 free_dma(uart->rx_dma_channel);
641 return -EBUSY;
642 }
643
644 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
645 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
646
647 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
648 uart->rx_dma_buf.head = 0;
649 uart->rx_dma_buf.tail = 0;
650 uart->rx_dma_nrows = 0;
651
652 set_dma_config(uart->rx_dma_channel,
653 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
654 INTR_ON_ROW, DIMENSION_2D,
655 DATA_SIZE_8,
656 DMA_SYNC_RESTART));
657 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
658 set_dma_x_modify(uart->rx_dma_channel, 1);
659 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
660 set_dma_y_modify(uart->rx_dma_channel, 1);
661 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
662 enable_dma(uart->rx_dma_channel);
663
664 uart->rx_dma_timer.data = (unsigned long)(uart);
665 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
666 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
667 add_timer(&(uart->rx_dma_timer));
668 #else
669 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
670 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
671 if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
672 kgdboc_break_enabled = 0;
673 else {
674 # endif
675 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
676 "BFIN_UART_RX", uart)) {
677 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
678 return -EBUSY;
679 }
680
681 if (request_irq
682 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
683 "BFIN_UART_TX", uart)) {
684 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
685 free_irq(uart->port.irq, uart);
686 return -EBUSY;
687 }
688
689 # ifdef CONFIG_BF54x
690 {
691 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
692
693 switch (uart->port.irq) {
694 case IRQ_UART3_RX:
695 uart_dma_ch_rx = CH_UART3_RX;
696 uart_dma_ch_tx = CH_UART3_TX;
697 break;
698 case IRQ_UART2_RX:
699 uart_dma_ch_rx = CH_UART2_RX;
700 uart_dma_ch_tx = CH_UART2_TX;
701 break;
702 default:
703 uart_dma_ch_rx = uart_dma_ch_tx = 0;
704 break;
705 };
706
707 if (uart_dma_ch_rx &&
708 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
709 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
710 free_irq(uart->port.irq, uart);
711 free_irq(uart->port.irq + 1, uart);
712 return -EBUSY;
713 }
714 if (uart_dma_ch_tx &&
715 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
716 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
717 free_dma(uart_dma_ch_rx);
718 free_irq(uart->port.irq, uart);
719 free_irq(uart->port.irq + 1, uart);
720 return -EBUSY;
721 }
722 }
723 # endif
724 # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
725 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
726 }
727 # endif
728 #endif
729
730 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
731 if (uart->cts_pin >= 0) {
732 if (request_irq(gpio_to_irq(uart->cts_pin),
733 bfin_serial_mctrl_cts_int,
734 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
735 IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
736 uart->cts_pin = -1;
737 pr_info("Unable to attach BlackFin UART CTS interrupt.\
738 So, disable it.\n");
739 }
740 }
741 if (uart->rts_pin >= 0) {
742 gpio_request(uart->rts_pin, DRIVER_NAME);
743 gpio_direction_output(uart->rts_pin, 0);
744 }
745 #endif
746 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
747 if (request_irq(uart->status_irq,
748 bfin_serial_mctrl_cts_int,
749 IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
750 pr_info("Unable to attach BlackFin UART Modem \
751 Status interrupt.\n");
752 }
753
754 /* CTS RTS PINs are negative assertive. */
755 UART_PUT_MCR(uart, ACTS);
756 UART_SET_IER(uart, EDSSI);
757 #endif
758
759 UART_SET_IER(uart, ERBFI);
760 return 0;
761 }
762
763 static void bfin_serial_shutdown(struct uart_port *port)
764 {
765 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
766
767 #ifdef CONFIG_SERIAL_BFIN_DMA
768 disable_dma(uart->tx_dma_channel);
769 free_dma(uart->tx_dma_channel);
770 disable_dma(uart->rx_dma_channel);
771 free_dma(uart->rx_dma_channel);
772 del_timer(&(uart->rx_dma_timer));
773 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
774 #else
775 #ifdef CONFIG_BF54x
776 switch (uart->port.irq) {
777 case IRQ_UART3_RX:
778 free_dma(CH_UART3_RX);
779 free_dma(CH_UART3_TX);
780 break;
781 case IRQ_UART2_RX:
782 free_dma(CH_UART2_RX);
783 free_dma(CH_UART2_TX);
784 break;
785 default:
786 break;
787 };
788 #endif
789 free_irq(uart->port.irq, uart);
790 free_irq(uart->port.irq+1, uart);
791 #endif
792
793 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
794 if (uart->cts_pin >= 0)
795 free_irq(gpio_to_irq(uart->cts_pin), uart);
796 if (uart->rts_pin >= 0)
797 gpio_free(uart->rts_pin);
798 #endif
799 #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
800 if (UART_GET_IER(uart) & EDSSI)
801 free_irq(uart->status_irq, uart);
802 #endif
803 }
804
805 static void
806 bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
807 struct ktermios *old)
808 {
809 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
810 unsigned long flags;
811 unsigned int baud, quot;
812 unsigned short val, ier, lcr = 0;
813
814 switch (termios->c_cflag & CSIZE) {
815 case CS8:
816 lcr = WLS(8);
817 break;
818 case CS7:
819 lcr = WLS(7);
820 break;
821 case CS6:
822 lcr = WLS(6);
823 break;
824 case CS5:
825 lcr = WLS(5);
826 break;
827 default:
828 printk(KERN_ERR "%s: word lengh not supported\n",
829 __func__);
830 }
831
832 /* Anomaly notes:
833 * 05000231 - STOP bit is always set to 1 whatever the user is set.
834 */
835 if (termios->c_cflag & CSTOPB) {
836 if (ANOMALY_05000231)
837 printk(KERN_WARNING "STOP bits other than 1 is not "
838 "supported in case of anomaly 05000231.\n");
839 else
840 lcr |= STB;
841 }
842 if (termios->c_cflag & PARENB)
843 lcr |= PEN;
844 if (!(termios->c_cflag & PARODD))
845 lcr |= EPS;
846 if (termios->c_cflag & CMSPAR)
847 lcr |= STP;
848
849 port->read_status_mask = OE;
850 if (termios->c_iflag & INPCK)
851 port->read_status_mask |= (FE | PE);
852 if (termios->c_iflag & (BRKINT | PARMRK))
853 port->read_status_mask |= BI;
854
855 /*
856 * Characters to ignore
857 */
858 port->ignore_status_mask = 0;
859 if (termios->c_iflag & IGNPAR)
860 port->ignore_status_mask |= FE | PE;
861 if (termios->c_iflag & IGNBRK) {
862 port->ignore_status_mask |= BI;
863 /*
864 * If we're ignoring parity and break indicators,
865 * ignore overruns too (for real raw support).
866 */
867 if (termios->c_iflag & IGNPAR)
868 port->ignore_status_mask |= OE;
869 }
870
871 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
872 quot = uart_get_divisor(port, baud);
873
874 /* If discipline is not IRDA, apply ANOMALY_05000230 */
875 if (termios->c_line != N_IRDA)
876 quot -= ANOMALY_05000230;
877
878 spin_lock_irqsave(&uart->port.lock, flags);
879
880 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
881
882 /* Disable UART */
883 ier = UART_GET_IER(uart);
884 UART_DISABLE_INTS(uart);
885
886 /* Set DLAB in LCR to Access DLL and DLH */
887 UART_SET_DLAB(uart);
888
889 UART_PUT_DLL(uart, quot & 0xFF);
890 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
891 SSYNC();
892
893 /* Clear DLAB in LCR to Access THR RBR IER */
894 UART_CLEAR_DLAB(uart);
895
896 UART_PUT_LCR(uart, lcr);
897
898 /* Enable UART */
899 UART_ENABLE_INTS(uart, ier);
900
901 val = UART_GET_GCTL(uart);
902 val |= UCEN;
903 UART_PUT_GCTL(uart, val);
904
905 /* Port speed changed, update the per-port timeout. */
906 uart_update_timeout(port, termios->c_cflag, baud);
907
908 spin_unlock_irqrestore(&uart->port.lock, flags);
909 }
910
911 static const char *bfin_serial_type(struct uart_port *port)
912 {
913 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
914
915 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
916 }
917
918 /*
919 * Release the memory region(s) being used by 'port'.
920 */
921 static void bfin_serial_release_port(struct uart_port *port)
922 {
923 }
924
925 /*
926 * Request the memory region(s) being used by 'port'.
927 */
928 static int bfin_serial_request_port(struct uart_port *port)
929 {
930 return 0;
931 }
932
933 /*
934 * Configure/autoconfigure the port.
935 */
936 static void bfin_serial_config_port(struct uart_port *port, int flags)
937 {
938 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
939
940 if (flags & UART_CONFIG_TYPE &&
941 bfin_serial_request_port(&uart->port) == 0)
942 uart->port.type = PORT_BFIN;
943 }
944
945 /*
946 * Verify the new serial_struct (for TIOCSSERIAL).
947 * The only change we allow are to the flags and type, and
948 * even then only between PORT_BFIN and PORT_UNKNOWN
949 */
950 static int
951 bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
952 {
953 return 0;
954 }
955
956 /*
957 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
958 * In other cases, disable IrDA function.
959 */
960 static void bfin_serial_set_ldisc(struct uart_port *port)
961 {
962 int line = port->line;
963 unsigned short val;
964
965 if (line >= port->state->port.tty->driver->num)
966 return;
967
968 switch (port->state->port.tty->termios->c_line) {
969 case N_IRDA:
970 val = UART_GET_GCTL(&bfin_serial_ports[line]);
971 val |= (IREN | RPOLC);
972 UART_PUT_GCTL(&bfin_serial_ports[line], val);
973 break;
974 default:
975 val = UART_GET_GCTL(&bfin_serial_ports[line]);
976 val &= ~(IREN | RPOLC);
977 UART_PUT_GCTL(&bfin_serial_ports[line], val);
978 }
979 }
980
981 static void bfin_serial_reset_irda(struct uart_port *port)
982 {
983 int line = port->line;
984 unsigned short val;
985
986 val = UART_GET_GCTL(&bfin_serial_ports[line]);
987 val &= ~(IREN | RPOLC);
988 UART_PUT_GCTL(&bfin_serial_ports[line], val);
989 SSYNC();
990 val |= (IREN | RPOLC);
991 UART_PUT_GCTL(&bfin_serial_ports[line], val);
992 SSYNC();
993 }
994
995 #ifdef CONFIG_CONSOLE_POLL
996 /* Anomaly notes:
997 * 05000099 - Because we only use THRE in poll_put and DR in poll_get,
998 * losing other bits of UART_LSR is not a problem here.
999 */
1000 static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
1001 {
1002 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1003
1004 while (!(UART_GET_LSR(uart) & THRE))
1005 cpu_relax();
1006
1007 UART_CLEAR_DLAB(uart);
1008 UART_PUT_CHAR(uart, (unsigned char)chr);
1009 }
1010
1011 static int bfin_serial_poll_get_char(struct uart_port *port)
1012 {
1013 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1014 unsigned char chr;
1015
1016 while (!(UART_GET_LSR(uart) & DR))
1017 cpu_relax();
1018
1019 UART_CLEAR_DLAB(uart);
1020 chr = UART_GET_CHAR(uart);
1021
1022 return chr;
1023 }
1024 #endif
1025
1026 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1027 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1028 static void bfin_kgdboc_port_shutdown(struct uart_port *port)
1029 {
1030 if (kgdboc_break_enabled) {
1031 kgdboc_break_enabled = 0;
1032 bfin_serial_shutdown(port);
1033 }
1034 }
1035
1036 static int bfin_kgdboc_port_startup(struct uart_port *port)
1037 {
1038 kgdboc_port_line = port->line;
1039 kgdboc_break_enabled = !bfin_serial_startup(port);
1040 return 0;
1041 }
1042 #endif
1043
1044 static struct uart_ops bfin_serial_pops = {
1045 .tx_empty = bfin_serial_tx_empty,
1046 .set_mctrl = bfin_serial_set_mctrl,
1047 .get_mctrl = bfin_serial_get_mctrl,
1048 .stop_tx = bfin_serial_stop_tx,
1049 .start_tx = bfin_serial_start_tx,
1050 .stop_rx = bfin_serial_stop_rx,
1051 .enable_ms = bfin_serial_enable_ms,
1052 .break_ctl = bfin_serial_break_ctl,
1053 .startup = bfin_serial_startup,
1054 .shutdown = bfin_serial_shutdown,
1055 .set_termios = bfin_serial_set_termios,
1056 .set_ldisc = bfin_serial_set_ldisc,
1057 .type = bfin_serial_type,
1058 .release_port = bfin_serial_release_port,
1059 .request_port = bfin_serial_request_port,
1060 .config_port = bfin_serial_config_port,
1061 .verify_port = bfin_serial_verify_port,
1062 #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
1063 defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
1064 .kgdboc_port_startup = bfin_kgdboc_port_startup,
1065 .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown,
1066 #endif
1067 #ifdef CONFIG_CONSOLE_POLL
1068 .poll_put_char = bfin_serial_poll_put_char,
1069 .poll_get_char = bfin_serial_poll_get_char,
1070 #endif
1071 };
1072
1073 static void __init bfin_serial_hw_init(void)
1074 {
1075 #ifdef CONFIG_SERIAL_BFIN_UART0
1076 peripheral_request(P_UART0_TX, DRIVER_NAME);
1077 peripheral_request(P_UART0_RX, DRIVER_NAME);
1078 #endif
1079
1080 #ifdef CONFIG_SERIAL_BFIN_UART1
1081 peripheral_request(P_UART1_TX, DRIVER_NAME);
1082 peripheral_request(P_UART1_RX, DRIVER_NAME);
1083
1084 # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x)
1085 peripheral_request(P_UART1_RTS, DRIVER_NAME);
1086 peripheral_request(P_UART1_CTS, DRIVER_NAME);
1087 # endif
1088 #endif
1089
1090 #ifdef CONFIG_SERIAL_BFIN_UART2
1091 peripheral_request(P_UART2_TX, DRIVER_NAME);
1092 peripheral_request(P_UART2_RX, DRIVER_NAME);
1093 #endif
1094
1095 #ifdef CONFIG_SERIAL_BFIN_UART3
1096 peripheral_request(P_UART3_TX, DRIVER_NAME);
1097 peripheral_request(P_UART3_RX, DRIVER_NAME);
1098
1099 # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x)
1100 peripheral_request(P_UART3_RTS, DRIVER_NAME);
1101 peripheral_request(P_UART3_CTS, DRIVER_NAME);
1102 # endif
1103 #endif
1104 }
1105
1106 static void __init bfin_serial_init_ports(void)
1107 {
1108 static int first = 1;
1109 int i;
1110
1111 if (!first)
1112 return;
1113 first = 0;
1114
1115 bfin_serial_hw_init();
1116
1117 for (i = 0; i < nr_active_ports; i++) {
1118 spin_lock_init(&bfin_serial_ports[i].port.lock);
1119 bfin_serial_ports[i].port.uartclk = get_sclk();
1120 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
1121 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
1122 bfin_serial_ports[i].port.line = i;
1123 bfin_serial_ports[i].port.iotype = UPIO_MEM;
1124 bfin_serial_ports[i].port.membase =
1125 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
1126 bfin_serial_ports[i].port.mapbase =
1127 bfin_serial_resource[i].uart_base_addr;
1128 bfin_serial_ports[i].port.irq =
1129 bfin_serial_resource[i].uart_irq;
1130 bfin_serial_ports[i].status_irq =
1131 bfin_serial_resource[i].uart_status_irq;
1132 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
1133 #ifdef CONFIG_SERIAL_BFIN_DMA
1134 bfin_serial_ports[i].tx_done = 1;
1135 bfin_serial_ports[i].tx_count = 0;
1136 bfin_serial_ports[i].tx_dma_channel =
1137 bfin_serial_resource[i].uart_tx_dma_channel;
1138 bfin_serial_ports[i].rx_dma_channel =
1139 bfin_serial_resource[i].uart_rx_dma_channel;
1140 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
1141 #endif
1142 #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1143 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1144 bfin_serial_ports[i].cts_pin =
1145 bfin_serial_resource[i].uart_cts_pin;
1146 bfin_serial_ports[i].rts_pin =
1147 bfin_serial_resource[i].uart_rts_pin;
1148 #endif
1149 }
1150 }
1151
1152 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1153 /*
1154 * If the port was already initialised (eg, by a boot loader),
1155 * try to determine the current setup.
1156 */
1157 static void __init
1158 bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
1159 int *parity, int *bits)
1160 {
1161 unsigned short status;
1162
1163 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
1164 if (status == (ERBFI | ETBEI)) {
1165 /* ok, the port was enabled */
1166 u16 lcr, dlh, dll;
1167
1168 lcr = UART_GET_LCR(uart);
1169
1170 *parity = 'n';
1171 if (lcr & PEN) {
1172 if (lcr & EPS)
1173 *parity = 'e';
1174 else
1175 *parity = 'o';
1176 }
1177 switch (lcr & 0x03) {
1178 case 0: *bits = 5; break;
1179 case 1: *bits = 6; break;
1180 case 2: *bits = 7; break;
1181 case 3: *bits = 8; break;
1182 }
1183 /* Set DLAB in LCR to Access DLL and DLH */
1184 UART_SET_DLAB(uart);
1185
1186 dll = UART_GET_DLL(uart);
1187 dlh = UART_GET_DLH(uart);
1188
1189 /* Clear DLAB in LCR to Access THR RBR IER */
1190 UART_CLEAR_DLAB(uart);
1191
1192 *baud = get_sclk() / (16*(dll | dlh << 8));
1193 }
1194 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
1195 }
1196
1197 static struct uart_driver bfin_serial_reg;
1198
1199 static int __init
1200 bfin_serial_console_setup(struct console *co, char *options)
1201 {
1202 struct bfin_serial_port *uart;
1203 int baud = 57600;
1204 int bits = 8;
1205 int parity = 'n';
1206 # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
1207 defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
1208 int flow = 'r';
1209 # else
1210 int flow = 'n';
1211 # endif
1212
1213 /*
1214 * Check whether an invalid uart number has been specified, and
1215 * if so, search for the first available port that does have
1216 * console support.
1217 */
1218 if (co->index == -1 || co->index >= nr_active_ports)
1219 co->index = 0;
1220 uart = &bfin_serial_ports[co->index];
1221
1222 if (options)
1223 uart_parse_options(options, &baud, &parity, &bits, &flow);
1224 else
1225 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1226
1227 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
1228 }
1229 #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1230 defined (CONFIG_EARLY_PRINTK) */
1231
1232 #ifdef CONFIG_SERIAL_BFIN_CONSOLE
1233 static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1234 {
1235 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1236 while (!(UART_GET_LSR(uart) & THRE))
1237 barrier();
1238 UART_PUT_CHAR(uart, ch);
1239 SSYNC();
1240 }
1241
1242 /*
1243 * Interrupts are disabled on entering
1244 */
1245 static void
1246 bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1247 {
1248 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1249 unsigned long flags;
1250
1251 spin_lock_irqsave(&uart->port.lock, flags);
1252 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1253 spin_unlock_irqrestore(&uart->port.lock, flags);
1254
1255 }
1256
1257 static struct console bfin_serial_console = {
1258 .name = BFIN_SERIAL_NAME,
1259 .write = bfin_serial_console_write,
1260 .device = uart_console_device,
1261 .setup = bfin_serial_console_setup,
1262 .flags = CON_PRINTBUFFER,
1263 .index = -1,
1264 .data = &bfin_serial_reg,
1265 };
1266
1267 static int __init bfin_serial_rs_console_init(void)
1268 {
1269 bfin_serial_init_ports();
1270 register_console(&bfin_serial_console);
1271
1272 return 0;
1273 }
1274 console_initcall(bfin_serial_rs_console_init);
1275
1276 #define BFIN_SERIAL_CONSOLE &bfin_serial_console
1277 #else
1278 #define BFIN_SERIAL_CONSOLE NULL
1279 #endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1280
1281
1282 #ifdef CONFIG_EARLY_PRINTK
1283 static __init void early_serial_putc(struct uart_port *port, int ch)
1284 {
1285 unsigned timeout = 0xffff;
1286 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1287
1288 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1289 cpu_relax();
1290 UART_PUT_CHAR(uart, ch);
1291 }
1292
1293 static __init void early_serial_write(struct console *con, const char *s,
1294 unsigned int n)
1295 {
1296 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1297 unsigned int i;
1298
1299 for (i = 0; i < n; i++, s++) {
1300 if (*s == '\n')
1301 early_serial_putc(&uart->port, '\r');
1302 early_serial_putc(&uart->port, *s);
1303 }
1304 }
1305
1306 /*
1307 * This should have a .setup or .early_setup in it, but then things get called
1308 * without the command line options, and the baud rate gets messed up - so
1309 * don't let the common infrastructure play with things. (see calls to setup
1310 * & earlysetup in ./kernel/printk.c:register_console()
1311 */
1312 static struct __initdata console bfin_early_serial_console = {
1313 .name = "early_BFuart",
1314 .write = early_serial_write,
1315 .device = uart_console_device,
1316 .flags = CON_PRINTBUFFER,
1317 .index = -1,
1318 .data = &bfin_serial_reg,
1319 };
1320
1321 struct console __init *bfin_earlyserial_init(unsigned int port,
1322 unsigned int cflag)
1323 {
1324 struct bfin_serial_port *uart;
1325 struct ktermios t;
1326
1327 if (port == -1 || port >= nr_active_ports)
1328 port = 0;
1329 bfin_serial_init_ports();
1330 bfin_early_serial_console.index = port;
1331 uart = &bfin_serial_ports[port];
1332 t.c_cflag = cflag;
1333 t.c_iflag = 0;
1334 t.c_oflag = 0;
1335 t.c_lflag = ICANON;
1336 t.c_line = port;
1337 bfin_serial_set_termios(&uart->port, &t, &t);
1338 return &bfin_early_serial_console;
1339 }
1340
1341 #endif /* CONFIG_EARLY_PRINTK */
1342
1343 static struct uart_driver bfin_serial_reg = {
1344 .owner = THIS_MODULE,
1345 .driver_name = "bfin-uart",
1346 .dev_name = BFIN_SERIAL_NAME,
1347 .major = BFIN_SERIAL_MAJOR,
1348 .minor = BFIN_SERIAL_MINOR,
1349 .nr = BFIN_UART_NR_PORTS,
1350 .cons = BFIN_SERIAL_CONSOLE,
1351 };
1352
1353 static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1354 {
1355 int i;
1356
1357 for (i = 0; i < nr_active_ports; i++) {
1358 if (bfin_serial_ports[i].port.dev != &dev->dev)
1359 continue;
1360 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1361 }
1362
1363 return 0;
1364 }
1365
1366 static int bfin_serial_resume(struct platform_device *dev)
1367 {
1368 int i;
1369
1370 for (i = 0; i < nr_active_ports; i++) {
1371 if (bfin_serial_ports[i].port.dev != &dev->dev)
1372 continue;
1373 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1374 }
1375
1376 return 0;
1377 }
1378
1379 static int bfin_serial_probe(struct platform_device *dev)
1380 {
1381 struct resource *res = dev->resource;
1382 int i;
1383
1384 for (i = 0; i < dev->num_resources; i++, res++)
1385 if (res->flags & IORESOURCE_MEM)
1386 break;
1387
1388 if (i < dev->num_resources) {
1389 for (i = 0; i < nr_active_ports; i++, res++) {
1390 if (bfin_serial_ports[i].port.mapbase != res->start)
1391 continue;
1392 bfin_serial_ports[i].port.dev = &dev->dev;
1393 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1394 }
1395 }
1396
1397 return 0;
1398 }
1399
1400 static int bfin_serial_remove(struct platform_device *dev)
1401 {
1402 int i;
1403
1404 for (i = 0; i < nr_active_ports; i++) {
1405 if (bfin_serial_ports[i].port.dev != &dev->dev)
1406 continue;
1407 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1408 bfin_serial_ports[i].port.dev = NULL;
1409 #if defined(CONFIG_SERIAL_BFIN_CTSRTS)
1410 gpio_free(bfin_serial_ports[i].cts_pin);
1411 gpio_free(bfin_serial_ports[i].rts_pin);
1412 #endif
1413 }
1414
1415 return 0;
1416 }
1417
1418 static struct platform_driver bfin_serial_driver = {
1419 .probe = bfin_serial_probe,
1420 .remove = bfin_serial_remove,
1421 .suspend = bfin_serial_suspend,
1422 .resume = bfin_serial_resume,
1423 .driver = {
1424 .name = "bfin-uart",
1425 .owner = THIS_MODULE,
1426 },
1427 };
1428
1429 static int __init bfin_serial_init(void)
1430 {
1431 int ret;
1432
1433 pr_info("Serial: Blackfin serial driver\n");
1434
1435 bfin_serial_init_ports();
1436
1437 ret = uart_register_driver(&bfin_serial_reg);
1438 if (ret == 0) {
1439 ret = platform_driver_register(&bfin_serial_driver);
1440 if (ret) {
1441 pr_debug("uart register failed\n");
1442 uart_unregister_driver(&bfin_serial_reg);
1443 }
1444 }
1445 return ret;
1446 }
1447
1448 static void __exit bfin_serial_exit(void)
1449 {
1450 platform_driver_unregister(&bfin_serial_driver);
1451 uart_unregister_driver(&bfin_serial_reg);
1452 }
1453
1454
1455 module_init(bfin_serial_init);
1456 module_exit(bfin_serial_exit);
1457
1458 MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1459 MODULE_DESCRIPTION("Blackfin generic serial port driver");
1460 MODULE_LICENSE("GPL");
1461 MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
1462 MODULE_ALIAS("platform:bfin-uart");
Linux with added FPC-III support