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USB: add PID for FTDI based OpenDCC hardware
[linux/fpc-iii.git] / drivers / serial / bfin_sport_uart.c
blob5318dd3774ae156dc17f482a73e80f8c8a3ec77b
1 /*
2 * Blackfin On-Chip Sport Emulated UART Driver
3 *
4 * Copyright 2006-2009 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 /*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
16 * Transmit Frame Sync is not used by this driver to transfer data out.
17 */
18
19 /* #define DEBUG */
20
21 #define DRV_NAME "bfin-sport-uart"
22 #define DEVICE_NAME "ttySS"
23 #define pr_fmt(fmt) DRV_NAME ": " fmt
24
25 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/io.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/slab.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_core.h>
36
37 #include <asm/bfin_sport.h>
38 #include <asm/delay.h>
39 #include <asm/portmux.h>
40
41 #include "bfin_sport_uart.h"
42
43 struct sport_uart_port {
44 struct uart_port port;
45 int err_irq;
46 unsigned short csize;
47 unsigned short rxmask;
48 unsigned short txmask1;
49 unsigned short txmask2;
50 unsigned char stopb;
51 /* unsigned char parib; */
52 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
53 int cts_pin;
54 int rts_pin;
55 #endif
56 };
57
58 static int sport_uart_tx_chars(struct sport_uart_port *up);
59 static void sport_stop_tx(struct uart_port *port);
60
61 static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
62 {
63 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
64 up->txmask1, up->txmask2);
65
66 /* Place Start and Stop bits */
67 __asm__ __volatile__ (
68 "%[val] <<= 1;"
69 "%[val] = %[val] & %[mask1];"
70 "%[val] = %[val] | %[mask2];"
71 : [val]"+d"(value)
72 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
73 : "ASTAT"
74 );
75 pr_debug("%s value:%x\n", __func__, value);
76
77 SPORT_PUT_TX(up, value);
78 }
79
80 static inline unsigned char rx_one_byte(struct sport_uart_port *up)
81 {
82 unsigned int value;
83 unsigned char extract;
84 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
85
86 if ((up->csize + up->stopb) > 7)
87 value = SPORT_GET_RX32(up);
88 else
89 value = SPORT_GET_RX(up);
90
91 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
92 up->csize, up->rxmask);
93
94 /* Extract data */
95 __asm__ __volatile__ (
96 "%[extr] = 0;"
97 "%[mask1] = %[rxmask];"
98 "%[mask2] = 0x0200(Z);"
99 "%[shift] = 0;"
100 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
101 ".Lloop_s:"
102 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
103 "%[tmp] <<= %[shift];"
104 "%[extr] = %[extr] | %[tmp];"
105 "%[mask1] = %[mask1] - %[mask2];"
106 ".Lloop_e:"
107 "%[shift] += 1;"
108 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
109 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
110 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
111 : "ASTAT", "LB0", "LC0", "LT0"
112 );
113
114 pr_debug(" extract:%x\n", extract);
115 return extract;
116 }
117
118 static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
119 {
120 int tclkdiv, rclkdiv;
121 unsigned int sclk = get_sclk();
122
123 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
124 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
125 SPORT_PUT_TCR2(up, size + 1);
126 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
127
128 /* Set RCR1 and RCR2 */
129 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
130 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
131 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
132
133 tclkdiv = sclk / (2 * baud_rate) - 1;
134 rclkdiv = sclk / (2 * baud_rate * 2) - 1;
135 SPORT_PUT_TCLKDIV(up, tclkdiv);
136 SPORT_PUT_RCLKDIV(up, rclkdiv);
137 SSYNC();
138 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
139 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
140
141 return 0;
142 }
143
144 static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
145 {
146 struct sport_uart_port *up = dev_id;
147 struct tty_struct *tty = up->port.state->port.tty;
148 unsigned int ch;
149
150 spin_lock(&up->port.lock);
151
152 while (SPORT_GET_STAT(up) & RXNE) {
153 ch = rx_one_byte(up);
154 up->port.icount.rx++;
155
156 if (!uart_handle_sysrq_char(&up->port, ch))
157 tty_insert_flip_char(tty, ch, TTY_NORMAL);
158 }
159 tty_flip_buffer_push(tty);
160
161 spin_unlock(&up->port.lock);
162
163 return IRQ_HANDLED;
164 }
165
166 static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
167 {
168 struct sport_uart_port *up = dev_id;
169
170 spin_lock(&up->port.lock);
171 sport_uart_tx_chars(up);
172 spin_unlock(&up->port.lock);
173
174 return IRQ_HANDLED;
175 }
176
177 static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
178 {
179 struct sport_uart_port *up = dev_id;
180 struct tty_struct *tty = up->port.state->port.tty;
181 unsigned int stat = SPORT_GET_STAT(up);
182
183 spin_lock(&up->port.lock);
184
185 /* Overflow in RX FIFO */
186 if (stat & ROVF) {
187 up->port.icount.overrun++;
188 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
189 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
190 }
191 /* These should not happen */
192 if (stat & (TOVF | TUVF | RUVF)) {
193 pr_err("SPORT Error:%s %s %s\n",
194 (stat & TOVF) ? "TX overflow" : "",
195 (stat & TUVF) ? "TX underflow" : "",
196 (stat & RUVF) ? "RX underflow" : "");
197 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
198 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
199 }
200 SSYNC();
201
202 spin_unlock(&up->port.lock);
203 return IRQ_HANDLED;
204 }
205
206 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
207 static unsigned int sport_get_mctrl(struct uart_port *port)
208 {
209 struct sport_uart_port *up = (struct sport_uart_port *)port;
210 if (up->cts_pin < 0)
211 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
212
213 /* CTS PIN is negative assertive. */
214 if (SPORT_UART_GET_CTS(up))
215 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
216 else
217 return TIOCM_DSR | TIOCM_CAR;
218 }
219
220 static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
221 {
222 struct sport_uart_port *up = (struct sport_uart_port *)port;
223 if (up->rts_pin < 0)
224 return;
225
226 /* RTS PIN is negative assertive. */
227 if (mctrl & TIOCM_RTS)
228 SPORT_UART_ENABLE_RTS(up);
229 else
230 SPORT_UART_DISABLE_RTS(up);
231 }
232
233 /*
234 * Handle any change of modem status signal.
235 */
236 static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
237 {
238 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
239 unsigned int status;
240
241 status = sport_get_mctrl(&up->port);
242 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
243
244 return IRQ_HANDLED;
245 }
246 #else
247 static unsigned int sport_get_mctrl(struct uart_port *port)
248 {
249 pr_debug("%s enter\n", __func__);
250 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
251 }
252
253 static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
254 {
255 pr_debug("%s enter\n", __func__);
256 }
257 #endif
258
259 /* Reqeust IRQ, Setup clock */
260 static int sport_startup(struct uart_port *port)
261 {
262 struct sport_uart_port *up = (struct sport_uart_port *)port;
263 int ret;
264
265 pr_debug("%s enter\n", __func__);
266 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
267 "SPORT_UART_RX", up);
268 if (ret) {
269 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
270 return ret;
271 }
272
273 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
274 "SPORT_UART_TX", up);
275 if (ret) {
276 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
277 goto fail1;
278 }
279
280 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
281 "SPORT_UART_STATUS", up);
282 if (ret) {
283 dev_err(port->dev, "unable to request SPORT status interrupt\n");
284 goto fail2;
285 }
286
287 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
288 if (up->cts_pin >= 0) {
289 if (request_irq(gpio_to_irq(up->cts_pin),
290 sport_mctrl_cts_int,
291 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
292 IRQF_DISABLED, "BFIN_SPORT_UART_CTS", up)) {
293 up->cts_pin = -1;
294 dev_info(port->dev, "Unable to attach BlackFin UART \
295 over SPORT CTS interrupt. So, disable it.\n");
296 }
297 }
298 if (up->rts_pin >= 0)
299 gpio_direction_output(up->rts_pin, 0);
300 #endif
301
302 return 0;
303 fail2:
304 free_irq(up->port.irq+1, up);
305 fail1:
306 free_irq(up->port.irq, up);
307
308 return ret;
309 }
310
311 /*
312 * sport_uart_tx_chars
313 *
314 * ret 1 means need to enable sport.
315 * ret 0 means do nothing.
316 */
317 static int sport_uart_tx_chars(struct sport_uart_port *up)
318 {
319 struct circ_buf *xmit = &up->port.state->xmit;
320
321 if (SPORT_GET_STAT(up) & TXF)
322 return 0;
323
324 if (up->port.x_char) {
325 tx_one_byte(up, up->port.x_char);
326 up->port.icount.tx++;
327 up->port.x_char = 0;
328 return 1;
329 }
330
331 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
332 /* The waiting loop to stop SPORT TX from TX interrupt is
333 * too long. This may block SPORT RX interrupts and cause
334 * RX FIFO overflow. So, do stop sport TX only after the last
335 * char in TX FIFO is moved into the shift register.
336 */
337 if (SPORT_GET_STAT(up) & TXHRE)
338 sport_stop_tx(&up->port);
339 return 0;
340 }
341
342 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
343 tx_one_byte(up, xmit->buf[xmit->tail]);
344 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
345 up->port.icount.tx++;
346 }
347
348 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
349 uart_write_wakeup(&up->port);
350
351 return 1;
352 }
353
354 static unsigned int sport_tx_empty(struct uart_port *port)
355 {
356 struct sport_uart_port *up = (struct sport_uart_port *)port;
357 unsigned int stat;
358
359 stat = SPORT_GET_STAT(up);
360 pr_debug("%s stat:%04x\n", __func__, stat);
361 if (stat & TXHRE) {
362 return TIOCSER_TEMT;
363 } else
364 return 0;
365 }
366
367 static void sport_stop_tx(struct uart_port *port)
368 {
369 struct sport_uart_port *up = (struct sport_uart_port *)port;
370
371 pr_debug("%s enter\n", __func__);
372
373 if (!(SPORT_GET_TCR1(up) & TSPEN))
374 return;
375
376 /* Although the hold register is empty, last byte is still in shift
377 * register and not sent out yet. So, put a dummy data into TX FIFO.
378 * Then, sport tx stops when last byte is shift out and the dummy
379 * data is moved into the shift register.
380 */
381 SPORT_PUT_TX(up, 0xffff);
382 while (!(SPORT_GET_STAT(up) & TXHRE))
383 cpu_relax();
384
385 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
386 SSYNC();
387
388 return;
389 }
390
391 static void sport_start_tx(struct uart_port *port)
392 {
393 struct sport_uart_port *up = (struct sport_uart_port *)port;
394
395 pr_debug("%s enter\n", __func__);
396
397 /* Write data into SPORT FIFO before enable SPROT to transmit */
398 if (sport_uart_tx_chars(up)) {
399 /* Enable transmit, then an interrupt will generated */
400 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
401 SSYNC();
402 }
403
404 pr_debug("%s exit\n", __func__);
405 }
406
407 static void sport_stop_rx(struct uart_port *port)
408 {
409 struct sport_uart_port *up = (struct sport_uart_port *)port;
410
411 pr_debug("%s enter\n", __func__);
412 /* Disable sport to stop rx */
413 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
414 SSYNC();
415 }
416
417 static void sport_enable_ms(struct uart_port *port)
418 {
419 pr_debug("%s enter\n", __func__);
420 }
421
422 static void sport_break_ctl(struct uart_port *port, int break_state)
423 {
424 pr_debug("%s enter\n", __func__);
425 }
426
427 static void sport_shutdown(struct uart_port *port)
428 {
429 struct sport_uart_port *up = (struct sport_uart_port *)port;
430
431 dev_dbg(port->dev, "%s enter\n", __func__);
432
433 /* Disable sport */
434 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
435 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
436 SSYNC();
437
438 free_irq(up->port.irq, up);
439 free_irq(up->port.irq+1, up);
440 free_irq(up->err_irq, up);
441 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
442 if (up->cts_pin >= 0)
443 free_irq(gpio_to_irq(up->cts_pin), up);
444 #endif
445 }
446
447 static const char *sport_type(struct uart_port *port)
448 {
449 struct sport_uart_port *up = (struct sport_uart_port *)port;
450
451 pr_debug("%s enter\n", __func__);
452 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
453 }
454
455 static void sport_release_port(struct uart_port *port)
456 {
457 pr_debug("%s enter\n", __func__);
458 }
459
460 static int sport_request_port(struct uart_port *port)
461 {
462 pr_debug("%s enter\n", __func__);
463 return 0;
464 }
465
466 static void sport_config_port(struct uart_port *port, int flags)
467 {
468 struct sport_uart_port *up = (struct sport_uart_port *)port;
469
470 pr_debug("%s enter\n", __func__);
471 up->port.type = PORT_BFIN_SPORT;
472 }
473
474 static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
475 {
476 pr_debug("%s enter\n", __func__);
477 return 0;
478 }
479
480 static void sport_set_termios(struct uart_port *port,
481 struct ktermios *termios, struct ktermios *old)
482 {
483 struct sport_uart_port *up = (struct sport_uart_port *)port;
484 unsigned long flags;
485 int i;
486
487 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
488
489 switch (termios->c_cflag & CSIZE) {
490 case CS8:
491 up->csize = 8;
492 break;
493 case CS7:
494 up->csize = 7;
495 break;
496 case CS6:
497 up->csize = 6;
498 break;
499 case CS5:
500 up->csize = 5;
501 break;
502 default:
503 pr_warning("requested word length not supported\n");
504 }
505
506 if (termios->c_cflag & CSTOPB) {
507 up->stopb = 1;
508 }
509 if (termios->c_cflag & PARENB) {
510 pr_warning("PAREN bits is not supported yet\n");
511 /* up->parib = 1; */
512 }
513
514 spin_lock_irqsave(&up->port.lock, flags);
515
516 port->read_status_mask = 0;
517
518 /*
519 * Characters to ignore
520 */
521 port->ignore_status_mask = 0;
522
523 /* RX extract mask */
524 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
525 /* TX masks, 8 bit data and 1 bit stop for example:
526 * mask1 = b#0111111110
527 * mask2 = b#1000000000
528 */
529 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
530 up->txmask1 |= (1<<i);
531 up->txmask2 = (1<<i);
532 if (up->stopb) {
533 ++i;
534 up->txmask2 |= (1<<i);
535 }
536 up->txmask1 <<= 1;
537 up->txmask2 <<= 1;
538 /* uart baud rate */
539 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
540
541 /* Disable UART */
542 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
543 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
544
545 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
546
547 /* driver TX line high after config, one dummy data is
548 * necessary to stop sport after shift one byte
549 */
550 SPORT_PUT_TX(up, 0xffff);
551 SPORT_PUT_TX(up, 0xffff);
552 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
553 SSYNC();
554 while (!(SPORT_GET_STAT(up) & TXHRE))
555 cpu_relax();
556 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
557 SSYNC();
558
559 /* Port speed changed, update the per-port timeout. */
560 uart_update_timeout(port, termios->c_cflag, port->uartclk);
561
562 /* Enable sport rx */
563 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
564 SSYNC();
565
566 spin_unlock_irqrestore(&up->port.lock, flags);
567 }
568
569 struct uart_ops sport_uart_ops = {
570 .tx_empty = sport_tx_empty,
571 .set_mctrl = sport_set_mctrl,
572 .get_mctrl = sport_get_mctrl,
573 .stop_tx = sport_stop_tx,
574 .start_tx = sport_start_tx,
575 .stop_rx = sport_stop_rx,
576 .enable_ms = sport_enable_ms,
577 .break_ctl = sport_break_ctl,
578 .startup = sport_startup,
579 .shutdown = sport_shutdown,
580 .set_termios = sport_set_termios,
581 .type = sport_type,
582 .release_port = sport_release_port,
583 .request_port = sport_request_port,
584 .config_port = sport_config_port,
585 .verify_port = sport_verify_port,
586 };
587
588 #define BFIN_SPORT_UART_MAX_PORTS 4
589
590 static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
591
592 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
593 #define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
594
595 static int __init
596 sport_uart_console_setup(struct console *co, char *options)
597 {
598 struct sport_uart_port *up;
599 int baud = 57600;
600 int bits = 8;
601 int parity = 'n';
602 # ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
603 int flow = 'r';
604 # else
605 int flow = 'n';
606 # endif
607
608 /* Check whether an invalid uart number has been specified */
609 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
610 return -ENODEV;
611
612 up = bfin_sport_uart_ports[co->index];
613 if (!up)
614 return -ENODEV;
615
616 if (options)
617 uart_parse_options(options, &baud, &parity, &bits, &flow);
618
619 return uart_set_options(&up->port, co, baud, parity, bits, flow);
620 }
621
622 static void sport_uart_console_putchar(struct uart_port *port, int ch)
623 {
624 struct sport_uart_port *up = (struct sport_uart_port *)port;
625
626 while (SPORT_GET_STAT(up) & TXF)
627 barrier();
628
629 tx_one_byte(up, ch);
630 }
631
632 /*
633 * Interrupts are disabled on entering
634 */
635 static void
636 sport_uart_console_write(struct console *co, const char *s, unsigned int count)
637 {
638 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
639 unsigned long flags;
640
641 spin_lock_irqsave(&up->port.lock, flags);
642
643 if (SPORT_GET_TCR1(up) & TSPEN)
644 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
645 else {
646 /* dummy data to start sport */
647 while (SPORT_GET_STAT(up) & TXF)
648 barrier();
649 SPORT_PUT_TX(up, 0xffff);
650 /* Enable transmit, then an interrupt will generated */
651 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
652 SSYNC();
653
654 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
655
656 /* Although the hold register is empty, last byte is still in shift
657 * register and not sent out yet. So, put a dummy data into TX FIFO.
658 * Then, sport tx stops when last byte is shift out and the dummy
659 * data is moved into the shift register.
660 */
661 while (SPORT_GET_STAT(up) & TXF)
662 barrier();
663 SPORT_PUT_TX(up, 0xffff);
664 while (!(SPORT_GET_STAT(up) & TXHRE))
665 barrier();
666
667 /* Stop sport tx transfer */
668 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
669 SSYNC();
670 }
671
672 spin_unlock_irqrestore(&up->port.lock, flags);
673 }
674
675 static struct uart_driver sport_uart_reg;
676
677 static struct console sport_uart_console = {
678 .name = DEVICE_NAME,
679 .write = sport_uart_console_write,
680 .device = uart_console_device,
681 .setup = sport_uart_console_setup,
682 .flags = CON_PRINTBUFFER,
683 .index = -1,
684 .data = &sport_uart_reg,
685 };
686
687 #define SPORT_UART_CONSOLE (&sport_uart_console)
688 #else
689 #define SPORT_UART_CONSOLE NULL
690 #endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
691
692
693 static struct uart_driver sport_uart_reg = {
694 .owner = THIS_MODULE,
695 .driver_name = DRV_NAME,
696 .dev_name = DEVICE_NAME,
697 .major = 204,
698 .minor = 84,
699 .nr = BFIN_SPORT_UART_MAX_PORTS,
700 .cons = SPORT_UART_CONSOLE,
701 };
702
703 #ifdef CONFIG_PM
704 static int sport_uart_suspend(struct device *dev)
705 {
706 struct sport_uart_port *sport = dev_get_drvdata(dev);
707
708 dev_dbg(dev, "%s enter\n", __func__);
709 if (sport)
710 uart_suspend_port(&sport_uart_reg, &sport->port);
711
712 return 0;
713 }
714
715 static int sport_uart_resume(struct device *dev)
716 {
717 struct sport_uart_port *sport = dev_get_drvdata(dev);
718
719 dev_dbg(dev, "%s enter\n", __func__);
720 if (sport)
721 uart_resume_port(&sport_uart_reg, &sport->port);
722
723 return 0;
724 }
725
726 static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
727 .suspend = sport_uart_suspend,
728 .resume = sport_uart_resume,
729 };
730 #endif
731
732 static int __devinit sport_uart_probe(struct platform_device *pdev)
733 {
734 struct resource *res;
735 struct sport_uart_port *sport;
736 int ret = 0;
737
738 dev_dbg(&pdev->dev, "%s enter\n", __func__);
739
740 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
741 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
742 return -ENOENT;
743 }
744
745 if (bfin_sport_uart_ports[pdev->id] == NULL) {
746 bfin_sport_uart_ports[pdev->id] =
747 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
748 sport = bfin_sport_uart_ports[pdev->id];
749 if (!sport) {
750 dev_err(&pdev->dev,
751 "Fail to malloc sport_uart_port\n");
752 return -ENOMEM;
753 }
754
755 ret = peripheral_request_list(
756 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
757 if (ret) {
758 dev_err(&pdev->dev,
759 "Fail to request SPORT peripherals\n");
760 goto out_error_free_mem;
761 }
762
763 spin_lock_init(&sport->port.lock);
764 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
765 sport->port.ops = &sport_uart_ops;
766 sport->port.line = pdev->id;
767 sport->port.iotype = UPIO_MEM;
768 sport->port.flags = UPF_BOOT_AUTOCONF;
769
770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
771 if (res == NULL) {
772 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
773 ret = -ENOENT;
774 goto out_error_free_peripherals;
775 }
776
777 sport->port.membase = ioremap(res->start, resource_size(res));
778 if (!sport->port.membase) {
779 dev_err(&pdev->dev, "Cannot map sport IO\n");
780 ret = -ENXIO;
781 goto out_error_free_peripherals;
782 }
783 sport->port.mapbase = res->start;
784
785 sport->port.irq = platform_get_irq(pdev, 0);
786 if (sport->port.irq < 0) {
787 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
788 ret = -ENOENT;
789 goto out_error_unmap;
790 }
791
792 sport->err_irq = platform_get_irq(pdev, 1);
793 if (sport->err_irq < 0) {
794 dev_err(&pdev->dev, "No sport status IRQ specified\n");
795 ret = -ENOENT;
796 goto out_error_unmap;
797 }
798 #ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
799 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
800 if (res == NULL)
801 sport->cts_pin = -1;
802 else
803 sport->cts_pin = res->start;
804
805 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
806 if (res == NULL)
807 sport->rts_pin = -1;
808 else
809 sport->rts_pin = res->start;
810
811 if (sport->rts_pin >= 0)
812 gpio_request(sport->rts_pin, DRV_NAME);
813 #endif
814 }
815
816 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
817 if (!is_early_platform_device(pdev)) {
818 #endif
819 sport = bfin_sport_uart_ports[pdev->id];
820 sport->port.dev = &pdev->dev;
821 dev_set_drvdata(&pdev->dev, sport);
822 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
823 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
824 }
825 #endif
826 if (!ret)
827 return 0;
828
829 if (sport) {
830 out_error_unmap:
831 iounmap(sport->port.membase);
832 out_error_free_peripherals:
833 peripheral_free_list(
834 (unsigned short *)pdev->dev.platform_data);
835 out_error_free_mem:
836 kfree(sport);
837 bfin_sport_uart_ports[pdev->id] = NULL;
838 }
839
840 return ret;
841 }
842
843 static int __devexit sport_uart_remove(struct platform_device *pdev)
844 {
845 struct sport_uart_port *sport = platform_get_drvdata(pdev);
846
847 dev_dbg(&pdev->dev, "%s enter\n", __func__);
848 dev_set_drvdata(&pdev->dev, NULL);
849
850 if (sport) {
851 uart_remove_one_port(&sport_uart_reg, &sport->port);
852 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
853 if (sport->rts_pin >= 0)
854 gpio_free(sport->rts_pin);
855 #endif
856 iounmap(sport->port.membase);
857 peripheral_free_list(
858 (unsigned short *)pdev->dev.platform_data);
859 kfree(sport);
860 bfin_sport_uart_ports[pdev->id] = NULL;
861 }
862
863 return 0;
864 }
865
866 static struct platform_driver sport_uart_driver = {
867 .probe = sport_uart_probe,
868 .remove = __devexit_p(sport_uart_remove),
869 .driver = {
870 .name = DRV_NAME,
871 #ifdef CONFIG_PM
872 .pm = &bfin_sport_uart_dev_pm_ops,
873 #endif
874 },
875 };
876
877 #ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
878 static __initdata struct early_platform_driver early_sport_uart_driver = {
879 .class_str = CLASS_BFIN_SPORT_CONSOLE,
880 .pdrv = &sport_uart_driver,
881 .requested_id = EARLY_PLATFORM_ID_UNSET,
882 };
883
884 static int __init sport_uart_rs_console_init(void)
885 {
886 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
887
888 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
889 BFIN_SPORT_UART_MAX_PORTS, 0);
890
891 register_console(&sport_uart_console);
892
893 return 0;
894 }
895 console_initcall(sport_uart_rs_console_init);
896 #endif
897
898 static int __init sport_uart_init(void)
899 {
900 int ret;
901
902 pr_info("Blackfin uart over sport driver\n");
903
904 ret = uart_register_driver(&sport_uart_reg);
905 if (ret) {
906 pr_err("failed to register %s:%d\n",
907 sport_uart_reg.driver_name, ret);
908 return ret;
909 }
910
911 ret = platform_driver_register(&sport_uart_driver);
912 if (ret) {
913 pr_err("failed to register sport uart driver:%d\n", ret);
914 uart_unregister_driver(&sport_uart_reg);
915 }
916
917 return ret;
918 }
919 module_init(sport_uart_init);
920
921 static void __exit sport_uart_exit(void)
922 {
923 platform_driver_unregister(&sport_uart_driver);
924 uart_unregister_driver(&sport_uart_reg);
925 }
926 module_exit(sport_uart_exit);
927
928 MODULE_AUTHOR("Sonic Zhang, Roy Huang");
929 MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
930 MODULE_LICENSE("GPL");
Linux with added FPC-III support