include/asm-arm/arch-iop13xx/iop13xx.h

   1 #ifndef _IOP13XX_HW_H_
   2 #define _IOP13XX_HW_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /* The ATU offsets can change based on the strapping */
   6 extern u32 iop13xx_atux_pmmr_offset;
   7 extern u32 iop13xx_atue_pmmr_offset;
   8 void iop13xx_init_irq(void);
   9 void iop13xx_map_io(void);
  10 void iop13xx_platform_init(void);
  11 void iop13xx_init_irq(void);
  12 void iop13xx_init_time(unsigned long tickrate);
  13 unsigned long iop13xx_gettimeoffset(void);
  14
  15 /* handle cp6 access
  16  * to do: handle access in entry-armv5.S and unify with
  17  * the iop3xx implementation
  18  * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
  19  * when interrupts are enabled
  20  */
  21 static inline unsigned long iop13xx_cp6_save(void)
  22 {
  23         u32 temp, cp_flags;
  24
  25         asm volatile (
  26                 "mrc    p15, 0, %1, c15, c1, 0\n\t"
  27                 "orr    %0, %1, #(1 << 6)\n\t"
  28                 "mcr    p15, 0, %0, c15, c1, 0\n\t"
  29                 : "=r" (temp), "=r"(cp_flags));
  30
  31         return cp_flags;
  32 }
  33
  34 static inline void iop13xx_cp6_restore(unsigned long cp_flags)
  35 {
  36         asm volatile (
  37                 "mcr    p15, 0, %0, c15, c1, 0\n\t"
  38                 : : "r" (cp_flags) );
  39 }
  40
  41 /* CPUID CP6 R0 Page 0 */
  42 static inline int iop13xx_cpu_id(void)
  43 {
  44         int id;
  45         asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
  46         return id;
  47 }
  48
  49 #endif
  50
  51 /*
  52  * IOP13XX I/O and Mem space regions for PCI autoconfiguration
  53  */
  54 #define IOP13XX_MAX_RAM_SIZE    0x80000000UL  /* 2GB */
  55 #define IOP13XX_PCI_OFFSET       IOP13XX_MAX_RAM_SIZE
  56
  57 /* PCI MAP
  58  * 0x0000.0000 - 0x8000.0000           1:1 mapping with Physical RAM
  59  * 0x8000.0000 - 0x8800.0000           PCIX/PCIE memory window (128MB)
  60 */
  61 #define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
  62 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
  63 #define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
  64 #define IOP13XX_PCIX_LOWER_IO_BA      0x0fff0000UL
  65 #define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
  66                                        IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
  67 #define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
  68                                        IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
  69 #define IOP13XX_PCIX_IO_OFFSET        (IOP13XX_PCIX_LOWER_IO_VA -\
  70                                        IOP13XX_PCIX_LOWER_IO_BA)
  71 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
  72                                            (IOP13XX_PCIX_LOWER_IO_PA\
  73                                            - IOP13XX_PCIX_LOWER_IO_VA))
  74
  75 #define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
  76 #define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
  77 #define IOP13XX_PCIX_LOWER_MEM_BA     (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
  78 #define IOP13XX_PCIX_LOWER_MEM_PA     (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
  79                                        IOP13XX_PCIX_LOWER_MEM_BA)
  80 #define IOP13XX_PCIX_UPPER_MEM_PA     (IOP13XX_PCIX_LOWER_MEM_PA +\
  81                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  82 #define IOP13XX_PCIX_UPPER_MEM_BA     (IOP13XX_PCIX_LOWER_MEM_BA +\
  83                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  84
  85 #define IOP13XX_PCIX_MEM_COOKIE        0x80000000UL
  86 #define IOP13XX_PCIX_LOWER_MEM_RA      IOP13XX_PCIX_MEM_COOKIE
  87 #define IOP13XX_PCIX_UPPER_MEM_RA      (IOP13XX_PCIX_LOWER_MEM_RA +\
  88                                         IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  89 #define IOP13XX_PCIX_MEM_OFFSET        (IOP13XX_PCIX_MEM_COOKIE -\
  90                                         IOP13XX_PCIX_LOWER_MEM_BA)
  91
  92 /* PCI-E ranges */
  93 #define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
  94 #define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
  95 #define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
  96 #define IOP13XX_PCIE_LOWER_IO_BA         0x0fff0000UL
  97 #define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
  98                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
  99 #define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
 100                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 101 #define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
 102                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 103 #define IOP13XX_PCIE_IO_OFFSET           (IOP13XX_PCIE_LOWER_IO_VA -\
 104                                          IOP13XX_PCIE_LOWER_IO_BA)
 105 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
 106                                            (IOP13XX_PCIE_LOWER_IO_PA\
 107                                            - IOP13XX_PCIE_LOWER_IO_VA))
 108
 109 #define IOP13XX_PCIE_MEM_PHYS_OFFSET     0x200000000ULL
 110 #define IOP13XX_PCIE_MEM_WINDOW_SIZE     0x3a000000UL
 111 #define IOP13XX_PCIE_LOWER_MEM_BA        (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
 112 #define IOP13XX_PCIE_LOWER_MEM_PA        (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
 113                                          IOP13XX_PCIE_LOWER_MEM_BA)
 114 #define IOP13XX_PCIE_UPPER_MEM_PA        (IOP13XX_PCIE_LOWER_MEM_PA +\
 115                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
 116 #define IOP13XX_PCIE_UPPER_MEM_BA        (IOP13XX_PCIE_LOWER_MEM_BA +\
 117                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
 118
 119 /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
 120 #define IOP13XX_PCIE_MEM_COOKIE          0xc0000000UL
 121 #define IOP13XX_PCIE_LOWER_MEM_RA        IOP13XX_PCIE_MEM_COOKIE
 122 #define IOP13XX_PCIE_UPPER_MEM_RA        (IOP13XX_PCIE_LOWER_MEM_RA +\
 123                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
 124 #define IOP13XX_PCIE_MEM_OFFSET          (IOP13XX_PCIE_MEM_COOKIE -\
 125                                          IOP13XX_PCIE_LOWER_MEM_BA)
 126
 127 /* PBI Ranges */
 128 #define IOP13XX_PBI_LOWER_MEM_PA          0xf0000000UL
 129 #define IOP13XX_PBI_MEM_WINDOW_SIZE       0x04000000UL
 130 #define IOP13XX_PBI_MEM_COOKIE            0xfa000000UL
 131 #define IOP13XX_PBI_LOWER_MEM_RA          IOP13XX_PBI_MEM_COOKIE
 132 #define IOP13XX_PBI_UPPER_MEM_RA          (IOP13XX_PBI_LOWER_MEM_RA +\
 133                                           IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
 134
 135 /*
 136  * IOP13XX chipset registers
 137  */
 138 #define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
 139 #define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
 140 #define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
 141 #define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
 142                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 143 #define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
 144                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 145 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
 146                                            (IOP13XX_PMMR_PHYS_MEM_BASE\
 147                                            - IOP13XX_PMMR_VIRT_MEM_BASE))
 148 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
 149                                            (IOP13XX_PMMR_PHYS_MEM_BASE\
 150                                            - IOP13XX_PMMR_VIRT_MEM_BASE))
 151 #define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 152 #define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 153 #define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 154 #define IOP13XX_REG_ADDR32_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 155 #define IOP13XX_REG_ADDR16_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 156 #define IOP13XX_REG_ADDR8_PHYS(reg)       (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 157 #define IOP13XX_PMMR_SIZE                  0x00080000
 158
 159 /*=================== Defines for Platform Devices =====================*/
 160 #define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
 161 #define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
 162 #define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
 163 #define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
 164
 165 #define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
 166 #define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
 167 #define IOP13XX_I2C2_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
 168 #define IOP13XX_I2C0_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
 169 #define IOP13XX_I2C1_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
 170 #define IOP13XX_I2C2_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
 171
 172 /* ATU selection flags */
 173 /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
 174 #define IOP13XX_INIT_ATU_DEFAULT     (0)
 175 #define IOP13XX_INIT_ATU_ATUX         (1 << 0)
 176 #define IOP13XX_INIT_ATU_ATUE         (1 << 1)
 177 #define IOP13XX_INIT_ATU_NONE         (1 << 2)
 178
 179 /* UART selection flags */
 180 /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
 181 #define IOP13XX_INIT_UART_DEFAULT    (0)
 182 #define IOP13XX_INIT_UART_0           (1 << 0)
 183 #define IOP13XX_INIT_UART_1           (1 << 1)
 184
 185 /* I2C selection flags */
 186 /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
 187 #define IOP13XX_INIT_I2C_DEFAULT     (0)
 188 #define IOP13XX_INIT_I2C_0            (1 << 0)
 189 #define IOP13XX_INIT_I2C_1            (1 << 1)
 190 #define IOP13XX_INIT_I2C_2            (1 << 2)
 191
 192 #define IQ81340_NUM_UART     2
 193 #define IQ81340_NUM_I2C      3
 194 #define IQ81340_NUM_PHYS_MAP_FLASH 1
 195 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
 196                                 IQ81340_NUM_I2C +\
 197                                 IQ81340_NUM_PHYS_MAP_FLASH)
 198
 199 /*========================== PMMR offsets for key registers ============*/
 200 #define IOP13XX_ATU0_PMMR_OFFSET        0x00048000
 201 #define IOP13XX_ATU1_PMMR_OFFSET        0x0004c000
 202 #define IOP13XX_ATU2_PMMR_OFFSET        0x0004d000
 203 #define IOP13XX_ADMA0_PMMR_OFFSET       0x00000000
 204 #define IOP13XX_ADMA1_PMMR_OFFSET       0x00000200
 205 #define IOP13XX_ADMA2_PMMR_OFFSET       0x00000400
 206 #define IOP13XX_PBI_PMMR_OFFSET         0x00001580
 207 #define IOP13XX_ESSR0_PMMR_OFFSET       0x00002188
 208 #define IOP13XX_ESSR0                   IOP13XX_REG_ADDR32(0x00002188)
 209
 210 #define IOP13XX_ESSR0_IFACE_MASK        0x00004000  /* Interface PCI-X / PCI-E */
 211 #define IOP13XX_CONTROLLER_ONLY         (1 << 14)
 212 #define IOP13XX_INTERFACE_SEL_PCIX      (1 << 15)
 213
 214 #define IOP13XX_PMON_PMMR_OFFSET        0x0001A000
 215 #define IOP13XX_PMON_BASE               (IOP13XX_PMMR_VIRT_MEM_BASE +\
 216                                         IOP13XX_PMON_PMMR_OFFSET)
 217 #define IOP13XX_PMON_PHYSBASE           (IOP13XX_PMMR_PHYS_MEM_BASE +\
 218                                         IOP13XX_PMON_PMMR_OFFSET)
 219
 220 #define IOP13XX_PMON_CMD0               (IOP13XX_PMON_BASE + 0x0)
 221 #define IOP13XX_PMON_EVR0               (IOP13XX_PMON_BASE + 0x4)
 222 #define IOP13XX_PMON_STS0               (IOP13XX_PMON_BASE + 0x8)
 223 #define IOP13XX_PMON_DATA0              (IOP13XX_PMON_BASE + 0xC)
 224
 225 #define IOP13XX_PMON_CMD3               (IOP13XX_PMON_BASE + 0x30)
 226 #define IOP13XX_PMON_EVR3               (IOP13XX_PMON_BASE + 0x34)
 227 #define IOP13XX_PMON_STS3               (IOP13XX_PMON_BASE + 0x38)
 228 #define IOP13XX_PMON_DATA3              (IOP13XX_PMON_BASE + 0x3C)
 229
 230 #define IOP13XX_PMON_CMD7               (IOP13XX_PMON_BASE + 0x70)
 231 #define IOP13XX_PMON_EVR7               (IOP13XX_PMON_BASE + 0x74)
 232 #define IOP13XX_PMON_STS7               (IOP13XX_PMON_BASE + 0x78)
 233 #define IOP13XX_PMON_DATA7              (IOP13XX_PMON_BASE + 0x7C)
 234
 235 #define IOP13XX_PMONEN                  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
 236 #define IOP13XX_PMONSTAT                (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
 237
 238 /*================================ATU===================================*/
 239 #define IOP13XX_ATUX_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
 240                                         iop13xx_atux_pmmr_offset + (ofs))
 241
 242 #define IOP13XX_ATUX_DID                IOP13XX_REG_ADDR16(\
 243                                         iop13xx_atux_pmmr_offset + 0x2)
 244
 245 #define IOP13XX_ATUX_ATUCMD             IOP13XX_REG_ADDR16(\
 246                                         iop13xx_atux_pmmr_offset + 0x4)
 247 #define IOP13XX_ATUX_ATUSR              IOP13XX_REG_ADDR16(\
 248                                         iop13xx_atux_pmmr_offset + 0x6)
 249
 250 #define IOP13XX_ATUX_IABAR0             IOP13XX_ATUX_OFFSET(0x10)
 251 #define IOP13XX_ATUX_IAUBAR0            IOP13XX_ATUX_OFFSET(0x14)
 252 #define IOP13XX_ATUX_IABAR1             IOP13XX_ATUX_OFFSET(0x18)
 253 #define IOP13XX_ATUX_IAUBAR1            IOP13XX_ATUX_OFFSET(0x1c)
 254 #define IOP13XX_ATUX_IABAR2             IOP13XX_ATUX_OFFSET(0x20)
 255 #define IOP13XX_ATUX_IAUBAR2            IOP13XX_ATUX_OFFSET(0x24)
 256 #define IOP13XX_ATUX_IALR0              IOP13XX_ATUX_OFFSET(0x40)
 257 #define IOP13XX_ATUX_IATVR0             IOP13XX_ATUX_OFFSET(0x44)
 258 #define IOP13XX_ATUX_IAUTVR0            IOP13XX_ATUX_OFFSET(0x48)
 259 #define IOP13XX_ATUX_IALR1              IOP13XX_ATUX_OFFSET(0x4c)
 260 #define IOP13XX_ATUX_IATVR1             IOP13XX_ATUX_OFFSET(0x50)
 261 #define IOP13XX_ATUX_IAUTVR1            IOP13XX_ATUX_OFFSET(0x54)
 262 #define IOP13XX_ATUX_IALR2              IOP13XX_ATUX_OFFSET(0x58)
 263 #define IOP13XX_ATUX_IATVR2             IOP13XX_ATUX_OFFSET(0x5c)
 264 #define IOP13XX_ATUX_IAUTVR2            IOP13XX_ATUX_OFFSET(0x60)
 265 #define IOP13XX_ATUX_ATUCR              IOP13XX_ATUX_OFFSET(0x70)
 266 #define IOP13XX_ATUX_PCSR               IOP13XX_ATUX_OFFSET(0x74)
 267 #define IOP13XX_ATUX_ATUISR             IOP13XX_ATUX_OFFSET(0x78)
 268 #define IOP13XX_ATUX_PCIXSR             IOP13XX_ATUX_OFFSET(0xD4)
 269 #define IOP13XX_ATUX_IABAR3             IOP13XX_ATUX_OFFSET(0x200)
 270 #define IOP13XX_ATUX_IAUBAR3            IOP13XX_ATUX_OFFSET(0x204)
 271 #define IOP13XX_ATUX_IALR3              IOP13XX_ATUX_OFFSET(0x208)
 272 #define IOP13XX_ATUX_IATVR3             IOP13XX_ATUX_OFFSET(0x20c)
 273 #define IOP13XX_ATUX_IAUTVR3            IOP13XX_ATUX_OFFSET(0x210)
 274
 275 #define IOP13XX_ATUX_OIOBAR             IOP13XX_ATUX_OFFSET(0x300)
 276 #define IOP13XX_ATUX_OIOWTVR            IOP13XX_ATUX_OFFSET(0x304)
 277 #define IOP13XX_ATUX_OUMBAR0            IOP13XX_ATUX_OFFSET(0x308)
 278 #define IOP13XX_ATUX_OUMWTVR0           IOP13XX_ATUX_OFFSET(0x30c)
 279 #define IOP13XX_ATUX_OUMBAR1            IOP13XX_ATUX_OFFSET(0x310)
 280 #define IOP13XX_ATUX_OUMWTVR1           IOP13XX_ATUX_OFFSET(0x314)
 281 #define IOP13XX_ATUX_OUMBAR2            IOP13XX_ATUX_OFFSET(0x318)
 282 #define IOP13XX_ATUX_OUMWTVR2           IOP13XX_ATUX_OFFSET(0x31c)
 283 #define IOP13XX_ATUX_OUMBAR3            IOP13XX_ATUX_OFFSET(0x320)
 284 #define IOP13XX_ATUX_OUMWTVR3           IOP13XX_ATUX_OFFSET(0x324)
 285 #define IOP13XX_ATUX_OUDMABAR           IOP13XX_ATUX_OFFSET(0x328)
 286 #define IOP13XX_ATUX_OUMSIBAR           IOP13XX_ATUX_OFFSET(0x32c)
 287 #define IOP13XX_ATUX_OCCAR              IOP13XX_ATUX_OFFSET(0x330)
 288 #define IOP13XX_ATUX_OCCDR              IOP13XX_ATUX_OFFSET(0x334)
 289
 290 #define IOP13XX_ATUX_ATUCR_OUT_EN               (1 << 1)
 291 #define IOP13XX_ATUX_PCSR_CENTRAL_RES           (1 << 25)
 292 #define IOP13XX_ATUX_PCSR_P_RSTOUT              (1 << 21)
 293 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY            (1 << 15)
 294 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY             (1 << 14)
 295 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET           (16)
 296
 297 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
 298 #define IOP13XX_ATUX_STAT_VPD_ADDR              (1 << 17)
 299 #define IOP13XX_ATUX_STAT_INT_PAR_ERR           (1 << 16)
 300 #define IOP13XX_ATUX_STAT_CFG_WRITE             (1 << 15)
 301 #define IOP13XX_ATUX_STAT_ERR_COR               (1 << 14)
 302 #define IOP13XX_ATUX_STAT_TX_SCEM               (1 << 13)
 303 #define IOP13XX_ATUX_STAT_REC_SCEM              (1 << 12)
 304 #define IOP13XX_ATUX_STAT_POWER_TRAN            (1 << 11)
 305 #define IOP13XX_ATUX_STAT_TX_SERR               (1 << 10)
 306 #define IOP13XX_ATUX_STAT_DET_PAR_ERR           (1 << 9 )
 307 #define IOP13XX_ATUX_STAT_BIST                  (1 << 8 )
 308 #define IOP13XX_ATUX_STAT_INT_REC_MABORT        (1 << 7 )
 309 #define IOP13XX_ATUX_STAT_REC_SERR              (1 << 4 )
 310 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT        (1 << 3 )
 311 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT        (1 << 2 )
 312 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT        (1 << 1 )
 313 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR       (1 << 0 )
 314
 315 #define IOP13XX_ATUX_PCIXSR_BUS_NUM     (8)
 316 #define IOP13XX_ATUX_PCIXSR_DEV_NUM     (3)
 317 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM    (0)
 318
 319 #define IOP13XX_ATUX_IALR_DISABLE       0x00000001
 320 #define IOP13XX_ATUX_OUMBAR_ENABLE      0x80000000
 321
 322 #define IOP13XX_ATUE_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
 323                                         iop13xx_atue_pmmr_offset + (ofs))
 324
 325 #define IOP13XX_ATUE_DID                IOP13XX_REG_ADDR16(\
 326                                         iop13xx_atue_pmmr_offset + 0x2)
 327 #define IOP13XX_ATUE_ATUCMD             IOP13XX_REG_ADDR16(\
 328                                         iop13xx_atue_pmmr_offset + 0x4)
 329 #define IOP13XX_ATUE_ATUSR              IOP13XX_REG_ADDR16(\
 330                                         iop13xx_atue_pmmr_offset + 0x6)
 331
 332 #define IOP13XX_ATUE_IABAR0             IOP13XX_ATUE_OFFSET(0x10)
 333 #define IOP13XX_ATUE_IAUBAR0            IOP13XX_ATUE_OFFSET(0x14)
 334 #define IOP13XX_ATUE_IABAR1             IOP13XX_ATUE_OFFSET(0x18)
 335 #define IOP13XX_ATUE_IAUBAR1            IOP13XX_ATUE_OFFSET(0x1c)
 336 #define IOP13XX_ATUE_IABAR2             IOP13XX_ATUE_OFFSET(0x20)
 337 #define IOP13XX_ATUE_IAUBAR2            IOP13XX_ATUE_OFFSET(0x24)
 338 #define IOP13XX_ATUE_IALR0              IOP13XX_ATUE_OFFSET(0x40)
 339 #define IOP13XX_ATUE_IATVR0             IOP13XX_ATUE_OFFSET(0x44)
 340 #define IOP13XX_ATUE_IAUTVR0            IOP13XX_ATUE_OFFSET(0x48)
 341 #define IOP13XX_ATUE_IALR1              IOP13XX_ATUE_OFFSET(0x4c)
 342 #define IOP13XX_ATUE_IATVR1             IOP13XX_ATUE_OFFSET(0x50)
 343 #define IOP13XX_ATUE_IAUTVR1            IOP13XX_ATUE_OFFSET(0x54)
 344 #define IOP13XX_ATUE_IALR2              IOP13XX_ATUE_OFFSET(0x58)
 345 #define IOP13XX_ATUE_IATVR2             IOP13XX_ATUE_OFFSET(0x5c)
 346 #define IOP13XX_ATUE_IAUTVR2            IOP13XX_ATUE_OFFSET(0x60)
 347 #define IOP13XX_ATUE_PE_LSTS            IOP13XX_REG_ADDR16(\
 348                                         iop13xx_atue_pmmr_offset + 0xe2)
 349 #define IOP13XX_ATUE_OIOWTVR            IOP13XX_ATUE_OFFSET(0x304)
 350 #define IOP13XX_ATUE_OUMBAR0            IOP13XX_ATUE_OFFSET(0x308)
 351 #define IOP13XX_ATUE_OUMWTVR0           IOP13XX_ATUE_OFFSET(0x30c)
 352 #define IOP13XX_ATUE_OUMBAR1            IOP13XX_ATUE_OFFSET(0x310)
 353 #define IOP13XX_ATUE_OUMWTVR1           IOP13XX_ATUE_OFFSET(0x314)
 354 #define IOP13XX_ATUE_OUMBAR2            IOP13XX_ATUE_OFFSET(0x318)
 355 #define IOP13XX_ATUE_OUMWTVR2           IOP13XX_ATUE_OFFSET(0x31c)
 356 #define IOP13XX_ATUE_OUMBAR3            IOP13XX_ATUE_OFFSET(0x320)
 357 #define IOP13XX_ATUE_OUMWTVR3           IOP13XX_ATUE_OFFSET(0x324)
 358
 359 #define IOP13XX_ATUE_ATUCR              IOP13XX_ATUE_OFFSET(0x70)
 360 #define IOP13XX_ATUE_PCSR               IOP13XX_ATUE_OFFSET(0x74)
 361 #define IOP13XX_ATUE_ATUISR             IOP13XX_ATUE_OFFSET(0x78)
 362 #define IOP13XX_ATUE_OIOBAR             IOP13XX_ATUE_OFFSET(0x300)
 363 #define IOP13XX_ATUE_OCCAR              IOP13XX_ATUE_OFFSET(0x32c)
 364 #define IOP13XX_ATUE_OCCDR              IOP13XX_ATUE_OFFSET(0x330)
 365
 366 #define IOP13XX_ATUE_PIE_STS            IOP13XX_ATUE_OFFSET(0x384)
 367 #define IOP13XX_ATUE_PIE_MSK            IOP13XX_ATUE_OFFSET(0x388)
 368
 369 #define IOP13XX_ATUE_ATUCR_IVM          (1 << 6)
 370 #define IOP13XX_ATUE_ATUCR_OUT_EN       (1 << 1)
 371 #define IOP13XX_ATUE_OCCAR_BUS_NUM      (24)
 372 #define IOP13XX_ATUE_OCCAR_DEV_NUM      (19)
 373 #define IOP13XX_ATUE_OCCAR_FUNC_NUM     (16)
 374 #define IOP13XX_ATUE_OCCAR_EXT_REG      (8)
 375 #define IOP13XX_ATUE_OCCAR_REG          (2)
 376
 377 #define IOP13XX_ATUE_PCSR_BUS_NUM       (24)
 378 #define IOP13XX_ATUE_PCSR_DEV_NUM       (19)
 379 #define IOP13XX_ATUE_PCSR_FUNC_NUM      (16)
 380 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY    (1 << 15)
 381 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY     (1 << 14)
 382 #define IOP13XX_ATUE_PCSR_END_POINT     (1 << 13)
 383 #define IOP13XX_ATUE_PCSR_LLRB_BUSY     (1 << 12)
 384
 385 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK          (0xff)
 386 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK          (0x1f)
 387 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
 388
 389 #define IOP13XX_ATUE_PCSR_CORE_RESET            (8)
 390 #define IOP13XX_ATUE_PCSR_FUNC_NUM              (16)
 391
 392 #define IOP13XX_ATUE_LSTS_TRAINING              (1 << 11)
 393 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG          (1 << 28)
 394 #define IOP13XX_ATUE_STAT_PME                   (1 << 27)
 395 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG          (1 << 26)
 396 #define IOP13XX_ATUE_STAT_IVM                   (1 << 25)
 397 #define IOP13XX_ATUE_STAT_BIST                  (1 << 24)
 398 #define IOP13XX_ATUE_STAT_CFG_WRITE             (1 << 18)
 399 #define IOP13XX_ATUE_STAT_VPD_ADDR              (1 << 17)
 400 #define IOP13XX_ATUE_STAT_POWER_TRAN            (1 << 16)
 401 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
 402 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR          (1 << 12)
 403 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG          (1 << 11)
 404 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
 405 #define IOP13XX_ATUE_STAT_ERR_COR               (1 << 9 )
 406 #define IOP13XX_ATUE_STAT_ERR_UNCOR             (1 << 8 )
 407 #define IOP13XX_ATUE_STAT_CRS                   (1 << 7 )
 408 #define IOP13XX_ATUE_STAT_LNK_DWN               (1 << 6 )
 409 #define IOP13XX_ATUE_STAT_INT_REC_MABORT        (1 << 5 )
 410 #define IOP13XX_ATUE_STAT_DET_PAR_ERR           (1 << 4 )
 411 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT        (1 << 3 )
 412 #define IOP13XX_ATUE_STAT_SIG_TABORT            (1 << 2 )
 413 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT        (1 << 1 )
 414 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR       (1 << 0 )
 415
 416 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ     (1 << 31)
 417 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT          (1 << 30)
 418 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP              (1 << 29)
 419 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR                   (1 << 28)
 420 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ          (1 << 20)
 421 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR         (1 << 19)
 422 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP            (1 << 18)
 423 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
 424 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP          (1 << 16)
 425 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT               (1 << 15)
 426 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT         (1 << 14)
 427 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR             (1 << 13)
 428 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP             (1 << 12)
 429 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR         (1 << 4 )
 430 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR         (1 << 0 )
 431
 432 #define IOP13XX_ATUE_IALR_DISABLE               (0x00000001)
 433 #define IOP13XX_ATUE_OUMBAR_ENABLE              (0x80000000)
 434 #define IOP13XX_ATU_OUMBAR_FUNC_NUM             (28)
 435 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK        (0x7)
 436 /*=======================================================================*/
 437
 438 /*==============================ADMA UNITS===============================*/
 439 #define IOP13XX_ADMA_PHYS_BASE(chan)    IOP13XX_REG_ADDR32_PHYS((chan << 9))
 440 #define IOP13XX_ADMA_UPPER_PA(chan)     (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
 441 #define IOP13XX_ADMA_OFFSET(chan, ofs)  IOP13XX_REG_ADDR32((chan << 9) + (ofs))
 442
 443 #define IOP13XX_ADMA_ACCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x0)
 444 #define IOP13XX_ADMA_ACSR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x4)
 445 #define IOP13XX_ADMA_ADAR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x8)
 446 #define IOP13XX_ADMA_IIPCR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x18)
 447 #define IOP13XX_ADMA_IIPAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x1c)
 448 #define IOP13XX_ADMA_IIPUAR(chan)    IOP13XX_ADMA_OFFSET(chan, 0x20)
 449 #define IOP13XX_ADMA_ANDAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x24)
 450 #define IOP13XX_ADMA_ADCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x28)
 451 #define IOP13XX_ADMA_CARMD(chan)     IOP13XX_ADMA_OFFSET(chan, 0x2c)
 452 #define IOP13XX_ADMA_ABCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x30)
 453 #define IOP13XX_ADMA_DLADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x34)
 454 #define IOP13XX_ADMA_DUADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x38)
 455 #define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
 456 #define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
 457
 458 /*==============================XSI BRIDGE===============================*/
 459 #define IOP13XX_XBG_BECSR               IOP13XX_REG_ADDR32(0x178c)
 460 #define IOP13XX_XBG_BERAR               IOP13XX_REG_ADDR32(0x1790)
 461 #define IOP13XX_XBG_BERUAR              IOP13XX_REG_ADDR32(0x1794)
 462 #define is_atue_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
 463                                         IOP13XX_PMMR_VIRT_TO_PHYS(\
 464                                         IOP13XX_ATUE_OCCDR))\
 465                                         && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
 466 #define is_atux_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
 467                                         IOP13XX_PMMR_VIRT_TO_PHYS(\
 468                                         IOP13XX_ATUX_OCCDR))\
 469                                         && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
 470 /*=======================================================================*/
 471
 472 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
 473                                                         (ofs))
 474
 475 #define IOP13XX_PBI_CR                  IOP13XX_PBI_OFFSET(0x0)
 476 #define IOP13XX_PBI_SR                  IOP13XX_PBI_OFFSET(0x4)
 477 #define IOP13XX_PBI_BAR0                IOP13XX_PBI_OFFSET(0x8)
 478 #define IOP13XX_PBI_LR0                 IOP13XX_PBI_OFFSET(0xc)
 479 #define IOP13XX_PBI_BAR1                IOP13XX_PBI_OFFSET(0x10)
 480 #define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
 481
 482 #define IOP13XX_TMR_TC                  0x01
 483 #define IOP13XX_TMR_EN                  0x02
 484 #define IOP13XX_TMR_RELOAD              0x04
 485 #define IOP13XX_TMR_PRIVILEGED          0x08
 486
 487 #define IOP13XX_TMR_RATIO_1_1           0x00
 488 #define IOP13XX_TMR_RATIO_4_1           0x10
 489 #define IOP13XX_TMR_RATIO_8_1           0x20
 490 #define IOP13XX_TMR_RATIO_16_1          0x30
 491
 492 #endif /* _IOP13XX_HW_H_ */