2 * simple driver for PWM (Pulse Width Modulator) controller
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/platform_device.h>
14 #include <linux/slab.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
18 #include <linux/pwm.h>
19 #include <linux/of_device.h>
21 /* i.MX1 and i.MX21 share the same PWM function block: */
23 #define MX1_PWMC 0x00 /* PWM Control Register */
24 #define MX1_PWMS 0x04 /* PWM Sample Register */
25 #define MX1_PWMP 0x08 /* PWM Period Register */
27 #define MX1_PWMC_EN (1 << 4)
29 /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
31 #define MX3_PWMCR 0x00 /* PWM Control Register */
32 #define MX3_PWMSAR 0x0C /* PWM Sample Register */
33 #define MX3_PWMPR 0x10 /* PWM Period Register */
34 #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
35 #define MX3_PWMCR_DOZEEN (1 << 24)
36 #define MX3_PWMCR_WAITEN (1 << 23)
37 #define MX3_PWMCR_DBGEN (1 << 22)
38 #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
39 #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
40 #define MX3_PWMCR_EN (1 << 0)
47 void __iomem
*mmio_base
;
51 int (*config
)(struct pwm_chip
*chip
,
52 struct pwm_device
*pwm
, int duty_ns
, int period_ns
);
53 void (*set_enable
)(struct pwm_chip
*chip
, bool enable
);
56 #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
58 static int imx_pwm_config_v1(struct pwm_chip
*chip
,
59 struct pwm_device
*pwm
, int duty_ns
, int period_ns
)
61 struct imx_chip
*imx
= to_imx_chip(chip
);
64 * The PWM subsystem allows for exact frequencies. However,
65 * I cannot connect a scope on my device to the PWM line and
66 * thus cannot provide the program the PWM controller
67 * exactly. Instead, I'm relying on the fact that the
68 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
69 * function group already. So I'll just modify the PWM sample
70 * register to follow the ratio of duty_ns vs. period_ns
73 * This is good enough for programming the brightness of
76 * The real implementation would divide PERCLK[0] first by
77 * both the prescaler (/1 .. /128) and then by CLKSEL
80 u32 max
= readl(imx
->mmio_base
+ MX1_PWMP
);
81 u32 p
= max
* duty_ns
/ period_ns
;
82 writel(max
- p
, imx
->mmio_base
+ MX1_PWMS
);
87 static void imx_pwm_set_enable_v1(struct pwm_chip
*chip
, bool enable
)
89 struct imx_chip
*imx
= to_imx_chip(chip
);
92 val
= readl(imx
->mmio_base
+ MX1_PWMC
);
99 writel(val
, imx
->mmio_base
+ MX1_PWMC
);
102 static int imx_pwm_config_v2(struct pwm_chip
*chip
,
103 struct pwm_device
*pwm
, int duty_ns
, int period_ns
)
105 struct imx_chip
*imx
= to_imx_chip(chip
);
106 unsigned long long c
;
107 unsigned long period_cycles
, duty_cycles
, prescale
;
110 c
= clk_get_rate(imx
->clk_per
);
112 do_div(c
, 1000000000);
115 prescale
= period_cycles
/ 0x10000 + 1;
117 period_cycles
/= prescale
;
118 c
= (unsigned long long)period_cycles
* duty_ns
;
119 do_div(c
, period_ns
);
123 * according to imx pwm RM, the real period value should be
124 * PERIOD value in PWMPR plus 2.
126 if (period_cycles
> 2)
131 writel(duty_cycles
, imx
->mmio_base
+ MX3_PWMSAR
);
132 writel(period_cycles
, imx
->mmio_base
+ MX3_PWMPR
);
134 cr
= MX3_PWMCR_PRESCALER(prescale
) |
135 MX3_PWMCR_DOZEEN
| MX3_PWMCR_WAITEN
|
136 MX3_PWMCR_DBGEN
| MX3_PWMCR_CLKSRC_IPG_HIGH
;
141 writel(cr
, imx
->mmio_base
+ MX3_PWMCR
);
146 static void imx_pwm_set_enable_v2(struct pwm_chip
*chip
, bool enable
)
148 struct imx_chip
*imx
= to_imx_chip(chip
);
151 val
= readl(imx
->mmio_base
+ MX3_PWMCR
);
156 val
&= ~MX3_PWMCR_EN
;
158 writel(val
, imx
->mmio_base
+ MX3_PWMCR
);
161 static int imx_pwm_config(struct pwm_chip
*chip
,
162 struct pwm_device
*pwm
, int duty_ns
, int period_ns
)
164 struct imx_chip
*imx
= to_imx_chip(chip
);
167 ret
= clk_prepare_enable(imx
->clk_ipg
);
171 ret
= imx
->config(chip
, pwm
, duty_ns
, period_ns
);
173 clk_disable_unprepare(imx
->clk_ipg
);
178 static int imx_pwm_enable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
180 struct imx_chip
*imx
= to_imx_chip(chip
);
183 ret
= clk_prepare_enable(imx
->clk_per
);
187 imx
->set_enable(chip
, true);
194 static void imx_pwm_disable(struct pwm_chip
*chip
, struct pwm_device
*pwm
)
196 struct imx_chip
*imx
= to_imx_chip(chip
);
198 imx
->set_enable(chip
, false);
200 clk_disable_unprepare(imx
->clk_per
);
204 static struct pwm_ops imx_pwm_ops
= {
205 .enable
= imx_pwm_enable
,
206 .disable
= imx_pwm_disable
,
207 .config
= imx_pwm_config
,
208 .owner
= THIS_MODULE
,
211 struct imx_pwm_data
{
212 int (*config
)(struct pwm_chip
*chip
,
213 struct pwm_device
*pwm
, int duty_ns
, int period_ns
);
214 void (*set_enable
)(struct pwm_chip
*chip
, bool enable
);
217 static struct imx_pwm_data imx_pwm_data_v1
= {
218 .config
= imx_pwm_config_v1
,
219 .set_enable
= imx_pwm_set_enable_v1
,
222 static struct imx_pwm_data imx_pwm_data_v2
= {
223 .config
= imx_pwm_config_v2
,
224 .set_enable
= imx_pwm_set_enable_v2
,
227 static const struct of_device_id imx_pwm_dt_ids
[] = {
228 { .compatible
= "fsl,imx1-pwm", .data
= &imx_pwm_data_v1
, },
229 { .compatible
= "fsl,imx27-pwm", .data
= &imx_pwm_data_v2
, },
232 MODULE_DEVICE_TABLE(of
, imx_pwm_dt_ids
);
234 static int imx_pwm_probe(struct platform_device
*pdev
)
236 const struct of_device_id
*of_id
=
237 of_match_device(imx_pwm_dt_ids
, &pdev
->dev
);
238 const struct imx_pwm_data
*data
;
239 struct imx_chip
*imx
;
246 imx
= devm_kzalloc(&pdev
->dev
, sizeof(*imx
), GFP_KERNEL
);
248 dev_err(&pdev
->dev
, "failed to allocate memory\n");
252 imx
->clk_per
= devm_clk_get(&pdev
->dev
, "per");
253 if (IS_ERR(imx
->clk_per
)) {
254 dev_err(&pdev
->dev
, "getting per clock failed with %ld\n",
255 PTR_ERR(imx
->clk_per
));
256 return PTR_ERR(imx
->clk_per
);
259 imx
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
260 if (IS_ERR(imx
->clk_ipg
)) {
261 dev_err(&pdev
->dev
, "getting ipg clock failed with %ld\n",
262 PTR_ERR(imx
->clk_ipg
));
263 return PTR_ERR(imx
->clk_ipg
);
266 imx
->chip
.ops
= &imx_pwm_ops
;
267 imx
->chip
.dev
= &pdev
->dev
;
271 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
273 dev_err(&pdev
->dev
, "no memory resource defined\n");
277 imx
->mmio_base
= devm_request_and_ioremap(&pdev
->dev
, r
);
278 if (imx
->mmio_base
== NULL
)
279 return -EADDRNOTAVAIL
;
282 imx
->config
= data
->config
;
283 imx
->set_enable
= data
->set_enable
;
285 ret
= pwmchip_add(&imx
->chip
);
289 platform_set_drvdata(pdev
, imx
);
293 static int imx_pwm_remove(struct platform_device
*pdev
)
295 struct imx_chip
*imx
;
297 imx
= platform_get_drvdata(pdev
);
301 return pwmchip_remove(&imx
->chip
);
304 static struct platform_driver imx_pwm_driver
= {
307 .of_match_table
= of_match_ptr(imx_pwm_dt_ids
),
309 .probe
= imx_pwm_probe
,
310 .remove
= imx_pwm_remove
,
313 module_platform_driver(imx_pwm_driver
);
315 MODULE_LICENSE("GPL v2");
316 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");