2 * Copyright (C) 2004 IBM Corporation
5 * Leendert van Doorn <leendert@watson.ibm.com>
6 * Dave Safford <safford@watson.ibm.com>
7 * Reiner Sailer <sailer@watson.ibm.com>
8 * Kylene Hall <kjhall@us.ibm.com>
10 * Maintained by: <tpmdd-devel@lists.sourceforge.net>
12 * Device driver for TCG/TCPA TPM (trusted platform module).
13 * Specifications at www.trustedcomputinggroup.org
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation, version 2 of the
22 #include <linux/platform_device.h>
23 #include <linux/slab.h>
26 /* National definitions */
29 TPM_NSC_BASE0_HI
= 0x60,
30 TPM_NSC_BASE0_LO
= 0x61,
31 TPM_NSC_BASE1_HI
= 0x62,
32 TPM_NSC_BASE1_LO
= 0x63
45 enum tpm_nsc_status_loc
{
53 NSC_STATUS_OBF
= 0x01, /* output buffer full */
54 NSC_STATUS_IBF
= 0x02, /* input buffer full */
55 NSC_STATUS_F0
= 0x04, /* F0 */
56 NSC_STATUS_A2
= 0x08, /* A2 */
57 NSC_STATUS_RDY
= 0x10, /* ready to receive command */
58 NSC_STATUS_IBR
= 0x20 /* ready to receive data */
62 enum tpm_nsc_cmd_mode
{
63 NSC_COMMAND_NORMAL
= 0x01, /* normal mode */
64 NSC_COMMAND_EOC
= 0x03,
65 NSC_COMMAND_CANCEL
= 0x22
73 * Wait for a certain status to appear
75 static int wait_for_stat(struct tpm_chip
*chip
, u8 mask
, u8 val
, u8
* data
)
77 struct tpm_nsc_priv
*priv
= dev_get_drvdata(&chip
->dev
);
80 /* status immediately available check */
81 *data
= inb(priv
->base
+ NSC_STATUS
);
82 if ((*data
& mask
) == val
)
86 stop
= jiffies
+ 10 * HZ
;
89 *data
= inb(priv
->base
+ 1);
90 if ((*data
& mask
) == val
)
93 while (time_before(jiffies
, stop
));
98 static int nsc_wait_for_ready(struct tpm_chip
*chip
)
100 struct tpm_nsc_priv
*priv
= dev_get_drvdata(&chip
->dev
);
104 /* status immediately available check */
105 status
= inb(priv
->base
+ NSC_STATUS
);
106 if (status
& NSC_STATUS_OBF
)
107 status
= inb(priv
->base
+ NSC_DATA
);
108 if (status
& NSC_STATUS_RDY
)
111 /* wait for status */
112 stop
= jiffies
+ 100;
115 status
= inb(priv
->base
+ NSC_STATUS
);
116 if (status
& NSC_STATUS_OBF
)
117 status
= inb(priv
->base
+ NSC_DATA
);
118 if (status
& NSC_STATUS_RDY
)
121 while (time_before(jiffies
, stop
));
123 dev_info(&chip
->dev
, "wait for ready failed\n");
128 static int tpm_nsc_recv(struct tpm_chip
*chip
, u8
* buf
, size_t count
)
130 struct tpm_nsc_priv
*priv
= dev_get_drvdata(&chip
->dev
);
139 if (wait_for_stat(chip
, NSC_STATUS_F0
, NSC_STATUS_F0
, &data
) < 0) {
140 dev_err(&chip
->dev
, "F0 timeout\n");
144 data
= inb(priv
->base
+ NSC_DATA
);
145 if (data
!= NSC_COMMAND_NORMAL
) {
146 dev_err(&chip
->dev
, "not in normal mode (0x%x)\n",
151 /* read the whole packet */
152 for (p
= buffer
; p
< &buffer
[count
]; p
++) {
154 (chip
, NSC_STATUS_OBF
, NSC_STATUS_OBF
, &data
) < 0) {
156 "OBF timeout (while reading data)\n");
159 if (data
& NSC_STATUS_F0
)
161 *p
= inb(priv
->base
+ NSC_DATA
);
164 if ((data
& NSC_STATUS_F0
) == 0 &&
165 (wait_for_stat(chip
, NSC_STATUS_F0
, NSC_STATUS_F0
, &data
) < 0)) {
166 dev_err(&chip
->dev
, "F0 not set\n");
170 data
= inb(priv
->base
+ NSC_DATA
);
171 if (data
!= NSC_COMMAND_EOC
) {
173 "expected end of command(0x%x)\n", data
);
177 native_size
= (__force __be32
*) (buf
+ 2);
178 size
= be32_to_cpu(*native_size
);
186 static int tpm_nsc_send(struct tpm_chip
*chip
, u8
* buf
, size_t count
)
188 struct tpm_nsc_priv
*priv
= dev_get_drvdata(&chip
->dev
);
193 * If we hit the chip with back to back commands it locks up
194 * and never set IBF. Hitting it with this "hammer" seems to
195 * fix it. Not sure why this is needed, we followed the flow
196 * chart in the manual to the letter.
198 outb(NSC_COMMAND_CANCEL
, priv
->base
+ NSC_COMMAND
);
200 if (nsc_wait_for_ready(chip
) != 0)
203 if (wait_for_stat(chip
, NSC_STATUS_IBF
, 0, &data
) < 0) {
204 dev_err(&chip
->dev
, "IBF timeout\n");
208 outb(NSC_COMMAND_NORMAL
, priv
->base
+ NSC_COMMAND
);
209 if (wait_for_stat(chip
, NSC_STATUS_IBR
, NSC_STATUS_IBR
, &data
) < 0) {
210 dev_err(&chip
->dev
, "IBR timeout\n");
214 for (i
= 0; i
< count
; i
++) {
215 if (wait_for_stat(chip
, NSC_STATUS_IBF
, 0, &data
) < 0) {
217 "IBF timeout (while writing data)\n");
220 outb(buf
[i
], priv
->base
+ NSC_DATA
);
223 if (wait_for_stat(chip
, NSC_STATUS_IBF
, 0, &data
) < 0) {
224 dev_err(&chip
->dev
, "IBF timeout\n");
227 outb(NSC_COMMAND_EOC
, priv
->base
+ NSC_COMMAND
);
232 static void tpm_nsc_cancel(struct tpm_chip
*chip
)
234 struct tpm_nsc_priv
*priv
= dev_get_drvdata(&chip
->dev
);
236 outb(NSC_COMMAND_CANCEL
, priv
->base
+ NSC_COMMAND
);
239 static u8
tpm_nsc_status(struct tpm_chip
*chip
)
241 struct tpm_nsc_priv
*priv
= dev_get_drvdata(&chip
->dev
);
243 return inb(priv
->base
+ NSC_STATUS
);
246 static bool tpm_nsc_req_canceled(struct tpm_chip
*chip
, u8 status
)
248 return (status
== NSC_STATUS_RDY
);
251 static const struct tpm_class_ops tpm_nsc
= {
252 .recv
= tpm_nsc_recv
,
253 .send
= tpm_nsc_send
,
254 .cancel
= tpm_nsc_cancel
,
255 .status
= tpm_nsc_status
,
256 .req_complete_mask
= NSC_STATUS_OBF
,
257 .req_complete_val
= NSC_STATUS_OBF
,
258 .req_canceled
= tpm_nsc_req_canceled
,
261 static struct platform_device
*pdev
= NULL
;
263 static void tpm_nsc_remove(struct device
*dev
)
265 struct tpm_chip
*chip
= dev_get_drvdata(dev
);
266 struct tpm_nsc_priv
*priv
= dev_get_drvdata(&chip
->dev
);
268 tpm_chip_unregister(chip
);
269 release_region(priv
->base
, 2);
272 static SIMPLE_DEV_PM_OPS(tpm_nsc_pm
, tpm_pm_suspend
, tpm_pm_resume
);
274 static struct platform_driver nsc_drv
= {
281 static inline int tpm_read_index(int base
, int index
)
284 return inb(base
+1) & 0xFF;
287 static inline void tpm_write_index(int base
, int index
, int value
)
290 outb(value
& 0xFF, base
+1);
293 static int __init
init_nsc(void)
297 int nscAddrBase
= TPM_ADDR
;
298 struct tpm_chip
*chip
;
300 struct tpm_nsc_priv
*priv
;
302 /* verify that it is a National part (SID) */
303 if (tpm_read_index(TPM_ADDR
, NSC_SID_INDEX
) != 0xEF) {
304 nscAddrBase
= (tpm_read_index(TPM_SUPERIO_ADDR
, 0x2C)<<8)|
305 (tpm_read_index(TPM_SUPERIO_ADDR
, 0x2B)&0xFE);
306 if (tpm_read_index(nscAddrBase
, NSC_SID_INDEX
) != 0xF6)
310 err
= platform_driver_register(&nsc_drv
);
314 hi
= tpm_read_index(nscAddrBase
, TPM_NSC_BASE0_HI
);
315 lo
= tpm_read_index(nscAddrBase
, TPM_NSC_BASE0_LO
);
318 /* enable the DPM module */
319 tpm_write_index(nscAddrBase
, NSC_LDC_INDEX
, 0x01);
321 pdev
= platform_device_alloc("tpm_nscl0", -1);
327 pdev
->num_resources
= 0;
328 pdev
->dev
.driver
= &nsc_drv
.driver
;
329 pdev
->dev
.release
= tpm_nsc_remove
;
331 if ((rc
= platform_device_add(pdev
)) < 0)
334 priv
= devm_kzalloc(&pdev
->dev
, sizeof(*priv
), GFP_KERNEL
);
342 if (request_region(base
, 2, "tpm_nsc0") == NULL
) {
347 chip
= tpmm_chip_alloc(&pdev
->dev
, &tpm_nsc
);
353 dev_set_drvdata(&chip
->dev
, priv
);
355 rc
= tpm_chip_register(chip
);
359 dev_dbg(&pdev
->dev
, "NSC TPM detected\n");
361 "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
362 tpm_read_index(nscAddrBase
,0x07), tpm_read_index(nscAddrBase
,0x20),
363 tpm_read_index(nscAddrBase
,0x27));
365 "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
366 tpm_read_index(nscAddrBase
,0x21), tpm_read_index(nscAddrBase
,0x25),
367 tpm_read_index(nscAddrBase
,0x26), tpm_read_index(nscAddrBase
,0x28));
368 dev_dbg(&pdev
->dev
, "NSC IO Base0 0x%x\n",
369 (tpm_read_index(nscAddrBase
,0x60) << 8) | tpm_read_index(nscAddrBase
,0x61));
370 dev_dbg(&pdev
->dev
, "NSC IO Base1 0x%x\n",
371 (tpm_read_index(nscAddrBase
,0x62) << 8) | tpm_read_index(nscAddrBase
,0x63));
372 dev_dbg(&pdev
->dev
, "NSC Interrupt number and wakeup 0x%x\n",
373 tpm_read_index(nscAddrBase
,0x70));
374 dev_dbg(&pdev
->dev
, "NSC IRQ type select 0x%x\n",
375 tpm_read_index(nscAddrBase
,0x71));
377 "NSC DMA channel select0 0x%x, select1 0x%x\n",
378 tpm_read_index(nscAddrBase
,0x74), tpm_read_index(nscAddrBase
,0x75));
381 "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
382 tpm_read_index(nscAddrBase
,0xF0), tpm_read_index(nscAddrBase
,0xF1),
383 tpm_read_index(nscAddrBase
,0xF2), tpm_read_index(nscAddrBase
,0xF3),
384 tpm_read_index(nscAddrBase
,0xF4), tpm_read_index(nscAddrBase
,0xF5),
385 tpm_read_index(nscAddrBase
,0xF6), tpm_read_index(nscAddrBase
,0xF7),
386 tpm_read_index(nscAddrBase
,0xF8), tpm_read_index(nscAddrBase
,0xF9));
389 "NSC TPM revision %d\n",
390 tpm_read_index(nscAddrBase
, 0x27) & 0x1F);
395 release_region(base
, 2);
397 platform_device_del(pdev
);
399 platform_device_put(pdev
);
401 platform_driver_unregister(&nsc_drv
);
405 static void __exit
cleanup_nsc(void)
408 tpm_nsc_remove(&pdev
->dev
);
409 platform_device_unregister(pdev
);
412 platform_driver_unregister(&nsc_drv
);
415 module_init(init_nsc
);
416 module_exit(cleanup_nsc
);
418 MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
419 MODULE_DESCRIPTION("TPM Driver");
420 MODULE_VERSION("2.0");
421 MODULE_LICENSE("GPL");