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Merge branch 'fix/pcm-hwptr' into for-linus
[linux/fpc-iii.git] / drivers / infiniband / hw / mlx4 / qp.c
blobc4a02648c8afe78ce6553e95fcc0742ed499274b
1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/log2.h>
35
36 #include <rdma/ib_cache.h>
37 #include <rdma/ib_pack.h>
38
39 #include <linux/mlx4/qp.h>
40
41 #include "mlx4_ib.h"
42 #include "user.h"
43
44 enum {
45 MLX4_IB_ACK_REQ_FREQ = 8,
46 };
47
48 enum {
49 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
50 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f
51 };
52
53 enum {
54 /*
55 * Largest possible UD header: send with GRH and immediate data.
56 */
57 MLX4_IB_UD_HEADER_SIZE = 72
58 };
59
60 struct mlx4_ib_sqp {
61 struct mlx4_ib_qp qp;
62 int pkey_index;
63 u32 qkey;
64 u32 send_psn;
65 struct ib_ud_header ud_header;
66 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
67 };
68
69 enum {
70 MLX4_IB_MIN_SQ_STRIDE = 6
71 };
72
73 static const __be32 mlx4_ib_opcode[] = {
74 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
75 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
76 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
77 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
78 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
79 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
80 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
81 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
82 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
83 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
84 [IB_WR_FAST_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
85 };
86
87 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
88 {
89 return container_of(mqp, struct mlx4_ib_sqp, qp);
90 }
91
92 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
93 {
94 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
95 qp->mqp.qpn <= dev->dev->caps.sqp_start + 3;
96 }
97
98 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
99 {
100 return qp->mqp.qpn >= dev->dev->caps.sqp_start &&
101 qp->mqp.qpn <= dev->dev->caps.sqp_start + 1;
102 }
103
104 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
105 {
106 return mlx4_buf_offset(&qp->buf, offset);
107 }
108
109 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
110 {
111 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
112 }
113
114 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
115 {
116 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
117 }
118
119 /*
120 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
121 * first four bytes of every 64 byte chunk with
122 * 0x7FFFFFF | (invalid_ownership_value << 31).
123 *
124 * When the max work request size is less than or equal to the WQE
125 * basic block size, as an optimization, we can stamp all WQEs with
126 * 0xffffffff, and skip the very first chunk of each WQE.
127 */
128 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n, int size)
129 {
130 __be32 *wqe;
131 int i;
132 int s;
133 int ind;
134 void *buf;
135 __be32 stamp;
136 struct mlx4_wqe_ctrl_seg *ctrl;
137
138 if (qp->sq_max_wqes_per_wr > 1) {
139 s = roundup(size, 1U << qp->sq.wqe_shift);
140 for (i = 0; i < s; i += 64) {
141 ind = (i >> qp->sq.wqe_shift) + n;
142 stamp = ind & qp->sq.wqe_cnt ? cpu_to_be32(0x7fffffff) :
143 cpu_to_be32(0xffffffff);
144 buf = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
145 wqe = buf + (i & ((1 << qp->sq.wqe_shift) - 1));
146 *wqe = stamp;
147 }
148 } else {
149 ctrl = buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
150 s = (ctrl->fence_size & 0x3f) << 4;
151 for (i = 64; i < s; i += 64) {
152 wqe = buf + i;
153 *wqe = cpu_to_be32(0xffffffff);
154 }
155 }
156 }
157
158 static void post_nop_wqe(struct mlx4_ib_qp *qp, int n, int size)
159 {
160 struct mlx4_wqe_ctrl_seg *ctrl;
161 struct mlx4_wqe_inline_seg *inl;
162 void *wqe;
163 int s;
164
165 ctrl = wqe = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
166 s = sizeof(struct mlx4_wqe_ctrl_seg);
167
168 if (qp->ibqp.qp_type == IB_QPT_UD) {
169 struct mlx4_wqe_datagram_seg *dgram = wqe + sizeof *ctrl;
170 struct mlx4_av *av = (struct mlx4_av *)dgram->av;
171 memset(dgram, 0, sizeof *dgram);
172 av->port_pd = cpu_to_be32((qp->port << 24) | to_mpd(qp->ibqp.pd)->pdn);
173 s += sizeof(struct mlx4_wqe_datagram_seg);
174 }
175
176 /* Pad the remainder of the WQE with an inline data segment. */
177 if (size > s) {
178 inl = wqe + s;
179 inl->byte_count = cpu_to_be32(1 << 31 | (size - s - sizeof *inl));
180 }
181 ctrl->srcrb_flags = 0;
182 ctrl->fence_size = size / 16;
183 /*
184 * Make sure descriptor is fully written before setting ownership bit
185 * (because HW can start executing as soon as we do).
186 */
187 wmb();
188
189 ctrl->owner_opcode = cpu_to_be32(MLX4_OPCODE_NOP | MLX4_WQE_CTRL_NEC) |
190 (n & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
191
192 stamp_send_wqe(qp, n + qp->sq_spare_wqes, size);
193 }
194
195 /* Post NOP WQE to prevent wrap-around in the middle of WR */
196 static inline unsigned pad_wraparound(struct mlx4_ib_qp *qp, int ind)
197 {
198 unsigned s = qp->sq.wqe_cnt - (ind & (qp->sq.wqe_cnt - 1));
199 if (unlikely(s < qp->sq_max_wqes_per_wr)) {
200 post_nop_wqe(qp, ind, s << qp->sq.wqe_shift);
201 ind += s;
202 }
203 return ind;
204 }
205
206 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
207 {
208 struct ib_event event;
209 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
210
211 if (type == MLX4_EVENT_TYPE_PATH_MIG)
212 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
213
214 if (ibqp->event_handler) {
215 event.device = ibqp->device;
216 event.element.qp = ibqp;
217 switch (type) {
218 case MLX4_EVENT_TYPE_PATH_MIG:
219 event.event = IB_EVENT_PATH_MIG;
220 break;
221 case MLX4_EVENT_TYPE_COMM_EST:
222 event.event = IB_EVENT_COMM_EST;
223 break;
224 case MLX4_EVENT_TYPE_SQ_DRAINED:
225 event.event = IB_EVENT_SQ_DRAINED;
226 break;
227 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
228 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
229 break;
230 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
231 event.event = IB_EVENT_QP_FATAL;
232 break;
233 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
234 event.event = IB_EVENT_PATH_MIG_ERR;
235 break;
236 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
237 event.event = IB_EVENT_QP_REQ_ERR;
238 break;
239 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
240 event.event = IB_EVENT_QP_ACCESS_ERR;
241 break;
242 default:
243 printk(KERN_WARNING "mlx4_ib: Unexpected event type %d "
244 "on QP %06x\n", type, qp->qpn);
245 return;
246 }
247
248 ibqp->event_handler(&event, ibqp->qp_context);
249 }
250 }
251
252 static int send_wqe_overhead(enum ib_qp_type type, u32 flags)
253 {
254 /*
255 * UD WQEs must have a datagram segment.
256 * RC and UC WQEs might have a remote address segment.
257 * MLX WQEs need two extra inline data segments (for the UD
258 * header and space for the ICRC).
259 */
260 switch (type) {
261 case IB_QPT_UD:
262 return sizeof (struct mlx4_wqe_ctrl_seg) +
263 sizeof (struct mlx4_wqe_datagram_seg) +
264 ((flags & MLX4_IB_QP_LSO) ? 64 : 0);
265 case IB_QPT_UC:
266 return sizeof (struct mlx4_wqe_ctrl_seg) +
267 sizeof (struct mlx4_wqe_raddr_seg);
268 case IB_QPT_RC:
269 return sizeof (struct mlx4_wqe_ctrl_seg) +
270 sizeof (struct mlx4_wqe_atomic_seg) +
271 sizeof (struct mlx4_wqe_raddr_seg);
272 case IB_QPT_SMI:
273 case IB_QPT_GSI:
274 return sizeof (struct mlx4_wqe_ctrl_seg) +
275 ALIGN(MLX4_IB_UD_HEADER_SIZE +
276 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
277 MLX4_INLINE_ALIGN) *
278 sizeof (struct mlx4_wqe_inline_seg),
279 sizeof (struct mlx4_wqe_data_seg)) +
280 ALIGN(4 +
281 sizeof (struct mlx4_wqe_inline_seg),
282 sizeof (struct mlx4_wqe_data_seg));
283 default:
284 return sizeof (struct mlx4_wqe_ctrl_seg);
285 }
286 }
287
288 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
289 int is_user, int has_srq, struct mlx4_ib_qp *qp)
290 {
291 /* Sanity check RQ size before proceeding */
292 if (cap->max_recv_wr > dev->dev->caps.max_wqes ||
293 cap->max_recv_sge > dev->dev->caps.max_rq_sg)
294 return -EINVAL;
295
296 if (has_srq) {
297 /* QPs attached to an SRQ should have no RQ */
298 if (cap->max_recv_wr)
299 return -EINVAL;
300
301 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
302 } else {
303 /* HW requires >= 1 RQ entry with >= 1 gather entry */
304 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge))
305 return -EINVAL;
306
307 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
308 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
309 qp->rq.wqe_shift = ilog2(qp->rq.max_gs * sizeof (struct mlx4_wqe_data_seg));
310 }
311
312 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
313 cap->max_recv_sge = qp->rq.max_gs;
314
315 return 0;
316 }
317
318 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
319 enum ib_qp_type type, struct mlx4_ib_qp *qp)
320 {
321 int s;
322
323 /* Sanity check SQ size before proceeding */
324 if (cap->max_send_wr > dev->dev->caps.max_wqes ||
325 cap->max_send_sge > dev->dev->caps.max_sq_sg ||
326 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
327 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
328 return -EINVAL;
329
330 /*
331 * For MLX transport we need 2 extra S/G entries:
332 * one for the header and one for the checksum at the end
333 */
334 if ((type == IB_QPT_SMI || type == IB_QPT_GSI) &&
335 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
336 return -EINVAL;
337
338 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
339 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
340 send_wqe_overhead(type, qp->flags);
341
342 if (s > dev->dev->caps.max_sq_desc_sz)
343 return -EINVAL;
344
345 /*
346 * Hermon supports shrinking WQEs, such that a single work
347 * request can include multiple units of 1 << wqe_shift. This
348 * way, work requests can differ in size, and do not have to
349 * be a power of 2 in size, saving memory and speeding up send
350 * WR posting. Unfortunately, if we do this then the
351 * wqe_index field in CQEs can't be used to look up the WR ID
352 * anymore, so we do this only if selective signaling is off.
353 *
354 * Further, on 32-bit platforms, we can't use vmap() to make
355 * the QP buffer virtually contigious. Thus we have to use
356 * constant-sized WRs to make sure a WR is always fully within
357 * a single page-sized chunk.
358 *
359 * Finally, we use NOP work requests to pad the end of the
360 * work queue, to avoid wrap-around in the middle of WR. We
361 * set NEC bit to avoid getting completions with error for
362 * these NOP WRs, but since NEC is only supported starting
363 * with firmware 2.2.232, we use constant-sized WRs for older
364 * firmware.
365 *
366 * And, since MLX QPs only support SEND, we use constant-sized
367 * WRs in this case.
368 *
369 * We look for the smallest value of wqe_shift such that the
370 * resulting number of wqes does not exceed device
371 * capabilities.
372 *
373 * We set WQE size to at least 64 bytes, this way stamping
374 * invalidates each WQE.
375 */
376 if (dev->dev->caps.fw_ver >= MLX4_FW_VER_WQE_CTRL_NEC &&
377 qp->sq_signal_bits && BITS_PER_LONG == 64 &&
378 type != IB_QPT_SMI && type != IB_QPT_GSI)
379 qp->sq.wqe_shift = ilog2(64);
380 else
381 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
382
383 for (;;) {
384 qp->sq_max_wqes_per_wr = DIV_ROUND_UP(s, 1U << qp->sq.wqe_shift);
385
386 /*
387 * We need to leave 2 KB + 1 WR of headroom in the SQ to
388 * allow HW to prefetch.
389 */
390 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + qp->sq_max_wqes_per_wr;
391 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr *
392 qp->sq_max_wqes_per_wr +
393 qp->sq_spare_wqes);
394
395 if (qp->sq.wqe_cnt <= dev->dev->caps.max_wqes)
396 break;
397
398 if (qp->sq_max_wqes_per_wr <= 1)
399 return -EINVAL;
400
401 ++qp->sq.wqe_shift;
402 }
403
404 qp->sq.max_gs = (min(dev->dev->caps.max_sq_desc_sz,
405 (qp->sq_max_wqes_per_wr << qp->sq.wqe_shift)) -
406 send_wqe_overhead(type, qp->flags)) /
407 sizeof (struct mlx4_wqe_data_seg);
408
409 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
410 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
411 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
412 qp->rq.offset = 0;
413 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
414 } else {
415 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
416 qp->sq.offset = 0;
417 }
418
419 cap->max_send_wr = qp->sq.max_post =
420 (qp->sq.wqe_cnt - qp->sq_spare_wqes) / qp->sq_max_wqes_per_wr;
421 cap->max_send_sge = min(qp->sq.max_gs,
422 min(dev->dev->caps.max_sq_sg,
423 dev->dev->caps.max_rq_sg));
424 /* We don't support inline sends for kernel QPs (yet) */
425 cap->max_inline_data = 0;
426
427 return 0;
428 }
429
430 static int set_user_sq_size(struct mlx4_ib_dev *dev,
431 struct mlx4_ib_qp *qp,
432 struct mlx4_ib_create_qp *ucmd)
433 {
434 /* Sanity check SQ size before proceeding */
435 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
436 ucmd->log_sq_stride >
437 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
438 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
439 return -EINVAL;
440
441 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
442 qp->sq.wqe_shift = ucmd->log_sq_stride;
443
444 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
445 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
446
447 return 0;
448 }
449
450 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
451 struct ib_qp_init_attr *init_attr,
452 struct ib_udata *udata, int sqpn, struct mlx4_ib_qp *qp)
453 {
454 int qpn;
455 int err;
456
457 mutex_init(&qp->mutex);
458 spin_lock_init(&qp->sq.lock);
459 spin_lock_init(&qp->rq.lock);
460
461 qp->state = IB_QPS_RESET;
462 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
463 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
464
465 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject, !!init_attr->srq, qp);
466 if (err)
467 goto err;
468
469 if (pd->uobject) {
470 struct mlx4_ib_create_qp ucmd;
471
472 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
473 err = -EFAULT;
474 goto err;
475 }
476
477 qp->sq_no_prefetch = ucmd.sq_no_prefetch;
478
479 err = set_user_sq_size(dev, qp, &ucmd);
480 if (err)
481 goto err;
482
483 qp->umem = ib_umem_get(pd->uobject->context, ucmd.buf_addr,
484 qp->buf_size, 0, 0);
485 if (IS_ERR(qp->umem)) {
486 err = PTR_ERR(qp->umem);
487 goto err;
488 }
489
490 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(qp->umem),
491 ilog2(qp->umem->page_size), &qp->mtt);
492 if (err)
493 goto err_buf;
494
495 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
496 if (err)
497 goto err_mtt;
498
499 if (!init_attr->srq) {
500 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
501 ucmd.db_addr, &qp->db);
502 if (err)
503 goto err_mtt;
504 }
505 } else {
506 qp->sq_no_prefetch = 0;
507
508 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
509 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
510
511 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
512 qp->flags |= MLX4_IB_QP_LSO;
513
514 err = set_kernel_sq_size(dev, &init_attr->cap, init_attr->qp_type, qp);
515 if (err)
516 goto err;
517
518 if (!init_attr->srq) {
519 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
520 if (err)
521 goto err;
522
523 *qp->db.db = 0;
524 }
525
526 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf)) {
527 err = -ENOMEM;
528 goto err_db;
529 }
530
531 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
532 &qp->mtt);
533 if (err)
534 goto err_buf;
535
536 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
537 if (err)
538 goto err_mtt;
539
540 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof (u64), GFP_KERNEL);
541 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof (u64), GFP_KERNEL);
542
543 if (!qp->sq.wrid || !qp->rq.wrid) {
544 err = -ENOMEM;
545 goto err_wrid;
546 }
547 }
548
549 if (sqpn) {
550 qpn = sqpn;
551 } else {
552 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn);
553 if (err)
554 goto err_wrid;
555 }
556
557 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
558 if (err)
559 goto err_qpn;
560
561 /*
562 * Hardware wants QPN written in big-endian order (after
563 * shifting) for send doorbell. Precompute this value to save
564 * a little bit when posting sends.
565 */
566 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
567
568 qp->mqp.event = mlx4_ib_qp_event;
569
570 return 0;
571
572 err_qpn:
573 if (!sqpn)
574 mlx4_qp_release_range(dev->dev, qpn, 1);
575
576 err_wrid:
577 if (pd->uobject) {
578 if (!init_attr->srq)
579 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context),
580 &qp->db);
581 } else {
582 kfree(qp->sq.wrid);
583 kfree(qp->rq.wrid);
584 }
585
586 err_mtt:
587 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
588
589 err_buf:
590 if (pd->uobject)
591 ib_umem_release(qp->umem);
592 else
593 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
594
595 err_db:
596 if (!pd->uobject && !init_attr->srq)
597 mlx4_db_free(dev->dev, &qp->db);
598
599 err:
600 return err;
601 }
602
603 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
604 {
605 switch (state) {
606 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
607 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
608 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
609 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
610 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
611 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
612 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
613 default: return -1;
614 }
615 }
616
617 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
618 {
619 if (send_cq == recv_cq)
620 spin_lock_irq(&send_cq->lock);
621 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
622 spin_lock_irq(&send_cq->lock);
623 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
624 } else {
625 spin_lock_irq(&recv_cq->lock);
626 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
627 }
628 }
629
630 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
631 {
632 if (send_cq == recv_cq)
633 spin_unlock_irq(&send_cq->lock);
634 else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
635 spin_unlock(&recv_cq->lock);
636 spin_unlock_irq(&send_cq->lock);
637 } else {
638 spin_unlock(&send_cq->lock);
639 spin_unlock_irq(&recv_cq->lock);
640 }
641 }
642
643 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
644 int is_user)
645 {
646 struct mlx4_ib_cq *send_cq, *recv_cq;
647
648 if (qp->state != IB_QPS_RESET)
649 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
650 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
651 printk(KERN_WARNING "mlx4_ib: modify QP %06x to RESET failed.\n",
652 qp->mqp.qpn);
653
654 send_cq = to_mcq(qp->ibqp.send_cq);
655 recv_cq = to_mcq(qp->ibqp.recv_cq);
656
657 mlx4_ib_lock_cqs(send_cq, recv_cq);
658
659 if (!is_user) {
660 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
661 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
662 if (send_cq != recv_cq)
663 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
664 }
665
666 mlx4_qp_remove(dev->dev, &qp->mqp);
667
668 mlx4_ib_unlock_cqs(send_cq, recv_cq);
669
670 mlx4_qp_free(dev->dev, &qp->mqp);
671
672 if (!is_sqp(dev, qp))
673 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
674
675 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
676
677 if (is_user) {
678 if (!qp->ibqp.srq)
679 mlx4_ib_db_unmap_user(to_mucontext(qp->ibqp.uobject->context),
680 &qp->db);
681 ib_umem_release(qp->umem);
682 } else {
683 kfree(qp->sq.wrid);
684 kfree(qp->rq.wrid);
685 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
686 if (!qp->ibqp.srq)
687 mlx4_db_free(dev->dev, &qp->db);
688 }
689 }
690
691 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
692 struct ib_qp_init_attr *init_attr,
693 struct ib_udata *udata)
694 {
695 struct mlx4_ib_dev *dev = to_mdev(pd->device);
696 struct mlx4_ib_sqp *sqp;
697 struct mlx4_ib_qp *qp;
698 int err;
699
700 /*
701 * We only support LSO and multicast loopback blocking, and
702 * only for kernel UD QPs.
703 */
704 if (init_attr->create_flags & ~(IB_QP_CREATE_IPOIB_UD_LSO |
705 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
706 return ERR_PTR(-EINVAL);
707
708 if (init_attr->create_flags &&
709 (pd->uobject || init_attr->qp_type != IB_QPT_UD))
710 return ERR_PTR(-EINVAL);
711
712 switch (init_attr->qp_type) {
713 case IB_QPT_RC:
714 case IB_QPT_UC:
715 case IB_QPT_UD:
716 {
717 qp = kzalloc(sizeof *qp, GFP_KERNEL);
718 if (!qp)
719 return ERR_PTR(-ENOMEM);
720
721 err = create_qp_common(dev, pd, init_attr, udata, 0, qp);
722 if (err) {
723 kfree(qp);
724 return ERR_PTR(err);
725 }
726
727 qp->ibqp.qp_num = qp->mqp.qpn;
728
729 break;
730 }
731 case IB_QPT_SMI:
732 case IB_QPT_GSI:
733 {
734 /* Userspace is not allowed to create special QPs: */
735 if (pd->uobject)
736 return ERR_PTR(-EINVAL);
737
738 sqp = kzalloc(sizeof *sqp, GFP_KERNEL);
739 if (!sqp)
740 return ERR_PTR(-ENOMEM);
741
742 qp = &sqp->qp;
743
744 err = create_qp_common(dev, pd, init_attr, udata,
745 dev->dev->caps.sqp_start +
746 (init_attr->qp_type == IB_QPT_SMI ? 0 : 2) +
747 init_attr->port_num - 1,
748 qp);
749 if (err) {
750 kfree(sqp);
751 return ERR_PTR(err);
752 }
753
754 qp->port = init_attr->port_num;
755 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 : 1;
756
757 break;
758 }
759 default:
760 /* Don't support raw QPs */
761 return ERR_PTR(-EINVAL);
762 }
763
764 return &qp->ibqp;
765 }
766
767 int mlx4_ib_destroy_qp(struct ib_qp *qp)
768 {
769 struct mlx4_ib_dev *dev = to_mdev(qp->device);
770 struct mlx4_ib_qp *mqp = to_mqp(qp);
771
772 if (is_qp0(dev, mqp))
773 mlx4_CLOSE_PORT(dev->dev, mqp->port);
774
775 destroy_qp_common(dev, mqp, !!qp->pd->uobject);
776
777 if (is_sqp(dev, mqp))
778 kfree(to_msqp(mqp));
779 else
780 kfree(mqp);
781
782 return 0;
783 }
784
785 static int to_mlx4_st(enum ib_qp_type type)
786 {
787 switch (type) {
788 case IB_QPT_RC: return MLX4_QP_ST_RC;
789 case IB_QPT_UC: return MLX4_QP_ST_UC;
790 case IB_QPT_UD: return MLX4_QP_ST_UD;
791 case IB_QPT_SMI:
792 case IB_QPT_GSI: return MLX4_QP_ST_MLX;
793 default: return -1;
794 }
795 }
796
797 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
798 int attr_mask)
799 {
800 u8 dest_rd_atomic;
801 u32 access_flags;
802 u32 hw_access_flags = 0;
803
804 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
805 dest_rd_atomic = attr->max_dest_rd_atomic;
806 else
807 dest_rd_atomic = qp->resp_depth;
808
809 if (attr_mask & IB_QP_ACCESS_FLAGS)
810 access_flags = attr->qp_access_flags;
811 else
812 access_flags = qp->atomic_rd_en;
813
814 if (!dest_rd_atomic)
815 access_flags &= IB_ACCESS_REMOTE_WRITE;
816
817 if (access_flags & IB_ACCESS_REMOTE_READ)
818 hw_access_flags |= MLX4_QP_BIT_RRE;
819 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
820 hw_access_flags |= MLX4_QP_BIT_RAE;
821 if (access_flags & IB_ACCESS_REMOTE_WRITE)
822 hw_access_flags |= MLX4_QP_BIT_RWE;
823
824 return cpu_to_be32(hw_access_flags);
825 }
826
827 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
828 int attr_mask)
829 {
830 if (attr_mask & IB_QP_PKEY_INDEX)
831 sqp->pkey_index = attr->pkey_index;
832 if (attr_mask & IB_QP_QKEY)
833 sqp->qkey = attr->qkey;
834 if (attr_mask & IB_QP_SQ_PSN)
835 sqp->send_psn = attr->sq_psn;
836 }
837
838 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
839 {
840 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
841 }
842
843 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_ah_attr *ah,
844 struct mlx4_qp_path *path, u8 port)
845 {
846 path->grh_mylmc = ah->src_path_bits & 0x7f;
847 path->rlid = cpu_to_be16(ah->dlid);
848 if (ah->static_rate) {
849 path->static_rate = ah->static_rate + MLX4_STAT_RATE_OFFSET;
850 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
851 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
852 --path->static_rate;
853 } else
854 path->static_rate = 0;
855 path->counter_index = 0xff;
856
857 if (ah->ah_flags & IB_AH_GRH) {
858 if (ah->grh.sgid_index >= dev->dev->caps.gid_table_len[port]) {
859 printk(KERN_ERR "sgid_index (%u) too large. max is %d\n",
860 ah->grh.sgid_index, dev->dev->caps.gid_table_len[port] - 1);
861 return -1;
862 }
863
864 path->grh_mylmc |= 1 << 7;
865 path->mgid_index = ah->grh.sgid_index;
866 path->hop_limit = ah->grh.hop_limit;
867 path->tclass_flowlabel =
868 cpu_to_be32((ah->grh.traffic_class << 20) |
869 (ah->grh.flow_label));
870 memcpy(path->rgid, ah->grh.dgid.raw, 16);
871 }
872
873 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
874 ((port - 1) << 6) | ((ah->sl & 0xf) << 2);
875
876 return 0;
877 }
878
879 static int __mlx4_ib_modify_qp(struct ib_qp *ibqp,
880 const struct ib_qp_attr *attr, int attr_mask,
881 enum ib_qp_state cur_state, enum ib_qp_state new_state)
882 {
883 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
884 struct mlx4_ib_qp *qp = to_mqp(ibqp);
885 struct mlx4_qp_context *context;
886 enum mlx4_qp_optpar optpar = 0;
887 int sqd_event;
888 int err = -EINVAL;
889
890 context = kzalloc(sizeof *context, GFP_KERNEL);
891 if (!context)
892 return -ENOMEM;
893
894 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
895 (to_mlx4_st(ibqp->qp_type) << 16));
896 context->flags |= cpu_to_be32(1 << 8); /* DE? */
897
898 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
899 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
900 else {
901 optpar |= MLX4_QP_OPTPAR_PM_STATE;
902 switch (attr->path_mig_state) {
903 case IB_MIG_MIGRATED:
904 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
905 break;
906 case IB_MIG_REARM:
907 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
908 break;
909 case IB_MIG_ARMED:
910 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
911 break;
912 }
913 }
914
915 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI)
916 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
917 else if (ibqp->qp_type == IB_QPT_UD) {
918 if (qp->flags & MLX4_IB_QP_LSO)
919 context->mtu_msgmax = (IB_MTU_4096 << 5) |
920 ilog2(dev->dev->caps.max_gso_sz);
921 else
922 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
923 } else if (attr_mask & IB_QP_PATH_MTU) {
924 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
925 printk(KERN_ERR "path MTU (%u) is invalid\n",
926 attr->path_mtu);
927 goto out;
928 }
929 context->mtu_msgmax = (attr->path_mtu << 5) |
930 ilog2(dev->dev->caps.max_msg_sz);
931 }
932
933 if (qp->rq.wqe_cnt)
934 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
935 context->rq_size_stride |= qp->rq.wqe_shift - 4;
936
937 if (qp->sq.wqe_cnt)
938 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
939 context->sq_size_stride |= qp->sq.wqe_shift - 4;
940
941 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
942 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
943
944 if (qp->ibqp.uobject)
945 context->usr_page = cpu_to_be32(to_mucontext(ibqp->uobject->context)->uar.index);
946 else
947 context->usr_page = cpu_to_be32(dev->priv_uar.index);
948
949 if (attr_mask & IB_QP_DEST_QPN)
950 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
951
952 if (attr_mask & IB_QP_PORT) {
953 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
954 !(attr_mask & IB_QP_AV)) {
955 mlx4_set_sched(&context->pri_path, attr->port_num);
956 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
957 }
958 }
959
960 if (attr_mask & IB_QP_PKEY_INDEX) {
961 context->pri_path.pkey_index = attr->pkey_index;
962 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
963 }
964
965 if (attr_mask & IB_QP_AV) {
966 if (mlx4_set_path(dev, &attr->ah_attr, &context->pri_path,
967 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
968 goto out;
969
970 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
971 MLX4_QP_OPTPAR_SCHED_QUEUE);
972 }
973
974 if (attr_mask & IB_QP_TIMEOUT) {
975 context->pri_path.ackto = attr->timeout << 3;
976 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
977 }
978
979 if (attr_mask & IB_QP_ALT_PATH) {
980 if (attr->alt_port_num == 0 ||
981 attr->alt_port_num > dev->dev->caps.num_ports)
982 goto out;
983
984 if (attr->alt_pkey_index >=
985 dev->dev->caps.pkey_table_len[attr->alt_port_num])
986 goto out;
987
988 if (mlx4_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
989 attr->alt_port_num))
990 goto out;
991
992 context->alt_path.pkey_index = attr->alt_pkey_index;
993 context->alt_path.ackto = attr->alt_timeout << 3;
994 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
995 }
996
997 context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pdn);
998 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
999
1000 /* Set "fast registration enabled" for all kernel QPs */
1001 if (!qp->ibqp.uobject)
1002 context->params1 |= cpu_to_be32(1 << 11);
1003
1004 if (attr_mask & IB_QP_RNR_RETRY) {
1005 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
1006 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
1007 }
1008
1009 if (attr_mask & IB_QP_RETRY_CNT) {
1010 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
1011 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
1012 }
1013
1014 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1015 if (attr->max_rd_atomic)
1016 context->params1 |=
1017 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
1018 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
1019 }
1020
1021 if (attr_mask & IB_QP_SQ_PSN)
1022 context->next_send_psn = cpu_to_be32(attr->sq_psn);
1023
1024 context->cqn_send = cpu_to_be32(to_mcq(ibqp->send_cq)->mcq.cqn);
1025
1026 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1027 if (attr->max_dest_rd_atomic)
1028 context->params2 |=
1029 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
1030 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
1031 }
1032
1033 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
1034 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
1035 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
1036 }
1037
1038 if (ibqp->srq)
1039 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
1040
1041 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1042 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
1043 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
1044 }
1045 if (attr_mask & IB_QP_RQ_PSN)
1046 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
1047
1048 context->cqn_recv = cpu_to_be32(to_mcq(ibqp->recv_cq)->mcq.cqn);
1049
1050 if (attr_mask & IB_QP_QKEY) {
1051 context->qkey = cpu_to_be32(attr->qkey);
1052 optpar |= MLX4_QP_OPTPAR_Q_KEY;
1053 }
1054
1055 if (ibqp->srq)
1056 context->srqn = cpu_to_be32(1 << 24 | to_msrq(ibqp->srq)->msrq.srqn);
1057
1058 if (!ibqp->srq && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1059 context->db_rec_addr = cpu_to_be64(qp->db.dma);
1060
1061 if (cur_state == IB_QPS_INIT &&
1062 new_state == IB_QPS_RTR &&
1063 (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI ||
1064 ibqp->qp_type == IB_QPT_UD)) {
1065 context->pri_path.sched_queue = (qp->port - 1) << 6;
1066 if (is_qp0(dev, qp))
1067 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
1068 else
1069 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
1070 }
1071
1072 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
1073 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
1074 sqd_event = 1;
1075 else
1076 sqd_event = 0;
1077
1078 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
1079 context->rlkey |= (1 << 4);
1080
1081 /*
1082 * Before passing a kernel QP to the HW, make sure that the
1083 * ownership bits of the send queue are set and the SQ
1084 * headroom is stamped so that the hardware doesn't start
1085 * processing stale work requests.
1086 */
1087 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
1088 struct mlx4_wqe_ctrl_seg *ctrl;
1089 int i;
1090
1091 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
1092 ctrl = get_send_wqe(qp, i);
1093 ctrl->owner_opcode = cpu_to_be32(1 << 31);
1094 if (qp->sq_max_wqes_per_wr == 1)
1095 ctrl->fence_size = 1 << (qp->sq.wqe_shift - 4);
1096
1097 stamp_send_wqe(qp, i, 1 << qp->sq.wqe_shift);
1098 }
1099 }
1100
1101 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
1102 to_mlx4_state(new_state), context, optpar,
1103 sqd_event, &qp->mqp);
1104 if (err)
1105 goto out;
1106
1107 qp->state = new_state;
1108
1109 if (attr_mask & IB_QP_ACCESS_FLAGS)
1110 qp->atomic_rd_en = attr->qp_access_flags;
1111 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1112 qp->resp_depth = attr->max_dest_rd_atomic;
1113 if (attr_mask & IB_QP_PORT)
1114 qp->port = attr->port_num;
1115 if (attr_mask & IB_QP_ALT_PATH)
1116 qp->alt_port = attr->alt_port_num;
1117
1118 if (is_sqp(dev, qp))
1119 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
1120
1121 /*
1122 * If we moved QP0 to RTR, bring the IB link up; if we moved
1123 * QP0 to RESET or ERROR, bring the link back down.
1124 */
1125 if (is_qp0(dev, qp)) {
1126 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
1127 if (mlx4_INIT_PORT(dev->dev, qp->port))
1128 printk(KERN_WARNING "INIT_PORT failed for port %d\n",
1129 qp->port);
1130
1131 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
1132 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
1133 mlx4_CLOSE_PORT(dev->dev, qp->port);
1134 }
1135
1136 /*
1137 * If we moved a kernel QP to RESET, clean up all old CQ
1138 * entries and reinitialize the QP.
1139 */
1140 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
1141 mlx4_ib_cq_clean(to_mcq(ibqp->recv_cq), qp->mqp.qpn,
1142 ibqp->srq ? to_msrq(ibqp->srq): NULL);
1143 if (ibqp->send_cq != ibqp->recv_cq)
1144 mlx4_ib_cq_clean(to_mcq(ibqp->send_cq), qp->mqp.qpn, NULL);
1145
1146 qp->rq.head = 0;
1147 qp->rq.tail = 0;
1148 qp->sq.head = 0;
1149 qp->sq.tail = 0;
1150 qp->sq_next_wqe = 0;
1151 if (!ibqp->srq)
1152 *qp->db.db = 0;
1153 }
1154
1155 out:
1156 kfree(context);
1157 return err;
1158 }
1159
1160 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1161 int attr_mask, struct ib_udata *udata)
1162 {
1163 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1164 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1165 enum ib_qp_state cur_state, new_state;
1166 int err = -EINVAL;
1167
1168 mutex_lock(&qp->mutex);
1169
1170 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
1171 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
1172
1173 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask))
1174 goto out;
1175
1176 if ((attr_mask & IB_QP_PORT) &&
1177 (attr->port_num == 0 || attr->port_num > dev->dev->caps.num_ports)) {
1178 goto out;
1179 }
1180
1181 if (attr_mask & IB_QP_PKEY_INDEX) {
1182 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
1183 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p])
1184 goto out;
1185 }
1186
1187 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1188 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
1189 goto out;
1190 }
1191
1192 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1193 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
1194 goto out;
1195 }
1196
1197 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1198 err = 0;
1199 goto out;
1200 }
1201
1202 err = __mlx4_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
1203
1204 out:
1205 mutex_unlock(&qp->mutex);
1206 return err;
1207 }
1208
1209 static int build_mlx_header(struct mlx4_ib_sqp *sqp, struct ib_send_wr *wr,
1210 void *wqe, unsigned *mlx_seg_len)
1211 {
1212 struct ib_device *ib_dev = &to_mdev(sqp->qp.ibqp.device)->ib_dev;
1213 struct mlx4_wqe_mlx_seg *mlx = wqe;
1214 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
1215 struct mlx4_ib_ah *ah = to_mah(wr->wr.ud.ah);
1216 u16 pkey;
1217 int send_size;
1218 int header_size;
1219 int spc;
1220 int i;
1221
1222 send_size = 0;
1223 for (i = 0; i < wr->num_sge; ++i)
1224 send_size += wr->sg_list[i].length;
1225
1226 ib_ud_header_init(send_size, mlx4_ib_ah_grh_present(ah), &sqp->ud_header);
1227
1228 sqp->ud_header.lrh.service_level =
1229 be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 28;
1230 sqp->ud_header.lrh.destination_lid = ah->av.dlid;
1231 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.g_slid & 0x7f);
1232 if (mlx4_ib_ah_grh_present(ah)) {
1233 sqp->ud_header.grh.traffic_class =
1234 (be32_to_cpu(ah->av.sl_tclass_flowlabel) >> 20) & 0xff;
1235 sqp->ud_header.grh.flow_label =
1236 ah->av.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
1237 sqp->ud_header.grh.hop_limit = ah->av.hop_limit;
1238 ib_get_cached_gid(ib_dev, be32_to_cpu(ah->av.port_pd) >> 24,
1239 ah->av.gid_index, &sqp->ud_header.grh.source_gid);
1240 memcpy(sqp->ud_header.grh.destination_gid.raw,
1241 ah->av.dgid, 16);
1242 }
1243
1244 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
1245 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
1246 (sqp->ud_header.lrh.destination_lid ==
1247 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
1248 (sqp->ud_header.lrh.service_level << 8));
1249 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1250
1251 switch (wr->opcode) {
1252 case IB_WR_SEND:
1253 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1254 sqp->ud_header.immediate_present = 0;
1255 break;
1256 case IB_WR_SEND_WITH_IMM:
1257 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1258 sqp->ud_header.immediate_present = 1;
1259 sqp->ud_header.immediate_data = wr->ex.imm_data;
1260 break;
1261 default:
1262 return -EINVAL;
1263 }
1264
1265 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1266 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1267 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1268 sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1269 if (!sqp->qp.ibqp.qp_num)
1270 ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index, &pkey);
1271 else
1272 ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->wr.ud.pkey_index, &pkey);
1273 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1274 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1275 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1276 sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1277 sqp->qkey : wr->wr.ud.remote_qkey);
1278 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1279
1280 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
1281
1282 if (0) {
1283 printk(KERN_ERR "built UD header of size %d:\n", header_size);
1284 for (i = 0; i < header_size / 4; ++i) {
1285 if (i % 8 == 0)
1286 printk(" [%02x] ", i * 4);
1287 printk(" %08x",
1288 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
1289 if ((i + 1) % 8 == 0)
1290 printk("\n");
1291 }
1292 printk("\n");
1293 }
1294
1295 /*
1296 * Inline data segments may not cross a 64 byte boundary. If
1297 * our UD header is bigger than the space available up to the
1298 * next 64 byte boundary in the WQE, use two inline data
1299 * segments to hold the UD header.
1300 */
1301 spc = MLX4_INLINE_ALIGN -
1302 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
1303 if (header_size <= spc) {
1304 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
1305 memcpy(inl + 1, sqp->header_buf, header_size);
1306 i = 1;
1307 } else {
1308 inl->byte_count = cpu_to_be32(1 << 31 | spc);
1309 memcpy(inl + 1, sqp->header_buf, spc);
1310
1311 inl = (void *) (inl + 1) + spc;
1312 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
1313 /*
1314 * Need a barrier here to make sure all the data is
1315 * visible before the byte_count field is set.
1316 * Otherwise the HCA prefetcher could grab the 64-byte
1317 * chunk with this inline segment and get a valid (!=
1318 * 0xffffffff) byte count but stale data, and end up
1319 * generating a packet with bad headers.
1320 *
1321 * The first inline segment's byte_count field doesn't
1322 * need a barrier, because it comes after a
1323 * control/MLX segment and therefore is at an offset
1324 * of 16 mod 64.
1325 */
1326 wmb();
1327 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
1328 i = 2;
1329 }
1330
1331 *mlx_seg_len =
1332 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
1333 return 0;
1334 }
1335
1336 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
1337 {
1338 unsigned cur;
1339 struct mlx4_ib_cq *cq;
1340
1341 cur = wq->head - wq->tail;
1342 if (likely(cur + nreq < wq->max_post))
1343 return 0;
1344
1345 cq = to_mcq(ib_cq);
1346 spin_lock(&cq->lock);
1347 cur = wq->head - wq->tail;
1348 spin_unlock(&cq->lock);
1349
1350 return cur + nreq >= wq->max_post;
1351 }
1352
1353 static __be32 convert_access(int acc)
1354 {
1355 return (acc & IB_ACCESS_REMOTE_ATOMIC ? cpu_to_be32(MLX4_WQE_FMR_PERM_ATOMIC) : 0) |
1356 (acc & IB_ACCESS_REMOTE_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_WRITE) : 0) |
1357 (acc & IB_ACCESS_REMOTE_READ ? cpu_to_be32(MLX4_WQE_FMR_PERM_REMOTE_READ) : 0) |
1358 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
1359 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
1360 }
1361
1362 static void set_fmr_seg(struct mlx4_wqe_fmr_seg *fseg, struct ib_send_wr *wr)
1363 {
1364 struct mlx4_ib_fast_reg_page_list *mfrpl = to_mfrpl(wr->wr.fast_reg.page_list);
1365 int i;
1366
1367 for (i = 0; i < wr->wr.fast_reg.page_list_len; ++i)
1368 mfrpl->mapped_page_list[i] =
1369 cpu_to_be64(wr->wr.fast_reg.page_list->page_list[i] |
1370 MLX4_MTT_FLAG_PRESENT);
1371
1372 fseg->flags = convert_access(wr->wr.fast_reg.access_flags);
1373 fseg->mem_key = cpu_to_be32(wr->wr.fast_reg.rkey);
1374 fseg->buf_list = cpu_to_be64(mfrpl->map);
1375 fseg->start_addr = cpu_to_be64(wr->wr.fast_reg.iova_start);
1376 fseg->reg_len = cpu_to_be64(wr->wr.fast_reg.length);
1377 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
1378 fseg->page_size = cpu_to_be32(wr->wr.fast_reg.page_shift);
1379 fseg->reserved[0] = 0;
1380 fseg->reserved[1] = 0;
1381 }
1382
1383 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
1384 {
1385 iseg->flags = 0;
1386 iseg->mem_key = cpu_to_be32(rkey);
1387 iseg->guest_id = 0;
1388 iseg->pa = 0;
1389 }
1390
1391 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
1392 u64 remote_addr, u32 rkey)
1393 {
1394 rseg->raddr = cpu_to_be64(remote_addr);
1395 rseg->rkey = cpu_to_be32(rkey);
1396 rseg->reserved = 0;
1397 }
1398
1399 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg, struct ib_send_wr *wr)
1400 {
1401 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1402 aseg->swap_add = cpu_to_be64(wr->wr.atomic.swap);
1403 aseg->compare = cpu_to_be64(wr->wr.atomic.compare_add);
1404 } else {
1405 aseg->swap_add = cpu_to_be64(wr->wr.atomic.compare_add);
1406 aseg->compare = 0;
1407 }
1408
1409 }
1410
1411 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
1412 struct ib_send_wr *wr)
1413 {
1414 memcpy(dseg->av, &to_mah(wr->wr.ud.ah)->av, sizeof (struct mlx4_av));
1415 dseg->dqpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1416 dseg->qkey = cpu_to_be32(wr->wr.ud.remote_qkey);
1417 }
1418
1419 static void set_mlx_icrc_seg(void *dseg)
1420 {
1421 u32 *t = dseg;
1422 struct mlx4_wqe_inline_seg *iseg = dseg;
1423
1424 t[1] = 0;
1425
1426 /*
1427 * Need a barrier here before writing the byte_count field to
1428 * make sure that all the data is visible before the
1429 * byte_count field is set. Otherwise, if the segment begins
1430 * a new cacheline, the HCA prefetcher could grab the 64-byte
1431 * chunk and get a valid (!= * 0xffffffff) byte count but
1432 * stale data, and end up sending the wrong data.
1433 */
1434 wmb();
1435
1436 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
1437 }
1438
1439 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1440 {
1441 dseg->lkey = cpu_to_be32(sg->lkey);
1442 dseg->addr = cpu_to_be64(sg->addr);
1443
1444 /*
1445 * Need a barrier here before writing the byte_count field to
1446 * make sure that all the data is visible before the
1447 * byte_count field is set. Otherwise, if the segment begins
1448 * a new cacheline, the HCA prefetcher could grab the 64-byte
1449 * chunk and get a valid (!= * 0xffffffff) byte count but
1450 * stale data, and end up sending the wrong data.
1451 */
1452 wmb();
1453
1454 dseg->byte_count = cpu_to_be32(sg->length);
1455 }
1456
1457 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
1458 {
1459 dseg->byte_count = cpu_to_be32(sg->length);
1460 dseg->lkey = cpu_to_be32(sg->lkey);
1461 dseg->addr = cpu_to_be64(sg->addr);
1462 }
1463
1464 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe, struct ib_send_wr *wr,
1465 struct mlx4_ib_qp *qp, unsigned *lso_seg_len,
1466 __be32 *lso_hdr_sz)
1467 {
1468 unsigned halign = ALIGN(sizeof *wqe + wr->wr.ud.hlen, 16);
1469
1470 /*
1471 * This is a temporary limitation and will be removed in
1472 * a forthcoming FW release:
1473 */
1474 if (unlikely(halign > 64))
1475 return -EINVAL;
1476
1477 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
1478 wr->num_sge > qp->sq.max_gs - (halign >> 4)))
1479 return -EINVAL;
1480
1481 memcpy(wqe->header, wr->wr.ud.header, wr->wr.ud.hlen);
1482
1483 *lso_hdr_sz = cpu_to_be32((wr->wr.ud.mss - wr->wr.ud.hlen) << 16 |
1484 wr->wr.ud.hlen);
1485 *lso_seg_len = halign;
1486 return 0;
1487 }
1488
1489 static __be32 send_ieth(struct ib_send_wr *wr)
1490 {
1491 switch (wr->opcode) {
1492 case IB_WR_SEND_WITH_IMM:
1493 case IB_WR_RDMA_WRITE_WITH_IMM:
1494 return wr->ex.imm_data;
1495
1496 case IB_WR_SEND_WITH_INV:
1497 return cpu_to_be32(wr->ex.invalidate_rkey);
1498
1499 default:
1500 return 0;
1501 }
1502 }
1503
1504 int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1505 struct ib_send_wr **bad_wr)
1506 {
1507 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1508 void *wqe;
1509 struct mlx4_wqe_ctrl_seg *ctrl;
1510 struct mlx4_wqe_data_seg *dseg;
1511 unsigned long flags;
1512 int nreq;
1513 int err = 0;
1514 unsigned ind;
1515 int uninitialized_var(stamp);
1516 int uninitialized_var(size);
1517 unsigned uninitialized_var(seglen);
1518 __be32 dummy;
1519 __be32 *lso_wqe;
1520 __be32 uninitialized_var(lso_hdr_sz);
1521 int i;
1522
1523 spin_lock_irqsave(&qp->sq.lock, flags);
1524
1525 ind = qp->sq_next_wqe;
1526
1527 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1528 lso_wqe = &dummy;
1529
1530 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1531 err = -ENOMEM;
1532 *bad_wr = wr;
1533 goto out;
1534 }
1535
1536 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
1537 err = -EINVAL;
1538 *bad_wr = wr;
1539 goto out;
1540 }
1541
1542 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
1543 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
1544
1545 ctrl->srcrb_flags =
1546 (wr->send_flags & IB_SEND_SIGNALED ?
1547 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1548 (wr->send_flags & IB_SEND_SOLICITED ?
1549 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1550 ((wr->send_flags & IB_SEND_IP_CSUM) ?
1551 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1552 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1553 qp->sq_signal_bits;
1554
1555 ctrl->imm = send_ieth(wr);
1556
1557 wqe += sizeof *ctrl;
1558 size = sizeof *ctrl / 16;
1559
1560 switch (ibqp->qp_type) {
1561 case IB_QPT_RC:
1562 case IB_QPT_UC:
1563 switch (wr->opcode) {
1564 case IB_WR_ATOMIC_CMP_AND_SWP:
1565 case IB_WR_ATOMIC_FETCH_AND_ADD:
1566 set_raddr_seg(wqe, wr->wr.atomic.remote_addr,
1567 wr->wr.atomic.rkey);
1568 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1569
1570 set_atomic_seg(wqe, wr);
1571 wqe += sizeof (struct mlx4_wqe_atomic_seg);
1572
1573 size += (sizeof (struct mlx4_wqe_raddr_seg) +
1574 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
1575
1576 break;
1577
1578 case IB_WR_RDMA_READ:
1579 case IB_WR_RDMA_WRITE:
1580 case IB_WR_RDMA_WRITE_WITH_IMM:
1581 set_raddr_seg(wqe, wr->wr.rdma.remote_addr,
1582 wr->wr.rdma.rkey);
1583 wqe += sizeof (struct mlx4_wqe_raddr_seg);
1584 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
1585 break;
1586
1587 case IB_WR_LOCAL_INV:
1588 ctrl->srcrb_flags |=
1589 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
1590 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
1591 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
1592 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
1593 break;
1594
1595 case IB_WR_FAST_REG_MR:
1596 ctrl->srcrb_flags |=
1597 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
1598 set_fmr_seg(wqe, wr);
1599 wqe += sizeof (struct mlx4_wqe_fmr_seg);
1600 size += sizeof (struct mlx4_wqe_fmr_seg) / 16;
1601 break;
1602
1603 default:
1604 /* No extra segments required for sends */
1605 break;
1606 }
1607 break;
1608
1609 case IB_QPT_UD:
1610 set_datagram_seg(wqe, wr);
1611 wqe += sizeof (struct mlx4_wqe_datagram_seg);
1612 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
1613
1614 if (wr->opcode == IB_WR_LSO) {
1615 err = build_lso_seg(wqe, wr, qp, &seglen, &lso_hdr_sz);
1616 if (unlikely(err)) {
1617 *bad_wr = wr;
1618 goto out;
1619 }
1620 lso_wqe = (__be32 *) wqe;
1621 wqe += seglen;
1622 size += seglen / 16;
1623 }
1624 break;
1625
1626 case IB_QPT_SMI:
1627 case IB_QPT_GSI:
1628 err = build_mlx_header(to_msqp(qp), wr, ctrl, &seglen);
1629 if (unlikely(err)) {
1630 *bad_wr = wr;
1631 goto out;
1632 }
1633 wqe += seglen;
1634 size += seglen / 16;
1635 break;
1636
1637 default:
1638 break;
1639 }
1640
1641 /*
1642 * Write data segments in reverse order, so as to
1643 * overwrite cacheline stamp last within each
1644 * cacheline. This avoids issues with WQE
1645 * prefetching.
1646 */
1647
1648 dseg = wqe;
1649 dseg += wr->num_sge - 1;
1650 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
1651
1652 /* Add one more inline data segment for ICRC for MLX sends */
1653 if (unlikely(qp->ibqp.qp_type == IB_QPT_SMI ||
1654 qp->ibqp.qp_type == IB_QPT_GSI)) {
1655 set_mlx_icrc_seg(dseg + 1);
1656 size += sizeof (struct mlx4_wqe_data_seg) / 16;
1657 }
1658
1659 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
1660 set_data_seg(dseg, wr->sg_list + i);
1661
1662 /*
1663 * Possibly overwrite stamping in cacheline with LSO
1664 * segment only after making sure all data segments
1665 * are written.
1666 */
1667 wmb();
1668 *lso_wqe = lso_hdr_sz;
1669
1670 ctrl->fence_size = (wr->send_flags & IB_SEND_FENCE ?
1671 MLX4_WQE_CTRL_FENCE : 0) | size;
1672
1673 /*
1674 * Make sure descriptor is fully written before
1675 * setting ownership bit (because HW can start
1676 * executing as soon as we do).
1677 */
1678 wmb();
1679
1680 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
1681 err = -EINVAL;
1682 goto out;
1683 }
1684
1685 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
1686 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0);
1687
1688 stamp = ind + qp->sq_spare_wqes;
1689 ind += DIV_ROUND_UP(size * 16, 1U << qp->sq.wqe_shift);
1690
1691 /*
1692 * We can improve latency by not stamping the last
1693 * send queue WQE until after ringing the doorbell, so
1694 * only stamp here if there are still more WQEs to post.
1695 *
1696 * Same optimization applies to padding with NOP wqe
1697 * in case of WQE shrinking (used to prevent wrap-around
1698 * in the middle of WR).
1699 */
1700 if (wr->next) {
1701 stamp_send_wqe(qp, stamp, size * 16);
1702 ind = pad_wraparound(qp, ind);
1703 }
1704 }
1705
1706 out:
1707 if (likely(nreq)) {
1708 qp->sq.head += nreq;
1709
1710 /*
1711 * Make sure that descriptors are written before
1712 * doorbell record.
1713 */
1714 wmb();
1715
1716 writel(qp->doorbell_qpn,
1717 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
1718
1719 /*
1720 * Make sure doorbells don't leak out of SQ spinlock
1721 * and reach the HCA out of order.
1722 */
1723 mmiowb();
1724
1725 stamp_send_wqe(qp, stamp, size * 16);
1726
1727 ind = pad_wraparound(qp, ind);
1728 qp->sq_next_wqe = ind;
1729 }
1730
1731 spin_unlock_irqrestore(&qp->sq.lock, flags);
1732
1733 return err;
1734 }
1735
1736 int mlx4_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1737 struct ib_recv_wr **bad_wr)
1738 {
1739 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1740 struct mlx4_wqe_data_seg *scat;
1741 unsigned long flags;
1742 int err = 0;
1743 int nreq;
1744 int ind;
1745 int i;
1746
1747 spin_lock_irqsave(&qp->rq.lock, flags);
1748
1749 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
1750
1751 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1752 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.send_cq)) {
1753 err = -ENOMEM;
1754 *bad_wr = wr;
1755 goto out;
1756 }
1757
1758 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1759 err = -EINVAL;
1760 *bad_wr = wr;
1761 goto out;
1762 }
1763
1764 scat = get_recv_wqe(qp, ind);
1765
1766 for (i = 0; i < wr->num_sge; ++i)
1767 __set_data_seg(scat + i, wr->sg_list + i);
1768
1769 if (i < qp->rq.max_gs) {
1770 scat[i].byte_count = 0;
1771 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
1772 scat[i].addr = 0;
1773 }
1774
1775 qp->rq.wrid[ind] = wr->wr_id;
1776
1777 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
1778 }
1779
1780 out:
1781 if (likely(nreq)) {
1782 qp->rq.head += nreq;
1783
1784 /*
1785 * Make sure that descriptors are written before
1786 * doorbell record.
1787 */
1788 wmb();
1789
1790 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
1791 }
1792
1793 spin_unlock_irqrestore(&qp->rq.lock, flags);
1794
1795 return err;
1796 }
1797
1798 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
1799 {
1800 switch (mlx4_state) {
1801 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
1802 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
1803 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
1804 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
1805 case MLX4_QP_STATE_SQ_DRAINING:
1806 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
1807 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
1808 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
1809 default: return -1;
1810 }
1811 }
1812
1813 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
1814 {
1815 switch (mlx4_mig_state) {
1816 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
1817 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
1818 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
1819 default: return -1;
1820 }
1821 }
1822
1823 static int to_ib_qp_access_flags(int mlx4_flags)
1824 {
1825 int ib_flags = 0;
1826
1827 if (mlx4_flags & MLX4_QP_BIT_RRE)
1828 ib_flags |= IB_ACCESS_REMOTE_READ;
1829 if (mlx4_flags & MLX4_QP_BIT_RWE)
1830 ib_flags |= IB_ACCESS_REMOTE_WRITE;
1831 if (mlx4_flags & MLX4_QP_BIT_RAE)
1832 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
1833
1834 return ib_flags;
1835 }
1836
1837 static void to_ib_ah_attr(struct mlx4_dev *dev, struct ib_ah_attr *ib_ah_attr,
1838 struct mlx4_qp_path *path)
1839 {
1840 memset(ib_ah_attr, 0, sizeof *ib_ah_attr);
1841 ib_ah_attr->port_num = path->sched_queue & 0x40 ? 2 : 1;
1842
1843 if (ib_ah_attr->port_num == 0 || ib_ah_attr->port_num > dev->caps.num_ports)
1844 return;
1845
1846 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
1847 ib_ah_attr->sl = (path->sched_queue >> 2) & 0xf;
1848 ib_ah_attr->src_path_bits = path->grh_mylmc & 0x7f;
1849 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
1850 ib_ah_attr->ah_flags = (path->grh_mylmc & (1 << 7)) ? IB_AH_GRH : 0;
1851 if (ib_ah_attr->ah_flags) {
1852 ib_ah_attr->grh.sgid_index = path->mgid_index;
1853 ib_ah_attr->grh.hop_limit = path->hop_limit;
1854 ib_ah_attr->grh.traffic_class =
1855 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
1856 ib_ah_attr->grh.flow_label =
1857 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
1858 memcpy(ib_ah_attr->grh.dgid.raw,
1859 path->rgid, sizeof ib_ah_attr->grh.dgid.raw);
1860 }
1861 }
1862
1863 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1864 struct ib_qp_init_attr *qp_init_attr)
1865 {
1866 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
1867 struct mlx4_ib_qp *qp = to_mqp(ibqp);
1868 struct mlx4_qp_context context;
1869 int mlx4_state;
1870 int err = 0;
1871
1872 mutex_lock(&qp->mutex);
1873
1874 if (qp->state == IB_QPS_RESET) {
1875 qp_attr->qp_state = IB_QPS_RESET;
1876 goto done;
1877 }
1878
1879 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
1880 if (err) {
1881 err = -EINVAL;
1882 goto out;
1883 }
1884
1885 mlx4_state = be32_to_cpu(context.flags) >> 28;
1886
1887 qp->state = to_ib_qp_state(mlx4_state);
1888 qp_attr->qp_state = qp->state;
1889 qp_attr->path_mtu = context.mtu_msgmax >> 5;
1890 qp_attr->path_mig_state =
1891 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
1892 qp_attr->qkey = be32_to_cpu(context.qkey);
1893 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
1894 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
1895 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
1896 qp_attr->qp_access_flags =
1897 to_ib_qp_access_flags(be32_to_cpu(context.params2));
1898
1899 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
1900 to_ib_ah_attr(dev->dev, &qp_attr->ah_attr, &context.pri_path);
1901 to_ib_ah_attr(dev->dev, &qp_attr->alt_ah_attr, &context.alt_path);
1902 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
1903 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
1904 }
1905
1906 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
1907 if (qp_attr->qp_state == IB_QPS_INIT)
1908 qp_attr->port_num = qp->port;
1909 else
1910 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
1911
1912 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
1913 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
1914
1915 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
1916
1917 qp_attr->max_dest_rd_atomic =
1918 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
1919 qp_attr->min_rnr_timer =
1920 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
1921 qp_attr->timeout = context.pri_path.ackto >> 3;
1922 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
1923 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
1924 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
1925
1926 done:
1927 qp_attr->cur_qp_state = qp_attr->qp_state;
1928 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
1929 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
1930
1931 if (!ibqp->uobject) {
1932 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
1933 qp_attr->cap.max_send_sge = qp->sq.max_gs;
1934 } else {
1935 qp_attr->cap.max_send_wr = 0;
1936 qp_attr->cap.max_send_sge = 0;
1937 }
1938
1939 /*
1940 * We don't support inline sends for kernel QPs (yet), and we
1941 * don't know what userspace's value should be.
1942 */
1943 qp_attr->cap.max_inline_data = 0;
1944
1945 qp_init_attr->cap = qp_attr->cap;
1946
1947 qp_init_attr->create_flags = 0;
1948 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1949 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
1950
1951 if (qp->flags & MLX4_IB_QP_LSO)
1952 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
1953
1954 out:
1955 mutex_unlock(&qp->mutex);
1956 return err;
1957 }
1958
Linux with added FPC-III support